usr.sbin/cxgbetool/tcbshowt6.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2018 Chelsio Communications, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #include <sys/cdefs.h>
  30 /* Auto-generated file.  Avoid direct editing.     */
  31 /* Edits will be lost when file regenerated.       */
  32 #include <stdio.h>
  33 #include "tcb_common.h"
  34
  35 void t6_display_tcb_aux_0 (_TCBVAR *tvp, int aux)
  36 {
  37
  38
  39
  40
  41
  42
  43
  44   PR("STATE:\n");
  45   PR("  %-12s (%-2u), %s, lock_tid %u, rss_fw %u\n",
  46               spr_tcp_state(val("t_state")),
  47               val("t_state"),
  48               spr_ip_version(val("ip_version")),
  49               val("lock_tid"),
  50               val("rss_fw")
  51              );
  52   PR("  l2t_ix 0x%x, smac sel 0x%x, tos 0x%x\n",
  53               val("l2t_ix"),
  54               val("smac_sel"),
  55               val("tos")
  56               );
  57   PR("  maxseg %u, recv_scaleflag %u, recv_tstmp %u, recv_sack %u\n",
  58               val("t_maxseg"),   val("recv_scale"),
  59               val("recv_tstmp"), val("recv_sack"));
  60
  61
  62   PR("TIMERS:\n"); /* **************************************** */
  63   PR("  timer    %u,  dack_timer      %u\n",
  64            val("timer"), val("dack_timer"));
  65   PR("  mod_schd: tx: %u, rx: %u, reason 0x%1x\n",
  66               val("mod_schd_tx"),
  67               val("mod_schd_rx"),
  68               ((val("mod_schd_reason2")<<2) | (val("mod_schd_reason1")<<1) |
  69                val("mod_schd_reason0"))
  70               );
  71
  72
  73   PR("  max_rt   %-2u, rxtshift        %u, keepalive   %u\n",
  74            val("max_rt"),  val("t_rxtshift"),
  75            val("keepalive"));
  76   PR("  timestamp_offset 0x%x,  timestamp 0x%x\n",
  77            val("timestamp_offset"),val("timestamp"));
  78
  79
  80   PR("  t_rtt_ts_recent_age %u  t_rttseq_recent %u\n",
  81            val("t_rtt_ts_recent_age"), val("t_rtseq_recent"));
  82   PR("  t_srtt %u, t_rttvar %u\n",
  83            val("t_srtt"),val("t_rttvar"));
  84
  85
  86
  87
  88
  89
  90   PR("TRANSMIT BUFFER:\n");   /* *************************** */
  91   PR("  snd_una %u, snd_nxt %u, snd_max %u, tx_max %u\n",
  92               val("snd_una"),val("snd_nxt"),
  93               val("snd_max"),val("tx_max"));
  94   PR("  core_fin %u, tx_hdr_offset %u\n",
  95               val("core_fin"), SEQ_SUB(val("tx_max"),val("snd_una"))
  96              );
  97   if (val("recv_scale") && !val("active_open")) {
  98     PR("  rcv_adv    %-5u << %-2u == %u (recv_scaleflag %u rcv_scale %u active open %u)\n",
  99                 val("rcv_adv"), val("rcv_scale"),
 100                 val("rcv_adv") << val("rcv_scale"),
 101                 val("recv_scale"), val("rcv_scale"), val("active_open"));
 102   } else {
 103     PR("  rcv_adv    %-5u (rcv_scale %-2u recv_scaleflag %u active_open %u)\n",
 104                 val("rcv_adv"), val("rcv_scale"),
 105                 val("recv_scale"), val("active_open"));
 106   }
 107
 108   PR("  snd_cwnd   %-5u  snd_ssthresh %u  snd_rec %u\n",
 109               val("snd_cwnd")    , val("snd_ssthresh"), val("snd_rec")
 110              );
 111
 112
 113
 114
 115   PR("  cctrl: sel %s, ecn %u, ece %u, cwr %u, rfr %u\n",
 116               spr_cctrl_sel(val("cctrl_sel0"),val("cctrl_sel1")),
 117               val("cctrl_ecn"), val("cctrl_ece"), val("cctrl_cwr"),
 118               val("cctrl_rfr"));
 119   PR("  t_dupacks %u, dupack_count_odd %u, fast_recovery %u\n",
 120               val("t_dupacks"), val("dupack_count_odd"),val("fast_recovery"));
 121   PR("  core_more    %u, core_urg,       %u  core_push   %u,",
 122               val("core_more"),val("core_urg"),val("core_push"));
 123   PR("  core_flush %u\n",val("core_flush"));
 124   PR("  nagle        %u, ssws_disable    %u, turbo       %u,",
 125               val("nagle"), val("ssws_disabled"), val("turbo"));
 126   PR("  tx_pdu_out %u\n",val("tx_pdu_out"));
 127   PR("  tx_pace_auto %u, tx_pace_fixed   %u, tx_queue    %u",
 128               val("tx_pace_auto"),val("tx_pace_fixed"),val("tx_queue"));
 129
 130
 131   PR("   tx_quiesce %u\n",val("tx_quiesce"));
 132   PR("  tx_channel   %u, tx_channel1     %u, tx_channel0 %u\n",
 133               val("tx_channel"),
 134               (val("tx_channel")>>1)&1,
 135               val("tx_channel")&1
 136               );
 137
 138
 139
 140
 141   PR("  tx_hdr_ptr   0x%-6x   tx_last_ptr 0x%-6x  tx_compact %u\n",
 142               val("tx_hdr_ptr"),val("tx_last_ptr"),val("tx_compact"));
 143
 144
 145
 146
 147   PR("RECEIVE BUFFER:\n");  /* *************************** */
 148   PR("  last_ack_sent %-10u                      rx_compact %u\n",
 149               val("ts_last_ack_sent"),val("rx_compact"));
 150   PR("  rcv_nxt       %-10u  hdr_off %-10u\n",
 151               val("rcv_nxt"), val("rx_hdr_offset"));
 152   PR("  frag0_idx     %-10u  length  %-10u  frag0_ptr  0x%-8x\n",
 153               val("rx_frag0_start_idx"),
 154               val("rx_frag0_len"),
 155               val("rx_ptr"));
 156   PR("  frag1_idx     %-10u  length  %-10u  ",
 157               val("rx_frag1_start_idx_offset"),
 158               val("rx_frag1_len"));
 159
 160
 161
 162
 163   if (val("ulp_type")!=4) { /* RDMA has FRAG1 idx && len, but no ptr?  Should I not display frag1 at all? */
 164     PR("frag1_ptr  0x%-8x\n",val("rx_frag1_ptr"));
 165   } else {
 166     PR("\n");
 167   }
 168
 169
 170   if (val("ulp_type") != 9 && val("ulp_type")!=8 && val("ulp_type") !=6 &&
 171       val("ulp_type") != 5 && val("ulp_type") !=4) {
 172     PR("  frag2_idx     %-10u  length  %-10u  frag2_ptr  0x%-8x\n",
 173                 val("rx_frag2_start_idx_offset"),
 174                 val("rx_frag2_len"),
 175                 val("rx_frag2_ptr"));
 176     PR("  frag3_idx     %-10u  length  %-10u  frag3_ptr  0x%-8x\n",
 177                 val("rx_frag3_start_idx_offset"),
 178                 val("rx_frag3_len"),
 179                 val("rx_frag3_ptr"));
 180   }
 181
 182
 183
 184
 185
 186
 187   PR("  peer_fin %u,   rx_pdu_out %u, pdu_len %u\n",
 188               val("peer_fin"),val("rx_pdu_out"), val("pdu_len"));
 189
 190
 191
 192
 193   if (val("recv_scale")) {
 194     PR("  rcv_wnd %u >> snd_scale %u == %u, recv_scaleflag = %u\n",
 195                 val("rcv_wnd"), val("snd_scale"),
 196                 val("rcv_wnd") >> val("snd_scale"),
 197                 val("recv_scale"));
 198   } else {
 199     PR("  rcv_wnd %u.  (snd_scale %u, recv_scaleflag = %u)\n",
 200                 val("rcv_wnd"), val("snd_scale"),
 201                 val("recv_scale"));
 202   }
 203
 204
 205
 206
 207  PR("  dack_mss   %u dack       %u,  dack_not_acked: %u\n",
 208               val("dack_mss"),val("dack"),val("dack_not_acked"));
 209   PR("  rcv_coal   %u rcv_co_psh %u rcv_co_last_psh  %u heart %u\n",
 210               val("rcv_coalesce_enable"),
 211               val("rcv_coalesce_push"),
 212               val("rcv_coalesce_last_psh"),
 213               val("rcv_coalesce_heartbeat"));
 214
 215   PR("  rx_channel %u rx_quiesce %u rx_flow_ctrl_dis %u,",
 216               val("rx_channel"), val("rx_quiesce"),
 217               val("rx_flow_control_disable"));
 218   PR("  rx_flow_ctrl_ddp %u\n",
 219               val("rx_flow_control_ddp"));
 220
 221
 222   PR("MISCELLANEOUS:\n");  /* *************************** */
 223   PR("  pend_ctl: 0x%1x, core_bypass: 0x%x,  main_slush: 0x%x\n",
 224               ((val("pend_ctl2")<<2) | (val("pend_ctl1")<<1) |
 225                val("pend_ctl0")),
 226               val("core_bypass"),val("main_slush"));
 227   PR("  Migrating %u, ask_mode %u, non_offload %u, rss_info %u\n",
 228               val("migrating"),
 229               val("ask_mode"), val("non_offload"), val("rss_info"));
 230   PR("  ULP: ulp_type %u (%s), ulp_raw %u",
 231               val("ulp_type"), spr_ulp_type(val("ulp_type")),
 232               val("ulp_raw"));
 233
 234
 235   if (aux==1) {
 236     PR(",  ulp_ext %u",val("ulp_ext"));
 237   }
 238   PR("\n");
 239
 240
 241
 242
 243   PR("  RDMA: error   %u, flm_err %u\n",
 244               val("rdma_error"), val("rdma_flm_error"));
 245
 246
 247 }
 248 void t6_display_tcb_aux_1 (_TCBVAR *tvp, int aux)
 249 {
 250
 251
 252
 253   PR("    aux1_slush0: 0x%x aux1_slush1 0x%x\n",
 254               val("aux1_slush0"), val("aux1_slush1"));
 255   PR("    pdu_hdr_len %u\n",val("pdu_hdr_len"));
 256
 257
 258
 259 }
 260 void t6_display_tcb_aux_2 (_TCBVAR *tvp, int aux)
 261 {
 262
 263
 264
 265
 266   PR("    qp_id %u, pd_id %u, stag %u\n",
 267                val("qp_id"), val("pd_id"),val("stag"));
 268   PR("    irs_ulp %u, iss_ulp %u\n",
 269               val("irs_ulp"),val("iss_ulp"));
 270   PR("    tx_pdu_len %u\n",
 271               val("tx_pdu_len"));
 272   PR("    cq_idx_sq %u, cq_idx_rq %u\n",
 273               val("cq_idx_sq"),val("cq_idx_rq"));
 274   PR("    rq_start %u, rq_MSN %u, rq_max_off %u, rq_write_ptr %u\n",
 275               val("rq_start"),val("rq_msn"),val("rq_max_offset"),
 276               val("rq_write_ptr"));
 277   PR("    L_valid %u, rdmap opcode %u\n",
 278               val("ord_l_bit_vld"),val("rdmap_opcode"));
 279   PR("    tx_flush: %u, tx_oos_rxmt %u, tx_oos_txmt %u\n",
 280               val("tx_flush"),val("tx_oos_rxmt"),val("tx_oos_txmt"));
 281
 282
 283
 284
 285 }
 286 void t6_display_tcb_aux_3 (_TCBVAR *tvp, int aux)
 287 {
 288
 289
 290
 291
 292
 293
 294   PR("  aux3_slush: 0x%x, unused: buf0 0x%x, buf1: 0x%x\n",
 295               val("aux3_slush"),val("ddp_buf0_unused"),val("ddp_buf1_unused"));
 296
 297
 298   PR("  ind_full: %u, tls_key_mode: %u\n",
 299               val("ddp_indicate_fll"),val("tls_key_mode"));
 300
 301
 302   PR("  DDP: DDPOFF  ActBuf  IndOut  WaitFrag  Rx2Tx  BufInf\n");
 303   PR("         %u       %u       %u        %u        %u      %u\n",
 304               val("ddp_off"),val("ddp_active_buf"),val("ddp_indicate_out"),
 305               val("ddp_wait_frag"),val("ddp_rx2tx"),val("ddp_buf_inf")
 306              );
 307
 308
 309   PR("        Ind  PshfEn PushDis Flush NoInvalidate\n");
 310   PR("   Buf0: %u      %u       %u    %u       %u\n",
 311               val("ddp_buf0_indicate"),
 312               val("ddp_pshf_enable_0"), val("ddp_push_disable_0"),
 313               val("ddp_buf0_flush"),  val("ddp_psh_no_invalidate0")
 314                );
 315   PR("   Buf1: %u      %u       %u    %u       %u\n",
 316               val("ddp_buf1_indicate"),
 317               val("ddp_pshf_enable_1"), val("ddp_push_disable_1"),
 318               val("ddp_buf1_flush"),  val("ddp_psh_no_invalidate1")
 319                );
 320
 321
 322
 323
 324
 325
 326
 327
 328
 329
 330   PR("        Valid  Offset   Length    Tag\n");
 331   PR("   Buf0:  %u    0x%6.6x 0x%6.6x  0x%8.8x",
 332               val("ddp_buf0_valid"),val("rx_ddp_buf0_offset"),
 333               val("rx_ddp_buf0_len"),val("rx_ddp_buf0_tag")
 334
 335
 336                );
 337   if      (0==val("ddp_off") && 1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) {
 338     PR("   (Active)\n");
 339   } else {
 340     PR(" (Inactive)\n");
 341   }
 342
 343
 344   PR("   Buf1:  %u    0x%6.6x 0x%6.6x  0x%8.8x",
 345               val("ddp_buf1_valid"),val("rx_ddp_buf1_offset"),
 346               val("rx_ddp_buf1_len"),val("rx_ddp_buf1_tag")
 347
 348
 349                );
 350
 351
 352   if      (0==val("ddp_off") && 1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
 353     PR("   (Active)\n");
 354   } else {
 355     PR(" (Inactive)\n");
 356   }
 357
 358
 359
 360
 361
 362
 363   if    (1==val("ddp_off")) {
 364     PR("   DDP is off (which also disables indicate)\n");
 365   } else if (1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) {
 366     PR("   Data being DDP'ed to buf 0, ");
 367     PR("which has %u - %u = %u bytes of space left\n",
 368                 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"),
 369                 val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset")
 370                );
 371     if (1==val("ddp_buf1_valid")) {
 372       PR("   And buf1, which is also valid, has %u - %u = %u bytes of space left\n",
 373                   val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"),
 374                   val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset")
 375                  );
 376     }
 377   } else if (1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
 378     PR("   Data being DDP'ed to buf 1, ");
 379     PR("which has %u - %u = %u bytes of space left\n",
 380                 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"),
 381                 val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset")
 382                );
 383     if (1==val("ddp_buf0_valid")) {
 384       PR("   And buf0, which is also valid, has %u - %u = %u bytes of space left\n",
 385                   val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"),
 386                   val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset")
 387                  );
 388     }
 389   } else if (0==val("ddp_buf0_valid") && 1==val("ddp_buf1_valid") && 0==val("ddp_active_buf")) {
 390     PR("   !!! Invalid DDP buf 1 valid, but buf 0 active.\n");
 391   } else if (1==val("ddp_buf0_valid") && 0==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
 392     PR("   !!! Invalid DDP buf 0 valid, but buf 1 active.\n");
 393   } else {
 394     PR("   DDP is enabled, but no buffers are active && valid.\n");
 395
 396
 397
 398
 399     if (0==val("ddp_indicate_out")) {
 400       if (0==val("ddp_buf0_indicate") && 0==val("ddp_buf1_indicate")) {
 401         PR("   0 length Indicate buffers ");
 402         if (0==val("rx_hdr_offset")) {
 403           PR("will cause new data to be held in PMRX.\n");
 404         } else {
 405           PR("is causing %u bytes to be held in PMRX\n",
 406                       val("rx_hdr_offset"));
 407         }
 408       } else {
 409         PR("   Data being indicated to host\n");
 410       }
 411     } else if (1==val("ddp_indicate_out")) {
 412       PR("   Indicate is off, which ");
 413       if (0==val("rx_hdr_offset")) {
 414         PR("will cause new data to be held in PMRX.\n");
 415       } else {
 416         PR("is causing %u bytes to be held in PMRX\n",
 417                     val("rx_hdr_offset"));
 418       }
 419     }
 420   }
 421
 422
 423
 424
 425 }
 426 void t6_display_tcb_aux_4 (_TCBVAR *tvp, int aux)
 427 {
 428
 429
 430
 431   PR("TLS:  offset: 0x%6.6x, len:0x%6.6x, flags: 0x%4.4x\n",
 432               val("rx_tls_buf_offset"),val("rx_tls_buf_len"),
 433               val("rx_tls_flags"));
 434   PR("      seq: 0x%llx \n",val64("rx_tls_seq"));
 435   PR("      tag: 0x%8.8x, key:0x%8.8x\n",
 436               val("rx_tls_buf_tag"),val("rx_tls_key_tag"));
 437
 438
 439
 440
 441 }