1 .\" Copyright (c) 1999 Chris Costello
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27 .Dd September 28, 1999
32 .Nd "control system cache behaviour with respect to memory"
54 A number of supported system architectures allow the behaviour of the CPU
55 cache to be programmed to behave differently depending on the region being
61 provides an interface to this facility, allowing CPU cache behavior to
62 be altered for ranges of system physical memory.
64 These ranges are typically power-of-2 aligned and sized, however the specific
65 rules governing their layout vary between architectures. The
67 utility does not attempt to enforce these rules, however the system will
68 reject any attempt to set an illegal combination.
72 .Bl -tag -width xxxxxx
74 List all range slots, even those that are inactive
77 Set memory range attributes.
78 .Bl -tag -width xxxxxx
80 Memory range base address
82 Length of memory range in bytes, power of 2
84 Text identifier for this setting (7 char max)
86 Attributes applied to this range; one of
94 Clear memory range attributes.
95 Ranges may be cleared by owner or by
96 base/length combination.
98 To clear based on ownership:
99 .Bl -tag -width xxxxxx
101 All ranges with this owner will be cleared
104 To clear based on the base/length combination:
105 .Bl -tag -width xxxxxx
107 Memory range base address
109 Length of memory range in bytes, power of 2
112 Base and length must exactly match an existing range.