2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2007 Yahoo!, Inc.
6 * Written by: John Baldwin <jhb@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 static const char rcsid[] =
38 #include <sys/types.h>
43 #include <sys/agpio.h>
44 #include <sys/pciio.h>
46 #include <dev/agp/agpreg.h>
47 #include <dev/pci/pcireg.h>
51 static void list_ecaps(int fd, struct pci_conf *p);
56 cap_power(int fd, struct pci_conf *p, uint8_t ptr)
60 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2);
61 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2);
62 printf("powerspec %d supports D0%s%s D3 current D%d",
64 cap & PCIM_PCAP_D1SUPP ? " D1" : "",
65 cap & PCIM_PCAP_D2SUPP ? " D2" : "",
66 status & PCIM_PSTAT_DMASK);
70 cap_agp(int fd, struct pci_conf *p, uint8_t ptr)
72 uint32_t status, command;
74 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4);
75 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4);
77 if (AGP_MODE_GET_MODE_3(status)) {
79 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x)
81 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x)
84 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x)
86 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x)
88 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x)
91 if (AGP_MODE_GET_SBA(status))
93 if (AGP_MODE_GET_AGP(command)) {
94 printf("enabled at ");
95 if (AGP_MODE_GET_MODE_3(command)) {
97 switch (AGP_MODE_GET_RATE(command)) {
98 case AGP_MODE_V3_RATE_8x:
101 case AGP_MODE_V3_RATE_4x:
106 switch (AGP_MODE_GET_RATE(command)) {
107 case AGP_MODE_V2_RATE_4x:
110 case AGP_MODE_V2_RATE_2x:
113 case AGP_MODE_V2_RATE_1x:
117 if (AGP_MODE_GET_SBA(command))
124 cap_vpd(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused)
131 cap_msi(int fd, struct pci_conf *p, uint8_t ptr)
136 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2);
137 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
138 printf("MSI supports %d message%s%s%s ", msgnum,
139 (msgnum == 1) ? "" : "s",
140 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
141 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : "");
142 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) {
143 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4);
144 printf("enabled with %d message%s", msgnum,
145 (msgnum == 1) ? "" : "s");
150 cap_pcix(int fd, struct pci_conf *p, uint8_t ptr)
153 int comma, max_splits, max_burst_read;
155 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4);
157 if (status & PCIXM_STATUS_64BIT)
159 if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
161 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP |
162 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0)
165 if (status & PCIXM_STATUS_133CAP) {
169 if (status & PCIXM_STATUS_266CAP) {
170 printf("%s 266MHz", comma ? "," : "");
173 if (status & PCIXM_STATUS_533CAP) {
174 printf("%s 533MHz", comma ? "," : "");
177 if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
180 switch (status & PCIXM_STATUS_MAX_READ) {
181 case PCIXM_STATUS_MAX_READ_512:
182 max_burst_read = 512;
184 case PCIXM_STATUS_MAX_READ_1024:
185 max_burst_read = 1024;
187 case PCIXM_STATUS_MAX_READ_2048:
188 max_burst_read = 2048;
190 case PCIXM_STATUS_MAX_READ_4096:
191 max_burst_read = 4096;
195 switch (status & PCIXM_STATUS_MAX_SPLITS) {
196 case PCIXM_STATUS_MAX_SPLITS_1:
199 case PCIXM_STATUS_MAX_SPLITS_2:
202 case PCIXM_STATUS_MAX_SPLITS_3:
205 case PCIXM_STATUS_MAX_SPLITS_4:
208 case PCIXM_STATUS_MAX_SPLITS_8:
211 case PCIXM_STATUS_MAX_SPLITS_12:
214 case PCIXM_STATUS_MAX_SPLITS_16:
217 case PCIXM_STATUS_MAX_SPLITS_32:
221 printf("%s %d burst read, %d split transaction%s", comma ? "," : "",
222 max_burst_read, max_splits, max_splits == 1 ? "" : "s");
226 cap_ht(int fd, struct pci_conf *p, uint8_t ptr)
231 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2);
233 if ((command & 0xe000) == PCIM_HTCAP_SLAVE)
235 else if ((command & 0xe000) == PCIM_HTCAP_HOST)
238 switch (command & PCIM_HTCMD_CAP_MASK) {
239 case PCIM_HTCAP_SWITCH:
242 case PCIM_HTCAP_INTERRUPT:
245 case PCIM_HTCAP_REVISION_ID:
246 printf("revision ID");
248 case PCIM_HTCAP_UNITID_CLUMPING:
249 printf("unit ID clumping");
251 case PCIM_HTCAP_EXT_CONFIG_SPACE:
252 printf("extended config space");
254 case PCIM_HTCAP_ADDRESS_MAPPING:
255 printf("address mapping");
257 case PCIM_HTCAP_MSI_MAPPING:
258 printf("MSI %saddress window %s at 0x",
259 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "",
260 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" :
262 if (command & PCIM_HTCMD_MSI_FIXED)
265 reg = read_config(fd, &p->pc_sel,
266 ptr + PCIR_HTMSI_ADDRESS_HI, 4);
269 reg = read_config(fd, &p->pc_sel,
270 ptr + PCIR_HTMSI_ADDRESS_LO, 4);
274 case PCIM_HTCAP_DIRECT_ROUTE:
275 printf("direct route");
277 case PCIM_HTCAP_VCSET:
280 case PCIM_HTCAP_RETRY_MODE:
281 printf("retry mode");
283 case PCIM_HTCAP_X86_ENCODING:
284 printf("X86 encoding");
286 case PCIM_HTCAP_GEN3:
290 printf("function-level extension");
293 printf("power management");
295 case PCIM_HTCAP_HIGH_NODE_COUNT:
296 printf("high node count");
299 printf("unknown %02x", command);
305 cap_vendor(int fd, struct pci_conf *p, uint8_t ptr)
309 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1);
310 printf("vendor (length %d)", length);
311 if (p->pc_vendor == 0x8086) {
315 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA,
317 printf(" Intel cap %d version %d", version >> 4, version & 0xf);
318 if (version >> 4 == 1 && length == 12) {
319 /* Feature Detection */
324 fvec = read_config(fd, &p->pc_sel, ptr +
325 PCIR_VENDOR_DATA + 5, 4);
326 printf("\n\t\t features:");
327 if (fvec & (1 << 0)) {
331 fvec = read_config(fd, &p->pc_sel, ptr +
332 PCIR_VENDOR_DATA + 1, 4);
333 if (fvec & (1 << 21)) {
334 printf("%s Quick Resume", comma ? "," : "");
337 if (fvec & (1 << 18)) {
338 printf("%s SATA RAID-5", comma ? "," : "");
341 if (fvec & (1 << 9)) {
342 printf("%s Mobile", comma ? "," : "");
345 if (fvec & (1 << 7)) {
346 printf("%s 6 PCI-e x1 slots", comma ? "," : "");
349 printf("%s 4 PCI-e x1 slots", comma ? "," : "");
352 if (fvec & (1 << 5)) {
353 printf("%s SATA RAID-0/1/10", comma ? "," : "");
357 printf(", SATA AHCI");
363 cap_debug(int fd, struct pci_conf *p, uint8_t ptr)
367 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2);
368 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port &
369 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13));
373 cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr)
376 uint16_t ssid, ssvid;
378 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4);
381 printf("PCI Bridge subvendor=0x%04x subdevice=0x%04x", ssvid, ssid);
384 #define MAX_PAYLOAD(field) (128 << (field))
387 link_speed_string(uint8_t speed)
405 max_read_string(u_int max_read)
427 aspm_string(uint8_t aspm)
443 slot_power(uint32_t cap)
447 mwatts = (cap & PCIEM_SLOT_CAP_SPLV) >> 7;
448 switch (cap & PCIEM_SLOT_CAP_SPLS) {
465 cap_express(int fd, struct pci_conf *p, uint8_t ptr)
468 uint16_t ctl, flags, sta;
469 unsigned int version;
471 flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2);
472 version = flags & PCIEM_FLAGS_VERSION;
473 printf("PCI-Express %u ", version);
474 switch (flags & PCIEM_FLAGS_TYPE) {
475 case PCIEM_TYPE_ENDPOINT:
478 case PCIEM_TYPE_LEGACY_ENDPOINT:
479 printf("legacy endpoint");
481 case PCIEM_TYPE_ROOT_PORT:
484 case PCIEM_TYPE_UPSTREAM_PORT:
485 printf("upstream port");
487 case PCIEM_TYPE_DOWNSTREAM_PORT:
488 printf("downstream port");
490 case PCIEM_TYPE_PCI_BRIDGE:
491 printf("PCI bridge");
493 case PCIEM_TYPE_PCIE_BRIDGE:
494 printf("PCI to PCIe bridge");
496 case PCIEM_TYPE_ROOT_INT_EP:
497 printf("root endpoint");
499 case PCIEM_TYPE_ROOT_EC:
500 printf("event collector");
503 printf("type %d", (flags & PCIEM_FLAGS_TYPE) >> 4);
506 if (flags & PCIEM_FLAGS_IRQ)
507 printf(" MSI %d", (flags & PCIEM_FLAGS_IRQ) >> 9);
508 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4);
509 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2);
510 printf(" max data %d(%d)",
511 MAX_PAYLOAD((ctl & PCIEM_CTL_MAX_PAYLOAD) >> 5),
512 MAX_PAYLOAD(cap & PCIEM_CAP_MAX_PAYLOAD));
513 if ((cap & PCIEM_CAP_FLR) != 0)
515 if (ctl & PCIEM_CTL_RELAXED_ORD_ENABLE)
517 if (ctl & PCIEM_CTL_NOSNOOP_ENABLE)
520 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP2, 4);
521 if ((cap & PCIEM_CAP2_ARI) != 0) {
522 ctl = read_config(fd, &p->pc_sel,
523 ptr + PCIER_DEVICE_CTL2, 4);
525 (ctl & PCIEM_CTL2_ARI) ? "enabled" : "disabled");
528 printf("\n max read %s", max_read_string((ctl &
529 PCIEM_CTL_MAX_READ_REQUEST) >> 12));
530 cap = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4);
531 sta = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_STA, 2);
532 if (cap == 0 && sta == 0)
535 printf(" link x%d(x%d)", (sta & PCIEM_LINK_STA_WIDTH) >> 4,
536 (cap & PCIEM_LINK_CAP_MAX_WIDTH) >> 4);
537 if ((cap & PCIEM_LINK_CAP_MAX_WIDTH) != 0) {
538 printf(" speed %s(%s)", (sta & PCIEM_LINK_STA_WIDTH) == 0 ?
539 "0.0" : link_speed_string(sta & PCIEM_LINK_STA_SPEED),
540 link_speed_string(cap & PCIEM_LINK_CAP_MAX_SPEED));
542 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
543 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2);
544 printf(" ASPM %s(%s)", aspm_string(ctl & PCIEM_LINK_CTL_ASPMC),
545 aspm_string((cap & PCIEM_LINK_CAP_ASPM) >> 10));
547 if ((cap & PCIEM_LINK_CAP_CLOCK_PM) != 0) {
548 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2);
549 printf(" ClockPM %s", (ctl & PCIEM_LINK_CTL_ECPM) ?
550 "enabled" : "disabled");
552 if (!(flags & PCIEM_FLAGS_SLOT))
554 cap = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CAP, 4);
555 sta = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_STA, 2);
556 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CTL, 2);
558 printf(" slot %d", (cap & PCIEM_SLOT_CAP_PSN) >> 19);
559 printf(" power limit %d mW", slot_power(cap));
560 if (cap & PCIEM_SLOT_CAP_HPC)
561 printf(" HotPlug(%s)", sta & PCIEM_SLOT_STA_PDS ? "present" :
563 if (cap & PCIEM_SLOT_CAP_HPS)
565 if (cap & PCIEM_SLOT_CAP_APB)
566 printf(" Attn Button");
567 if (cap & PCIEM_SLOT_CAP_PCP)
568 printf(" PC(%s)", ctl & PCIEM_SLOT_CTL_PCC ? "off" : "on");
569 if (cap & PCIEM_SLOT_CAP_MRLSP)
570 printf(" MRL(%s)", sta & PCIEM_SLOT_STA_MRLSS ? "open" :
572 if (cap & PCIEM_SLOT_CAP_EIP)
573 printf(" EI(%s)", sta & PCIEM_SLOT_STA_EIS ? "engaged" :
578 cap_msix(int fd, struct pci_conf *p, uint8_t ptr)
580 uint32_t pba_offset, table_offset, val;
581 int msgnum, pba_bar, table_bar;
584 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2);
585 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
587 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4);
588 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
589 table_offset = val & ~PCIM_MSIX_BIR_MASK;
591 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4);
592 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
593 pba_offset = val & ~PCIM_MSIX_BIR_MASK;
595 printf("MSI-X supports %d message%s%s\n", msgnum,
596 (msgnum == 1) ? "" : "s",
597 (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) ? ", enabled" : "");
600 printf("Table in map 0x%x[0x%x], PBA in map 0x%x[0x%x]",
601 table_bar, table_offset, pba_bar, pba_offset);
605 cap_sata(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused)
608 printf("SATA Index-Data Pair");
612 cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr)
616 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1);
617 printf("PCI Advanced Features:%s%s",
618 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "",
619 cap & PCIM_PCIAFCAP_TP ? " TP" : "");
623 ea_bei_to_name(int bei)
625 static const char *barstr[] = {
626 "BAR0", "BAR1", "BAR2", "BAR3", "BAR4", "BAR5"
628 static const char *vfbarstr[] = {
629 "VFBAR0", "VFBAR1", "VFBAR2", "VFBAR3", "VFBAR4", "VFBAR5"
632 if ((bei >= PCIM_EA_BEI_BAR_0) && (bei <= PCIM_EA_BEI_BAR_5))
633 return (barstr[bei - PCIM_EA_BEI_BAR_0]);
634 if ((bei >= PCIM_EA_BEI_VF_BAR_0) && (bei <= PCIM_EA_BEI_VF_BAR_5))
635 return (vfbarstr[bei - PCIM_EA_BEI_VF_BAR_0]);
638 case PCIM_EA_BEI_BRIDGE:
640 case PCIM_EA_BEI_ENI:
642 case PCIM_EA_BEI_ROM:
644 case PCIM_EA_BEI_RESERVED:
651 ea_prop_to_name(uint8_t prop)
656 return "Non-Prefetchable Memory";
657 case PCIM_EA_P_MEM_PREFETCH:
658 return "Prefetchable Memory";
661 case PCIM_EA_P_VF_MEM_PREFETCH:
662 return "VF Prefetchable Memory";
663 case PCIM_EA_P_VF_MEM:
664 return "VF Non-Prefetchable Memory";
665 case PCIM_EA_P_BRIDGE_MEM:
666 return "Bridge Non-Prefetchable Memory";
667 case PCIM_EA_P_BRIDGE_MEM_PREFETCH:
668 return "Bridge Prefetchable Memory";
669 case PCIM_EA_P_BRIDGE_IO:
670 return "Bridge I/O Space";
671 case PCIM_EA_P_MEM_RESERVED:
672 return "Reserved Memory";
673 case PCIM_EA_P_IO_RESERVED:
674 return "Reserved I/O Space";
675 case PCIM_EA_P_UNAVAILABLE:
676 return "Unavailable";
683 cap_ea(int fd, struct pci_conf *p, uint8_t ptr)
691 uint32_t flags, flags_pp, flags_sp;
692 uint64_t base, max_offset;
693 uint8_t fixed_sub_bus_nr, fixed_sec_bus_nr;
695 /* Determine the number of entries */
696 num_ent = read_config(fd, &p->pc_sel, ptr + PCIR_EA_NUM_ENT, 2);
697 num_ent &= PCIM_EA_NUM_ENT_MASK;
699 printf("PCI Enhanced Allocation (%d entries)", num_ent);
701 /* Find the first entry to care of */
702 ptr += PCIR_EA_FIRST_ENT;
704 /* Print BUS numbers for bridges */
705 if ((p->pc_hdr & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) {
706 val = read_config(fd, &p->pc_sel, ptr, 4);
708 fixed_sec_bus_nr = PCIM_EA_SEC_NR(val);
709 fixed_sub_bus_nr = PCIM_EA_SUB_NR(val);
711 printf("\n\t\t BRIDGE, sec bus [%d], sub bus [%d]",
712 fixed_sec_bus_nr, fixed_sub_bus_nr);
716 for (a = 0; a < num_ent; a++) {
717 /* Read a number of dwords in the entry */
718 val = read_config(fd, &p->pc_sel, ptr, 4);
720 ent_size = (val & PCIM_EA_ES);
722 for (b = 0; b < ent_size; b++) {
723 dw[b] = read_config(fd, &p->pc_sel, ptr, 4);
728 flags_pp = (flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET;
729 flags_sp = (flags & PCIM_EA_SP) >> PCIM_EA_SP_OFFSET;
730 bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET;
732 base = dw[0] & PCIM_EA_FIELD_MASK;
733 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK;
735 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) {
736 base |= (uint64_t)dw[b] << 32UL;
739 if (((dw[1] & PCIM_EA_IS_64) != 0)
741 max_offset |= (uint64_t)dw[b] << 32UL;
745 printf("\n\t\t [%d] %s, %s, %s, base [0x%jx], size [0x%jx]"
746 "\n\t\t\tPrimary properties [0x%x] (%s)"
747 "\n\t\t\tSecondary properties [0x%x] (%s)",
748 bei, ea_bei_to_name(bei),
749 (flags & PCIM_EA_ENABLE ? "Enabled" : "Disabled"),
750 (flags & PCIM_EA_WRITABLE ? "Writable" : "Read-only"),
751 (uintmax_t)base, (uintmax_t)(max_offset + 1),
752 flags_pp, ea_prop_to_name(flags_pp),
753 flags_sp, ea_prop_to_name(flags_sp));
758 list_caps(int fd, struct pci_conf *p, int level)
764 /* Are capabilities present for this device? */
765 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2);
766 if (!(sta & PCIM_STATUS_CAPPRESENT))
771 switch (p->pc_hdr & PCIM_HDRTYPE) {
772 case PCIM_HDRTYPE_NORMAL:
773 case PCIM_HDRTYPE_BRIDGE:
776 case PCIM_HDRTYPE_CARDBUS:
777 ptr = PCIR_CAP_PTR_2;
780 errx(1, "list_caps: bad header type");
783 /* Walk the capability list. */
785 ptr = read_config(fd, &p->pc_sel, ptr, 1);
786 while (ptr != 0 && ptr != 0xff) {
787 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
788 printf(" cap %02x[%02x] = ", cap, ptr);
791 cap_power(fd, p, ptr);
803 cap_pcix(fd, p, ptr);
809 cap_vendor(fd, p, ptr);
812 cap_debug(fd, p, ptr);
815 cap_subvendor(fd, p, ptr);
819 cap_express(fd, p, ptr);
822 cap_msix(fd, p, ptr);
825 cap_sata(fd, p, ptr);
828 cap_pciaf(fd, p, ptr);
838 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);
845 /* From <sys/systm.h>. */
846 static __inline uint32_t
847 bitcount32(uint32_t x)
850 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1);
851 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2);
852 x = (x + (x >> 4)) & 0x0f0f0f0f;
854 x = (x + (x >> 16)) & 0x000000ff;
859 ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
863 printf("AER %d", ver);
868 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4);
869 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4);
870 printf(" %d fatal", bitcount32(sta & mask));
871 printf(" %d non-fatal", bitcount32(sta & ~mask));
872 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4);
873 printf(" %d corrected\n", bitcount32(sta));
877 ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
881 printf("VC %d", ver);
886 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4);
887 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT);
888 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0)
889 printf(" lowpri VC0-VC%d",
890 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4);
895 ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
899 printf("Serial %d", ver);
904 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4);
905 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4);
906 printf(" %08x%08x\n", high, low);
910 ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
913 uint16_t nextptr, len;
916 val = read_config(fd, &p->pc_sel, ptr, 4);
917 nextptr = PCI_EXTCAP_NEXTPTR(val);
918 hdr = read_config(fd, &p->pc_sel, ptr + PCIR_VSEC_HEADER, 4);
919 len = PCIR_VSEC_LENGTH(hdr);
926 printf("Vendor [%d] ID %04x Rev %d Length %d\n", ver,
927 PCIR_VSEC_ID(hdr), PCIR_VSEC_REV(hdr), len);
928 if ((ver < 1) || (cap_level <= 1))
930 for (i = 0; i < len; i += 4) {
931 val = read_config(fd, &p->pc_sel, ptr + i, 4);
934 printf("%02x %02x %02x %02x", val & 0xff, (val >> 8) & 0xff,
935 (val >> 16) & 0xff, (val >> 24) & 0xff);
936 if ((((i + 4) % 16) == 0 ) || ((i + 4) >= len))
944 ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
948 printf("PCIe Sec %d", ver);
953 val = read_config(fd, &p->pc_sel, ptr + 8, 4);
954 printf(" lane errors %#x\n", val);
958 check_enabled(int value)
961 return (value ? "enabled" : "disabled");
965 ecap_sriov(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
967 const char *comma, *enabled;
968 uint16_t iov_ctl, total_vfs, num_vfs, vf_offset, vf_stride, vf_did;
969 uint32_t page_caps, page_size, page_shift, size;
972 printf("SR-IOV %d ", ver);
974 iov_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_CTL, 2);
975 printf("IOV %s, Memory Space %s, ARI %s\n",
976 check_enabled(iov_ctl & PCIM_SRIOV_VF_EN),
977 check_enabled(iov_ctl & PCIM_SRIOV_VF_MSE),
978 check_enabled(iov_ctl & PCIM_SRIOV_ARI_EN));
980 total_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_TOTAL_VFS, 2);
981 num_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_NUM_VFS, 2);
983 printf("%d VFs configured out of %d supported\n", num_vfs, total_vfs);
985 vf_offset = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_OFF, 2);
986 vf_stride = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_STRIDE, 2);
988 printf("First VF RID Offset 0x%04x, VF RID Stride 0x%04x\n", vf_offset,
991 vf_did = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_DID, 2);
992 printf(" VF Device ID 0x%04x\n", vf_did);
994 page_caps = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_CAP, 4);
995 page_size = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_SIZE, 4);
997 printf("Page Sizes: ");
999 while (page_caps != 0) {
1000 page_shift = ffs(page_caps) - 1;
1002 if (page_caps & page_size)
1003 enabled = " (enabled)";
1007 size = (1 << (page_shift + PCI_SRIOV_BASE_PAGE_SHIFT));
1008 printf("%s%d%s", comma, size, enabled);
1011 page_caps &= ~(1 << page_shift);
1015 for (i = 0; i <= PCIR_MAX_BAR_0; i++)
1016 print_bar(fd, p, "iov bar ", ptr + PCIR_SRIOV_BAR(i));
1023 { PCIZ_AER, "AER" },
1024 { PCIZ_VC, "Virtual Channel" },
1025 { PCIZ_SERNUM, "Device Serial Number" },
1026 { PCIZ_PWRBDGT, "Power Budgeting" },
1027 { PCIZ_RCLINK_DCL, "Root Complex Link Declaration" },
1028 { PCIZ_RCLINK_CTL, "Root Complex Internal Link Control" },
1029 { PCIZ_RCEC_ASSOC, "Root Complex Event Collector ASsociation" },
1030 { PCIZ_MFVC, "MFVC" },
1031 { PCIZ_VC2, "Virtual Channel 2" },
1032 { PCIZ_RCRB, "RCRB" },
1033 { PCIZ_CAC, "Configuration Access Correction" },
1034 { PCIZ_ACS, "ACS" },
1035 { PCIZ_ARI, "ARI" },
1036 { PCIZ_ATS, "ATS" },
1037 { PCIZ_SRIOV, "SRIOV" },
1038 { PCIZ_MRIOV, "MRIOV" },
1039 { PCIZ_MULTICAST, "Multicast" },
1040 { PCIZ_PAGE_REQ, "Page Page Request" },
1041 { PCIZ_AMD, "AMD proprietary "},
1042 { PCIZ_RESIZE_BAR, "Resizable BAR" },
1043 { PCIZ_DPA, "DPA" },
1044 { PCIZ_TPH_REQ, "TPH Requester" },
1045 { PCIZ_LTR, "LTR" },
1046 { PCIZ_SEC_PCIE, "Secondary PCI Express" },
1047 { PCIZ_PMUX, "Protocol Multiplexing" },
1048 { PCIZ_PASID, "Process Address Space ID" },
1049 { PCIZ_LN_REQ, "LN Requester" },
1050 { PCIZ_DPC, "Downstream Port Containment" },
1051 { PCIZ_L1PM, "L1 PM Substates" },
1052 { PCIZ_PTM, "Precision Time Measurement" },
1053 { PCIZ_M_PCIE, "PCIe over M-PHY" },
1054 { PCIZ_FRS, "FRS Queuing" },
1055 { PCIZ_RTR, "Readiness Time Reporting" },
1056 { PCIZ_DVSEC, "Designated Vendor-Specific" },
1057 { PCIZ_VF_REBAR, "VF Resizable BAR" },
1058 { PCIZ_DLNK, "Data Link Feature" },
1059 { PCIZ_16GT, "Physical Layer 16.0 GT/s" },
1060 { PCIZ_LMR, "Lane Margining at Receiver" },
1061 { PCIZ_HIER_ID, "Hierarchy ID" },
1062 { PCIZ_NPEM, "Native PCIe Enclosure Management" },
1063 { PCIZ_PL32, "Physical Layer 32.0 GT/s" },
1064 { PCIZ_AP, "Alternate Protocol" },
1065 { PCIZ_SFI, "System Firmware Intermediary" },
1070 list_ecaps(int fd, struct pci_conf *p)
1078 ecap = read_config(fd, &p->pc_sel, ptr, 4);
1079 if (ecap == 0xffffffff || ecap == 0)
1082 printf(" ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr);
1083 switch (PCI_EXTCAP_ID(ecap)) {
1085 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap));
1088 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap));
1091 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap));
1094 ecap_vendor(fd, p, ptr, PCI_EXTCAP_VER(ecap));
1097 ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap));
1100 ecap_sriov(fd, p, ptr, PCI_EXTCAP_VER(ecap));
1104 for (i = 0; ecap_names[i].name != NULL; i++)
1105 if (ecap_names[i].id == PCI_EXTCAP_ID(ecap)) {
1106 name = ecap_names[i].name;
1109 printf("%s %d\n", name, PCI_EXTCAP_VER(ecap));
1112 ptr = PCI_EXTCAP_NEXTPTR(ecap);
1115 ecap = read_config(fd, &p->pc_sel, ptr, 4);
1119 /* Find offset of a specific capability. Returns 0 on failure. */
1121 pci_find_cap(int fd, struct pci_conf *p, uint8_t id)
1126 /* Are capabilities present for this device? */
1127 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2);
1128 if (!(sta & PCIM_STATUS_CAPPRESENT))
1131 switch (p->pc_hdr & PCIM_HDRTYPE) {
1132 case PCIM_HDRTYPE_NORMAL:
1133 case PCIM_HDRTYPE_BRIDGE:
1136 case PCIM_HDRTYPE_CARDBUS:
1137 ptr = PCIR_CAP_PTR_2;
1143 ptr = read_config(fd, &p->pc_sel, ptr, 1);
1144 while (ptr != 0 && ptr != 0xff) {
1145 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
1148 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);
1153 /* Find offset of a specific extended capability. Returns 0 on failure. */
1155 pcie_find_cap(int fd, struct pci_conf *p, uint16_t id)
1161 ecap = read_config(fd, &p->pc_sel, ptr, 4);
1162 if (ecap == 0xffffffff || ecap == 0)
1165 if (PCI_EXTCAP_ID(ecap) == id)
1167 ptr = PCI_EXTCAP_NEXTPTR(ecap);
1170 ecap = read_config(fd, &p->pc_sel, ptr, 4);