2 * Copyright (c) 2007 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 static const char rcsid[] =
35 #include <sys/types.h>
39 #include <sys/agpio.h>
40 #include <sys/pciio.h>
42 #include <pci/agpreg.h>
43 #include <dev/pci/pcireg.h>
48 cap_power(int fd, struct pci_conf *p, uint8_t ptr)
52 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2);
53 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2);
54 printf("powerspec %d supports D0%s%s D3 current D%d",
56 cap & PCIM_PCAP_D1SUPP ? " D1" : "",
57 cap & PCIM_PCAP_D2SUPP ? " D2" : "",
58 status & PCIM_PSTAT_DMASK);
62 cap_agp(int fd, struct pci_conf *p, uint8_t ptr)
64 uint32_t status, command;
66 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4);
67 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4);
69 if (AGP_MODE_GET_MODE_3(status)) {
71 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x)
73 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x)
76 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x)
78 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x)
80 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x)
83 if (AGP_MODE_GET_SBA(status))
85 if (AGP_MODE_GET_AGP(command)) {
86 printf("enabled at ");
87 if (AGP_MODE_GET_MODE_3(command)) {
89 switch (AGP_MODE_GET_RATE(command)) {
90 case AGP_MODE_V3_RATE_8x:
93 case AGP_MODE_V3_RATE_4x:
98 switch (AGP_MODE_GET_RATE(command)) {
99 case AGP_MODE_V2_RATE_4x:
102 case AGP_MODE_V2_RATE_2x:
105 case AGP_MODE_V2_RATE_1x:
109 if (AGP_MODE_GET_SBA(command))
116 cap_vpd(int fd, struct pci_conf *p, uint8_t ptr)
123 cap_msi(int fd, struct pci_conf *p, uint8_t ptr)
128 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2);
129 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
130 printf("MSI supports %d message%s%s%s ", msgnum,
131 (msgnum == 1) ? "" : "s",
132 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
133 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : "");
134 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) {
135 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4);
136 printf("enabled with %d message%s", msgnum,
137 (msgnum == 1) ? "" : "s");
142 cap_pcix(int fd, struct pci_conf *p, uint8_t ptr)
145 int comma, max_splits, max_burst_read;
147 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4);
149 if (status & PCIXM_STATUS_64BIT)
151 if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
155 if (status & PCIXM_STATUS_133CAP) {
156 printf("%s 133MHz", comma ? "," : "");
159 if (status & PCIXM_STATUS_266CAP) {
160 printf("%s 266MHz", comma ? "," : "");
163 if (status & PCIXM_STATUS_533CAP) {
164 printf("%s 533MHz", comma ? "," : "");
167 if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
169 switch (status & PCIXM_STATUS_MAX_READ) {
170 case PCIXM_STATUS_MAX_READ_512:
171 max_burst_read = 512;
173 case PCIXM_STATUS_MAX_READ_1024:
174 max_burst_read = 1024;
176 case PCIXM_STATUS_MAX_READ_2048:
177 max_burst_read = 2048;
179 case PCIXM_STATUS_MAX_READ_4096:
180 max_burst_read = 4096;
183 switch (status & PCIXM_STATUS_MAX_SPLITS) {
184 case PCIXM_STATUS_MAX_SPLITS_1:
187 case PCIXM_STATUS_MAX_SPLITS_2:
190 case PCIXM_STATUS_MAX_SPLITS_3:
193 case PCIXM_STATUS_MAX_SPLITS_4:
196 case PCIXM_STATUS_MAX_SPLITS_8:
199 case PCIXM_STATUS_MAX_SPLITS_12:
202 case PCIXM_STATUS_MAX_SPLITS_16:
205 case PCIXM_STATUS_MAX_SPLITS_32:
209 printf("%s %d burst read, %d split transaction%s", comma ? "," : "",
210 max_burst_read, max_splits, max_splits == 1 ? "" : "s");
214 cap_ht(int fd, struct pci_conf *p, uint8_t ptr)
219 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2);
221 if ((command & 0xe000) == PCIM_HTCAP_SLAVE)
223 else if ((command & 0xe000) == PCIM_HTCAP_HOST)
226 switch (command & PCIM_HTCMD_CAP_MASK) {
227 case PCIM_HTCAP_SWITCH:
230 case PCIM_HTCAP_INTERRUPT:
233 case PCIM_HTCAP_REVISION_ID:
234 printf("revision ID");
236 case PCIM_HTCAP_UNITID_CLUMPING:
237 printf("unit ID clumping");
239 case PCIM_HTCAP_EXT_CONFIG_SPACE:
240 printf("extended config space");
242 case PCIM_HTCAP_ADDRESS_MAPPING:
243 printf("address mapping");
245 case PCIM_HTCAP_MSI_MAPPING:
246 printf("MSI %saddress window %s at 0x",
247 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "",
248 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" :
250 if (command & PCIM_HTCMD_MSI_FIXED)
253 reg = read_config(fd, &p->pc_sel,
254 ptr + PCIR_HTMSI_ADDRESS_HI, 4);
257 reg = read_config(fd, &p->pc_sel,
258 ptr + PCIR_HTMSI_ADDRESS_LO, 4);
262 case PCIM_HTCAP_DIRECT_ROUTE:
263 printf("direct route");
265 case PCIM_HTCAP_VCSET:
268 case PCIM_HTCAP_RETRY_MODE:
269 printf("retry mode");
272 printf("unknown %02x", command);
278 cap_vendor(int fd, struct pci_conf *p, uint8_t ptr)
282 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1);
283 printf("vendor (length %d)", length);
284 if (p->pc_vendor == 0x8086) {
288 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA,
290 printf(" Intel cap %d version %d", version >> 4, version & 0xf);
291 if (version >> 4 == 1 && length == 12) {
292 /* Feature Detection */
297 fvec = read_config(fd, &p->pc_sel, ptr +
298 PCIR_VENDOR_DATA + 5, 4);
299 printf("\n\t\t features:");
300 if (fvec & (1 << 0)) {
304 fvec = read_config(fd, &p->pc_sel, ptr +
305 PCIR_VENDOR_DATA + 1, 4);
306 if (fvec & (1 << 21)) {
307 printf("%s Quick Resume", comma ? "," : "");
310 if (fvec & (1 << 18)) {
311 printf("%s SATA RAID-5", comma ? "," : "");
314 if (fvec & (1 << 9)) {
315 printf("%s Mobile", comma ? "," : "");
318 if (fvec & (1 << 7)) {
319 printf("%s 6 PCI-e x1 slots", comma ? "," : "");
322 printf("%s 4 PCI-e x1 slots", comma ? "," : "");
325 if (fvec & (1 << 5)) {
326 printf("%s SATA RAID-0/1/10", comma ? "," : "");
329 if (fvec & (1 << 3)) {
330 printf("%s SATA AHCI", comma ? "," : "");
338 cap_debug(int fd, struct pci_conf *p, uint8_t ptr)
342 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2);
343 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port &
344 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13));
348 cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr)
352 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4);
353 printf("PCI Bridge card=0x%08x", id);
357 cap_express(int fd, struct pci_conf *p, uint8_t ptr)
361 flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_FLAGS, 2);
362 printf("PCI-Express %d ", flags & PCIM_EXP_FLAGS_VERSION);
363 switch (flags & PCIM_EXP_FLAGS_TYPE) {
364 case PCIM_EXP_TYPE_ENDPOINT:
367 case PCIM_EXP_TYPE_LEGACY_ENDPOINT:
368 printf("legacy endpoint");
370 case PCIM_EXP_TYPE_ROOT_PORT:
373 case PCIM_EXP_TYPE_UPSTREAM_PORT:
374 printf("upstream port");
376 case PCIM_EXP_TYPE_DOWNSTREAM_PORT:
377 printf("downstream port");
379 case PCIM_EXP_TYPE_PCI_BRIDGE:
380 printf("PCI bridge");
383 printf("type %d", (flags & PCIM_EXP_FLAGS_TYPE) >> 8);
386 if (flags & PCIM_EXP_FLAGS_IRQ)
387 printf(" IRQ %d", (flags & PCIM_EXP_FLAGS_IRQ) >> 17);
391 cap_msix(int fd, struct pci_conf *p, uint8_t ptr)
395 int msgnum, table_bar, pba_bar;
397 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2);
398 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
399 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4);
400 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
401 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4);
402 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
403 printf("MSI-X supports %d message%s ", msgnum,
404 (msgnum == 1) ? "" : "s");
405 if (table_bar == pba_bar)
406 printf("in map 0x%x", table_bar);
408 printf("in maps 0x%x and 0x%x", table_bar, pba_bar);
409 if (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE)
414 list_caps(int fd, struct pci_conf *p)
419 /* Are capabilities present for this device? */
420 cmd = read_config(fd, &p->pc_sel, PCIR_STATUS, 2);
421 if (!(cmd & PCIM_STATUS_CAPPRESENT))
424 switch (p->pc_hdr & PCIM_HDRTYPE) {
430 ptr = PCIR_CAP_PTR_2;
433 errx(1, "list_caps: bad header type");
436 /* Walk the capability list. */
437 ptr = read_config(fd, &p->pc_sel, ptr, 1);
438 while (ptr != 0 && ptr != 0xff) {
439 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
440 printf(" cap %02x[%02x] = ", cap, ptr);
443 cap_power(fd, p, ptr);
455 cap_pcix(fd, p, ptr);
461 cap_vendor(fd, p, ptr);
464 cap_debug(fd, p, ptr);
467 cap_subvendor(fd, p, ptr);
470 cap_express(fd, p, ptr);
473 cap_msix(fd, p, ptr);
480 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);