2 * Copyright (c) 2007 Yahoo!, Inc.
4 * Written by: John Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 static const char rcsid[] =
36 #include <sys/types.h>
40 #include <sys/agpio.h>
41 #include <sys/pciio.h>
43 #include <dev/agp/agpreg.h>
44 #include <dev/pci/pcireg.h>
48 static void list_ecaps(int fd, struct pci_conf *p);
51 cap_power(int fd, struct pci_conf *p, uint8_t ptr)
55 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2);
56 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2);
57 printf("powerspec %d supports D0%s%s D3 current D%d",
59 cap & PCIM_PCAP_D1SUPP ? " D1" : "",
60 cap & PCIM_PCAP_D2SUPP ? " D2" : "",
61 status & PCIM_PSTAT_DMASK);
65 cap_agp(int fd, struct pci_conf *p, uint8_t ptr)
67 uint32_t status, command;
69 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4);
70 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4);
72 if (AGP_MODE_GET_MODE_3(status)) {
74 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x)
76 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x)
79 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x)
81 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x)
83 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x)
86 if (AGP_MODE_GET_SBA(status))
88 if (AGP_MODE_GET_AGP(command)) {
89 printf("enabled at ");
90 if (AGP_MODE_GET_MODE_3(command)) {
92 switch (AGP_MODE_GET_RATE(command)) {
93 case AGP_MODE_V3_RATE_8x:
96 case AGP_MODE_V3_RATE_4x:
101 switch (AGP_MODE_GET_RATE(command)) {
102 case AGP_MODE_V2_RATE_4x:
105 case AGP_MODE_V2_RATE_2x:
108 case AGP_MODE_V2_RATE_1x:
112 if (AGP_MODE_GET_SBA(command))
119 cap_vpd(int fd, struct pci_conf *p, uint8_t ptr)
126 cap_msi(int fd, struct pci_conf *p, uint8_t ptr)
131 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2);
132 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
133 printf("MSI supports %d message%s%s%s ", msgnum,
134 (msgnum == 1) ? "" : "s",
135 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
136 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : "");
137 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) {
138 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4);
139 printf("enabled with %d message%s", msgnum,
140 (msgnum == 1) ? "" : "s");
145 cap_pcix(int fd, struct pci_conf *p, uint8_t ptr)
148 int comma, max_splits, max_burst_read;
150 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4);
152 if (status & PCIXM_STATUS_64BIT)
154 if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
156 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP |
157 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0)
160 if (status & PCIXM_STATUS_133CAP) {
161 printf("%s 133MHz", comma ? "," : "");
164 if (status & PCIXM_STATUS_266CAP) {
165 printf("%s 266MHz", comma ? "," : "");
168 if (status & PCIXM_STATUS_533CAP) {
169 printf("%s 533MHz", comma ? "," : "");
172 if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
174 switch (status & PCIXM_STATUS_MAX_READ) {
175 case PCIXM_STATUS_MAX_READ_512:
176 max_burst_read = 512;
178 case PCIXM_STATUS_MAX_READ_1024:
179 max_burst_read = 1024;
181 case PCIXM_STATUS_MAX_READ_2048:
182 max_burst_read = 2048;
184 case PCIXM_STATUS_MAX_READ_4096:
185 max_burst_read = 4096;
188 switch (status & PCIXM_STATUS_MAX_SPLITS) {
189 case PCIXM_STATUS_MAX_SPLITS_1:
192 case PCIXM_STATUS_MAX_SPLITS_2:
195 case PCIXM_STATUS_MAX_SPLITS_3:
198 case PCIXM_STATUS_MAX_SPLITS_4:
201 case PCIXM_STATUS_MAX_SPLITS_8:
204 case PCIXM_STATUS_MAX_SPLITS_12:
207 case PCIXM_STATUS_MAX_SPLITS_16:
210 case PCIXM_STATUS_MAX_SPLITS_32:
214 printf("%s %d burst read, %d split transaction%s", comma ? "," : "",
215 max_burst_read, max_splits, max_splits == 1 ? "" : "s");
219 cap_ht(int fd, struct pci_conf *p, uint8_t ptr)
224 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2);
226 if ((command & 0xe000) == PCIM_HTCAP_SLAVE)
228 else if ((command & 0xe000) == PCIM_HTCAP_HOST)
231 switch (command & PCIM_HTCMD_CAP_MASK) {
232 case PCIM_HTCAP_SWITCH:
235 case PCIM_HTCAP_INTERRUPT:
238 case PCIM_HTCAP_REVISION_ID:
239 printf("revision ID");
241 case PCIM_HTCAP_UNITID_CLUMPING:
242 printf("unit ID clumping");
244 case PCIM_HTCAP_EXT_CONFIG_SPACE:
245 printf("extended config space");
247 case PCIM_HTCAP_ADDRESS_MAPPING:
248 printf("address mapping");
250 case PCIM_HTCAP_MSI_MAPPING:
251 printf("MSI %saddress window %s at 0x",
252 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "",
253 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" :
255 if (command & PCIM_HTCMD_MSI_FIXED)
258 reg = read_config(fd, &p->pc_sel,
259 ptr + PCIR_HTMSI_ADDRESS_HI, 4);
262 reg = read_config(fd, &p->pc_sel,
263 ptr + PCIR_HTMSI_ADDRESS_LO, 4);
267 case PCIM_HTCAP_DIRECT_ROUTE:
268 printf("direct route");
270 case PCIM_HTCAP_VCSET:
273 case PCIM_HTCAP_RETRY_MODE:
274 printf("retry mode");
276 case PCIM_HTCAP_X86_ENCODING:
277 printf("X86 encoding");
279 case PCIM_HTCAP_GEN3:
283 printf("function-level extension");
286 printf("power management");
288 case PCIM_HTCAP_HIGH_NODE_COUNT:
289 printf("high node count");
292 printf("unknown %02x", command);
298 cap_vendor(int fd, struct pci_conf *p, uint8_t ptr)
302 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1);
303 printf("vendor (length %d)", length);
304 if (p->pc_vendor == 0x8086) {
308 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA,
310 printf(" Intel cap %d version %d", version >> 4, version & 0xf);
311 if (version >> 4 == 1 && length == 12) {
312 /* Feature Detection */
317 fvec = read_config(fd, &p->pc_sel, ptr +
318 PCIR_VENDOR_DATA + 5, 4);
319 printf("\n\t\t features:");
320 if (fvec & (1 << 0)) {
324 fvec = read_config(fd, &p->pc_sel, ptr +
325 PCIR_VENDOR_DATA + 1, 4);
326 if (fvec & (1 << 21)) {
327 printf("%s Quick Resume", comma ? "," : "");
330 if (fvec & (1 << 18)) {
331 printf("%s SATA RAID-5", comma ? "," : "");
334 if (fvec & (1 << 9)) {
335 printf("%s Mobile", comma ? "," : "");
338 if (fvec & (1 << 7)) {
339 printf("%s 6 PCI-e x1 slots", comma ? "," : "");
342 printf("%s 4 PCI-e x1 slots", comma ? "," : "");
345 if (fvec & (1 << 5)) {
346 printf("%s SATA RAID-0/1/10", comma ? "," : "");
349 if (fvec & (1 << 3)) {
350 printf("%s SATA AHCI", comma ? "," : "");
358 cap_debug(int fd, struct pci_conf *p, uint8_t ptr)
362 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2);
363 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port &
364 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13));
368 cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr)
372 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4);
373 printf("PCI Bridge card=0x%08x", id);
376 #define MAX_PAYLOAD(field) (128 << (field))
379 link_speed_string(uint8_t speed)
395 cap_express(int fd, struct pci_conf *p, uint8_t ptr)
400 flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2);
401 printf("PCI-Express %d ", flags & PCIEM_FLAGS_VERSION);
402 switch (flags & PCIEM_FLAGS_TYPE) {
403 case PCIEM_TYPE_ENDPOINT:
406 case PCIEM_TYPE_LEGACY_ENDPOINT:
407 printf("legacy endpoint");
409 case PCIEM_TYPE_ROOT_PORT:
412 case PCIEM_TYPE_UPSTREAM_PORT:
413 printf("upstream port");
415 case PCIEM_TYPE_DOWNSTREAM_PORT:
416 printf("downstream port");
418 case PCIEM_TYPE_PCI_BRIDGE:
419 printf("PCI bridge");
421 case PCIEM_TYPE_PCIE_BRIDGE:
422 printf("PCI to PCIe bridge");
424 case PCIEM_TYPE_ROOT_INT_EP:
425 printf("root endpoint");
427 case PCIEM_TYPE_ROOT_EC:
428 printf("event collector");
431 printf("type %d", (flags & PCIEM_FLAGS_TYPE) >> 4);
434 if (flags & PCIEM_FLAGS_SLOT)
436 if (flags & PCIEM_FLAGS_IRQ)
437 printf(" IRQ %d", (flags & PCIEM_FLAGS_IRQ) >> 9);
438 val = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4);
439 flags = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2);
440 printf(" max data %d(%d)",
441 MAX_PAYLOAD((flags & PCIEM_CTL_MAX_PAYLOAD) >> 5),
442 MAX_PAYLOAD(val & PCIEM_CAP_MAX_PAYLOAD));
443 if (val & PCIEM_CAP_FLR)
445 val = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4);
446 flags = read_config(fd, &p->pc_sel, ptr+ PCIER_LINK_STA, 2);
447 printf(" link x%d(x%d)", (flags & PCIEM_LINK_STA_WIDTH) >> 4,
448 (val & PCIEM_LINK_CAP_MAX_WIDTH) >> 4);
450 * Only print link speed info if the link's max width is
453 if ((val & PCIEM_LINK_CAP_MAX_WIDTH) != 0) {
455 printf(" %s(%s)", (flags & PCIEM_LINK_STA_WIDTH) == 0 ?
456 "0.0" : link_speed_string(flags & PCIEM_LINK_STA_SPEED),
457 link_speed_string(val & PCIEM_LINK_CAP_MAX_SPEED));
462 cap_msix(int fd, struct pci_conf *p, uint8_t ptr)
464 uint32_t pba_offset, table_offset, val;
465 int msgnum, pba_bar, table_bar;
468 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2);
469 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
471 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4);
472 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
473 table_offset = val & ~PCIM_MSIX_BIR_MASK;
475 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4);
476 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
477 pba_offset = val & ~PCIM_MSIX_BIR_MASK;
479 printf("MSI-X supports %d message%s%s\n", msgnum,
480 (msgnum == 1) ? "" : "s",
481 (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) ? ", enabled" : "");
484 printf("Table in map 0x%x[0x%x], PBA in map 0x%x[0x%x]",
485 table_bar, table_offset, pba_bar, pba_offset);
489 cap_sata(int fd, struct pci_conf *p, uint8_t ptr)
492 printf("SATA Index-Data Pair");
496 cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr)
500 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1);
501 printf("PCI Advanced Features:%s%s",
502 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "",
503 cap & PCIM_PCIAFCAP_TP ? " TP" : "");
507 list_caps(int fd, struct pci_conf *p)
513 /* Are capabilities present for this device? */
514 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2);
515 if (!(sta & PCIM_STATUS_CAPPRESENT))
518 switch (p->pc_hdr & PCIM_HDRTYPE) {
519 case PCIM_HDRTYPE_NORMAL:
520 case PCIM_HDRTYPE_BRIDGE:
523 case PCIM_HDRTYPE_CARDBUS:
524 ptr = PCIR_CAP_PTR_2;
527 errx(1, "list_caps: bad header type");
530 /* Walk the capability list. */
532 ptr = read_config(fd, &p->pc_sel, ptr, 1);
533 while (ptr != 0 && ptr != 0xff) {
534 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
535 printf(" cap %02x[%02x] = ", cap, ptr);
538 cap_power(fd, p, ptr);
550 cap_pcix(fd, p, ptr);
556 cap_vendor(fd, p, ptr);
559 cap_debug(fd, p, ptr);
562 cap_subvendor(fd, p, ptr);
566 cap_express(fd, p, ptr);
569 cap_msix(fd, p, ptr);
572 cap_sata(fd, p, ptr);
575 cap_pciaf(fd, p, ptr);
582 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);
589 /* From <sys/systm.h>. */
590 static __inline uint32_t
591 bitcount32(uint32_t x)
594 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1);
595 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2);
596 x = (x + (x >> 4)) & 0x0f0f0f0f;
598 x = (x + (x >> 16)) & 0x000000ff;
603 ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
607 printf("AER %d", ver);
610 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4);
611 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4);
612 printf(" %d fatal", bitcount32(sta & mask));
613 printf(" %d non-fatal", bitcount32(sta & ~mask));
614 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4);
615 printf(" %d corrected", bitcount32(sta));
619 ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
623 printf("VC %d", ver);
626 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4);
627 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT);
628 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0)
629 printf(" lowpri VC0-VC%d",
630 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4);
634 ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
638 printf("Serial %d", ver);
641 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4);
642 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4);
643 printf(" %08x%08x", high, low);
647 ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
651 printf("Vendor %d", ver);
654 val = read_config(fd, &p->pc_sel, ptr + 4, 4);
655 printf(" ID %d", val & 0xffff);
659 ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
663 printf("PCIe Sec %d", ver);
666 val = read_config(fd, &p->pc_sel, ptr + 8, 4);
667 printf(" lane errors %#x", val);
674 { PCIZ_PWRBDGT, "Power Budgeting" },
675 { PCIZ_RCLINK_DCL, "Root Complex Link Declaration" },
676 { PCIZ_RCLINK_CTL, "Root Complex Internal Link Control" },
677 { PCIZ_RCEC_ASSOC, "Root Complex Event Collector ASsociation" },
678 { PCIZ_MFVC, "MFVC" },
679 { PCIZ_RCRB, "RCRB" },
683 { PCIZ_SRIOV, "SRIOV" },
684 { PCIZ_MULTICAST, "Multicast" },
685 { PCIZ_RESIZE_BAR, "Resizable BAR" },
687 { PCIZ_TPH_REQ, "TPH Requester" },
693 list_ecaps(int fd, struct pci_conf *p)
701 ecap = read_config(fd, &p->pc_sel, ptr, 4);
702 if (ecap == 0xffffffff || ecap == 0)
705 printf(" ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr);
706 switch (PCI_EXTCAP_ID(ecap)) {
708 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap));
711 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap));
714 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap));
717 ecap_vendor(fd, p, ptr, PCI_EXTCAP_VER(ecap));
720 ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap));
724 for (i = 0; ecap_names[i].name != NULL; i++)
725 if (ecap_names[i].id == PCI_EXTCAP_ID(ecap)) {
726 name = ecap_names[i].name;
729 printf("%s %d", name, PCI_EXTCAP_VER(ecap));
733 ptr = PCI_EXTCAP_NEXTPTR(ecap);
736 ecap = read_config(fd, &p->pc_sel, ptr, 4);
740 /* Find offset of a specific capability. Returns 0 on failure. */
742 pci_find_cap(int fd, struct pci_conf *p, uint8_t id)
747 /* Are capabilities present for this device? */
748 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2);
749 if (!(sta & PCIM_STATUS_CAPPRESENT))
752 switch (p->pc_hdr & PCIM_HDRTYPE) {
753 case PCIM_HDRTYPE_NORMAL:
754 case PCIM_HDRTYPE_BRIDGE:
757 case PCIM_HDRTYPE_CARDBUS:
758 ptr = PCIR_CAP_PTR_2;
764 ptr = read_config(fd, &p->pc_sel, ptr, 1);
765 while (ptr != 0 && ptr != 0xff) {
766 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
769 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);
774 /* Find offset of a specific extended capability. Returns 0 on failure. */
776 pcie_find_cap(int fd, struct pci_conf *p, uint16_t id)
782 ecap = read_config(fd, &p->pc_sel, ptr, 4);
783 if (ecap == 0xffffffff || ecap == 0)
786 if (PCI_EXTCAP_ID(ecap) == id)
788 ptr = PCI_EXTCAP_NEXTPTR(ecap);
791 ecap = read_config(fd, &p->pc_sel, ptr, 4);