1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
16 #define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
18 #include "InfoByHwMode.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/SetVector.h"
23 #include "llvm/ADT/SmallPtrSet.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/SparseBitVector.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/StringMap.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/CodeGen/MachineValueType.h"
30 #include "llvm/MC/LaneBitmask.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/TableGen/Record.h"
33 #include "llvm/TableGen/SetTheory.h"
46 template <typename T, typename Vector, typename Set> class SetVector;
48 /// Used to encode a step in a register lane mask transformation.
49 /// Mask the bits specified in Mask, then rotate them Rol bits to the left
50 /// assuming a wraparound at 32bits.
55 bool operator==(const MaskRolPair Other) const {
56 return Mask == Other.Mask && RotateLeft == Other.RotateLeft;
58 bool operator!=(const MaskRolPair Other) const {
59 return Mask != Other.Mask || RotateLeft != Other.RotateLeft;
63 /// CodeGenSubRegIndex - Represents a sub-register index.
64 class CodeGenSubRegIndex {
67 std::string Namespace;
72 const unsigned EnumValue;
73 mutable LaneBitmask LaneMask;
74 mutable SmallVector<MaskRolPair,1> CompositionLaneMaskTransform;
76 /// A list of subregister indexes concatenated resulting in this
77 /// subregister index. This is the reverse of CodeGenRegBank::ConcatIdx.
78 SmallVector<CodeGenSubRegIndex*,4> ConcatenationOf;
80 // Are all super-registers containing this SubRegIndex covered by their
82 bool AllSuperRegsCovered;
84 CodeGenSubRegIndex(Record *R, unsigned Enum);
85 CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
87 const std::string &getName() const { return Name; }
88 const std::string &getNamespace() const { return Namespace; }
89 std::string getQualifiedName() const;
91 // Map of composite subreg indices.
92 typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *,
93 deref<llvm::less>> CompMap;
95 // Returns the subreg index that results from composing this with Idx.
96 // Returns NULL if this and Idx don't compose.
97 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
98 CompMap::const_iterator I = Composed.find(Idx);
99 return I == Composed.end() ? nullptr : I->second;
102 // Add a composite subreg index: this+A = B.
103 // Return a conflicting composite, or NULL
104 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
105 CodeGenSubRegIndex *B) {
107 std::pair<CompMap::iterator, bool> Ins =
108 Composed.insert(std::make_pair(A, B));
109 // Synthetic subreg indices that aren't contiguous (for instance ARM
110 // register tuples) don't have a bit range, so it's OK to let
111 // B->Offset == -1. For the other cases, accumulate the offset and set
112 // the size here. Only do so if there is no offset yet though.
113 if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
114 (B->Offset == (uint16_t)-1)) {
115 B->Offset = Offset + A->Offset;
118 return (Ins.second || Ins.first->second == B) ? nullptr
122 // Update the composite maps of components specified in 'ComposedOf'.
123 void updateComponents(CodeGenRegBank&);
125 // Return the map of composites.
126 const CompMap &getComposites() const { return Composed; }
128 // Compute LaneMask from Composed. Return LaneMask.
129 LaneBitmask computeLaneMask() const;
131 void setConcatenationOf(ArrayRef<CodeGenSubRegIndex*> Parts);
133 /// Replaces subregister indexes in the `ConcatenationOf` list with
134 /// list of subregisters they are composed of (if any). Do this recursively.
135 void computeConcatTransitiveClosure();
141 inline bool operator<(const CodeGenSubRegIndex &A,
142 const CodeGenSubRegIndex &B) {
143 return A.EnumValue < B.EnumValue;
146 /// CodeGenRegister - Represents a register definition.
147 struct CodeGenRegister {
151 bool CoveredBySubRegs;
152 bool HasDisjunctSubRegs;
154 // Map SubRegIndex -> Register.
155 typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<llvm::less>>
158 CodeGenRegister(Record *R, unsigned Enum);
160 const StringRef getName() const;
162 // Extract more information from TheDef. This is used to build an object
163 // graph after all CodeGenRegister objects have been created.
164 void buildObjectGraph(CodeGenRegBank&);
166 // Lazily compute a map of all sub-registers.
167 // This includes unique entries for all sub-sub-registers.
168 const SubRegMap &computeSubRegs(CodeGenRegBank&);
170 // Compute extra sub-registers by combining the existing sub-registers.
171 void computeSecondarySubRegs(CodeGenRegBank&);
173 // Add this as a super-register to all sub-registers after the sub-register
174 // graph has been built.
175 void computeSuperRegs(CodeGenRegBank&);
177 const SubRegMap &getSubRegs() const {
178 assert(SubRegsComplete && "Must precompute sub-registers");
182 // Add sub-registers to OSet following a pre-order defined by the .td file.
183 void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
184 CodeGenRegBank&) const;
186 // Return the sub-register index naming Reg as a sub-register of this
187 // register. Returns NULL if Reg is not a sub-register.
188 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
189 return SubReg2Idx.lookup(Reg);
192 typedef std::vector<const CodeGenRegister*> SuperRegList;
194 // Get the list of super-registers in topological order, small to large.
195 // This is valid after computeSubRegs visits all registers during RegBank
197 const SuperRegList &getSuperRegs() const {
198 assert(SubRegsComplete && "Must precompute sub-registers");
202 // Get the list of ad hoc aliases. The graph is symmetric, so the list
203 // contains all registers in 'Aliases', and all registers that mention this
204 // register in 'Aliases'.
205 ArrayRef<CodeGenRegister*> getExplicitAliases() const {
206 return ExplicitAliases;
209 // Get the topological signature of this register. This is a small integer
210 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
211 // identical sub-register structure. That is, they support the same set of
212 // sub-register indices mapping to the same kind of sub-registers
214 unsigned getTopoSig() const {
215 assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
219 // List of register units in ascending order.
220 typedef SparseBitVector<> RegUnitList;
221 typedef SmallVector<LaneBitmask, 16> RegUnitLaneMaskList;
223 // How many entries in RegUnitList are native?
224 RegUnitList NativeRegUnits;
226 // Get the list of register units.
227 // This is only valid after computeSubRegs() completes.
228 const RegUnitList &getRegUnits() const { return RegUnits; }
230 ArrayRef<LaneBitmask> getRegUnitLaneMasks() const {
231 return makeArrayRef(RegUnitLaneMasks).slice(0, NativeRegUnits.count());
234 // Get the native register units. This is a prefix of getRegUnits().
235 RegUnitList getNativeRegUnits() const {
236 return NativeRegUnits;
239 void setRegUnitLaneMasks(const RegUnitLaneMaskList &LaneMasks) {
240 RegUnitLaneMasks = LaneMasks;
243 // Inherit register units from subregisters.
244 // Return true if the RegUnits changed.
245 bool inheritRegUnits(CodeGenRegBank &RegBank);
247 // Adopt a register unit for pressure tracking.
248 // A unit is adopted iff its unit number is >= NativeRegUnits.count().
249 void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); }
251 // Get the sum of this register's register unit weights.
252 unsigned getWeight(const CodeGenRegBank &RegBank) const;
254 // Canonically ordered set.
255 typedef std::vector<const CodeGenRegister*> Vec;
258 bool SubRegsComplete;
259 bool SuperRegsComplete;
262 // The sub-registers explicit in the .td file form a tree.
263 SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices;
264 SmallVector<CodeGenRegister*, 8> ExplicitSubRegs;
266 // Explicit ad hoc aliases, symmetrized to form an undirected graph.
267 SmallVector<CodeGenRegister*, 8> ExplicitAliases;
269 // Super-registers where this is the first explicit sub-register.
270 SuperRegList LeadingSuperRegs;
273 SuperRegList SuperRegs;
274 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
275 RegUnitList RegUnits;
276 RegUnitLaneMaskList RegUnitLaneMasks;
279 inline bool operator<(const CodeGenRegister &A, const CodeGenRegister &B) {
280 return A.EnumValue < B.EnumValue;
283 inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) {
284 return A.EnumValue == B.EnumValue;
287 class CodeGenRegisterClass {
288 CodeGenRegister::Vec Members;
289 // Allocation orders. Order[0] always contains all registers in Members.
290 std::vector<SmallVector<Record*, 16>> Orders;
291 // Bit mask of sub-classes including this, indexed by their EnumValue.
292 BitVector SubClasses;
293 // List of super-classes, topologocally ordered to have the larger classes
294 // first. This is the same as sorting by EnumValue.
295 SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
299 // For a synthesized class, inherit missing properties from the nearest
301 void inheritProperties(CodeGenRegBank&);
303 // Map SubRegIndex -> sub-class. This is the largest sub-class where all
304 // registers have a SubRegIndex sub-register.
305 DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *>
308 // Map SubRegIndex -> set of super-reg classes. This is all register
309 // classes SuperRC such that:
311 // R:SubRegIndex in this RC for all R in SuperRC.
313 DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>>
316 // Bit vector of TopoSigs for the registers in this class. This will be
317 // very sparse on regular architectures.
323 SmallVector<ValueTypeByHwMode, 4> VTs;
324 RegSizeInfoByHwMode RSI;
327 StringRef AltOrderSelect;
328 uint8_t AllocationPriority;
329 /// Contains the combination of the lane masks of all subregisters.
330 LaneBitmask LaneMask;
331 /// True if there are at least 2 subregisters which do not interfere.
332 bool HasDisjunctSubRegs;
333 bool CoveredBySubRegs;
335 // Return the Record that defined this class, or NULL if the class was
336 // created by TableGen.
337 Record *getDef() const { return TheDef; }
339 const std::string &getName() const { return Name; }
340 std::string getQualifiedName() const;
341 ArrayRef<ValueTypeByHwMode> getValueTypes() const { return VTs; }
342 unsigned getNumValueTypes() const { return VTs.size(); }
344 ValueTypeByHwMode getValueTypeNum(unsigned VTNum) const {
345 if (VTNum < VTs.size())
347 llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
350 // Return true if this this class contains the register.
351 bool contains(const CodeGenRegister*) const;
353 // Returns true if RC is a subclass.
354 // RC is a sub-class of this class if it is a valid replacement for any
355 // instruction operand where a register of this classis required. It must
356 // satisfy these conditions:
358 // 1. All RC registers are also in this.
359 // 2. The RC spill size must not be smaller than our spill size.
360 // 3. RC spill alignment must be compatible with ours.
362 bool hasSubClass(const CodeGenRegisterClass *RC) const {
363 return SubClasses.test(RC->EnumValue);
366 // getSubClassWithSubReg - Returns the largest sub-class where all
367 // registers have a SubIdx sub-register.
368 CodeGenRegisterClass *
369 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
370 return SubClassWithSubReg.lookup(SubIdx);
373 /// Find largest subclass where all registers have SubIdx subregisters in
374 /// SubRegClass and the largest subregister class that contains those
375 /// subregisters without (as far as possible) also containing additional registers.
377 /// This can be used to find a suitable pair of classes for subregister copies.
378 /// \return std::pair<SubClass, SubRegClass> where SubClass is a SubClass is
379 /// a class where every register has SubIdx and SubRegClass is a class where
380 /// every register is covered by the SubIdx subregister of SubClass.
381 Optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>>
382 getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank,
383 const CodeGenSubRegIndex *SubIdx) const;
385 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
386 CodeGenRegisterClass *SubRC) {
387 SubClassWithSubReg[SubIdx] = SubRC;
390 // getSuperRegClasses - Returns a bit vector of all register classes
391 // containing only SubIdx super-registers of this class.
392 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
393 BitVector &Out) const;
395 // addSuperRegClass - Add a class containing only SubIdx super-registers.
396 void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
397 CodeGenRegisterClass *SuperRC) {
398 SuperRegClasses[SubIdx].insert(SuperRC);
401 // getSubClasses - Returns a constant BitVector of subclasses indexed by
403 // The SubClasses vector includes an entry for this class.
404 const BitVector &getSubClasses() const { return SubClasses; }
406 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
407 // The array does not include an entry for this class.
408 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
412 // Returns an ordered list of class members.
413 // The order of registers is the same as in the .td file.
414 // No = 0 is the default allocation order, No = 1 is the first alternative.
415 ArrayRef<Record*> getOrder(unsigned No = 0) const {
419 // Return the total number of allocation orders available.
420 unsigned getNumOrders() const { return Orders.size(); }
422 // Get the set of registers. This set contains the same registers as
424 const CodeGenRegister::Vec &getMembers() const { return Members; }
426 // Get a bit vector of TopoSigs present in this register class.
427 const BitVector &getTopoSigs() const { return TopoSigs; }
429 // Populate a unique sorted list of units from a register set.
430 void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
432 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
434 // A key representing the parts of a register class used for forming
435 // sub-classes. Note the ordering provided by this key is not the same as
436 // the topological order used for the EnumValues.
438 const CodeGenRegister::Vec *Members;
439 RegSizeInfoByHwMode RSI;
441 Key(const CodeGenRegister::Vec *M, const RegSizeInfoByHwMode &I)
442 : Members(M), RSI(I) {}
444 Key(const CodeGenRegisterClass &RC)
445 : Members(&RC.getMembers()), RSI(RC.RSI) {}
447 // Lexicographical order of (Members, RegSizeInfoByHwMode).
448 bool operator<(const Key&) const;
451 // Create a non-user defined register class.
452 CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
454 // Called by CodeGenRegBank::CodeGenRegBank().
455 static void computeSubClasses(CodeGenRegBank&);
458 // Register units are used to model interference and register pressure.
459 // Every register is assigned one or more register units such that two
460 // registers overlap if and only if they have a register unit in common.
462 // Normally, one register unit is created per leaf register. Non-leaf
463 // registers inherit the units of their sub-registers.
465 // Weight assigned to this RegUnit for estimating register pressure.
466 // This is useful when equalizing weights in register classes with mixed
467 // register topologies.
470 // Each native RegUnit corresponds to one or two root registers. The full
471 // set of registers containing this unit can be computed as the union of
472 // these two registers and their super-registers.
473 const CodeGenRegister *Roots[2];
475 // Index into RegClassUnitSets where we can find the list of UnitSets that
476 // contain this unit.
477 unsigned RegClassUnitSetsIdx;
479 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) {
480 Roots[0] = Roots[1] = nullptr;
483 ArrayRef<const CodeGenRegister*> getRoots() const {
484 assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
485 return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]);
489 // Each RegUnitSet is a sorted vector with a name.
491 typedef std::vector<unsigned>::const_iterator iterator;
494 std::vector<unsigned> Units;
495 unsigned Weight = 0; // Cache the sum of all unit weights.
496 unsigned Order = 0; // Cache the sort key.
498 RegUnitSet() = default;
501 // Base vector for identifying TopoSigs. The contents uniquely identify a
502 // TopoSig, only computeSuperRegs needs to know how.
503 typedef SmallVector<unsigned, 16> TopoSigId;
505 // CodeGenRegBank - Represent a target's registers and the relations between
507 class CodeGenRegBank {
510 const CodeGenHwModes &CGH;
512 std::deque<CodeGenSubRegIndex> SubRegIndices;
513 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
515 CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
517 typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>,
518 CodeGenSubRegIndex*> ConcatIdxMap;
519 ConcatIdxMap ConcatIdx;
522 std::deque<CodeGenRegister> Registers;
523 StringMap<CodeGenRegister*> RegistersByName;
524 DenseMap<Record*, CodeGenRegister*> Def2Reg;
525 unsigned NumNativeRegUnits;
527 std::map<TopoSigId, unsigned> TopoSigs;
529 // Includes native (0..NumNativeRegUnits-1) and adopted register units.
530 SmallVector<RegUnit, 8> RegUnits;
533 std::list<CodeGenRegisterClass> RegClasses;
534 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
535 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
538 // Remember each unique set of register units. Initially, this contains a
539 // unique set for each register class. Simliar sets are coalesced with
540 // pruneUnitSets and new supersets are inferred during computeRegUnitSets.
541 std::vector<RegUnitSet> RegUnitSets;
543 // Map RegisterClass index to the index of the RegUnitSet that contains the
544 // class's units and any inferred RegUnit supersets.
546 // NOTE: This could grow beyond the number of register classes when we map
547 // register units to lists of unit sets. If the list of unit sets does not
548 // already exist for a register class, we create a new entry in this vector.
549 std::vector<std::vector<unsigned>> RegClassUnitSets;
551 // Give each register unit set an order based on sorting criteria.
552 std::vector<unsigned> RegUnitSetOrder;
554 // Add RC to *2RC maps.
555 void addToMaps(CodeGenRegisterClass*);
557 // Create a synthetic sub-class if it is missing.
558 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
559 const CodeGenRegister::Vec *Membs,
562 // Infer missing register classes.
563 void computeInferredRegisterClasses();
564 void inferCommonSubClass(CodeGenRegisterClass *RC);
565 void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
567 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) {
568 inferMatchingSuperRegClass(RC, RegClasses.begin());
571 void inferMatchingSuperRegClass(
572 CodeGenRegisterClass *RC,
573 std::list<CodeGenRegisterClass>::iterator FirstSubRegRC);
575 // Iteratively prune unit sets.
576 void pruneUnitSets();
578 // Compute a weight for each register unit created during getSubRegs.
579 void computeRegUnitWeights();
581 // Create a RegUnitSet for each RegClass and infer superclasses.
582 void computeRegUnitSets();
584 // Populate the Composite map from sub-register relationships.
585 void computeComposites();
587 // Compute a lane mask for each sub-register index.
588 void computeSubRegLaneMasks();
590 /// Computes a lane mask for each register unit enumerated by a physical
592 void computeRegUnitLaneMasks();
595 CodeGenRegBank(RecordKeeper&, const CodeGenHwModes&);
597 SetTheory &getSets() { return Sets; }
599 const CodeGenHwModes &getHwModes() const { return CGH; }
601 // Sub-register indices. The first NumNamedIndices are defined by the user
602 // in the .td files. The rest are synthesized such that all sub-registers
603 // have a unique name.
604 const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const {
605 return SubRegIndices;
608 // Find a SubRegIndex form its Record def.
609 CodeGenSubRegIndex *getSubRegIdx(Record*);
611 // Find or create a sub-register index representing the A+B composition.
612 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
613 CodeGenSubRegIndex *B);
615 // Find or create a sub-register index representing the concatenation of
616 // non-overlapping sibling indices.
618 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&);
620 const std::deque<CodeGenRegister> &getRegisters() { return Registers; }
622 const StringMap<CodeGenRegister*> &getRegistersByName() {
623 return RegistersByName;
626 // Find a register from its Record def.
627 CodeGenRegister *getReg(Record*);
629 // Get a Register's index into the Registers array.
630 unsigned getRegIndex(const CodeGenRegister *Reg) const {
631 return Reg->EnumValue - 1;
634 // Return the number of allocated TopoSigs. The first TopoSig representing
635 // leaf registers is allocated number 0.
636 unsigned getNumTopoSigs() const {
637 return TopoSigs.size();
640 // Find or create a TopoSig for the given TopoSigId.
641 // This function is only for use by CodeGenRegister::computeSuperRegs().
642 // Others should simply use Reg->getTopoSig().
643 unsigned getTopoSig(const TopoSigId &Id) {
644 return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
647 // Create a native register unit that is associated with one or two root
649 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) {
650 RegUnits.resize(RegUnits.size() + 1);
651 RegUnits.back().Roots[0] = R0;
652 RegUnits.back().Roots[1] = R1;
653 return RegUnits.size() - 1;
656 // Create a new non-native register unit that can be adopted by a register
657 // to increase its pressure. Note that NumNativeRegUnits is not increased.
658 unsigned newRegUnit(unsigned Weight) {
659 RegUnits.resize(RegUnits.size() + 1);
660 RegUnits.back().Weight = Weight;
661 return RegUnits.size() - 1;
664 // Native units are the singular unit of a leaf register. Register aliasing
665 // is completely characterized by native units. Adopted units exist to give
666 // register additional weight but don't affect aliasing.
667 bool isNativeUnit(unsigned RUID) {
668 return RUID < NumNativeRegUnits;
671 unsigned getNumNativeRegUnits() const {
672 return NumNativeRegUnits;
675 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
676 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
678 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }
680 const std::list<CodeGenRegisterClass> &getRegClasses() const {
684 // Find a register class from its def.
685 CodeGenRegisterClass *getRegClass(Record*);
687 /// getRegisterClassForRegister - Find the register class that contains the
688 /// specified physical register. If the register is not in a register
689 /// class, return null. If the register is in multiple classes, and the
690 /// classes have a superset-subset relationship and the same set of types,
691 /// return the superclass. Otherwise return null.
692 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
694 // Get the sum of unit weights.
695 unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
697 for (std::vector<unsigned>::const_iterator
698 I = Units.begin(), E = Units.end(); I != E; ++I)
699 Weight += getRegUnit(*I).Weight;
703 unsigned getRegSetIDAt(unsigned Order) const {
704 return RegUnitSetOrder[Order];
707 const RegUnitSet &getRegSetAt(unsigned Order) const {
708 return RegUnitSets[RegUnitSetOrder[Order]];
711 // Increase a RegUnitWeight.
712 void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
713 getRegUnit(RUID).Weight += Inc;
716 // Get the number of register pressure dimensions.
717 unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
719 // Get a set of register unit IDs for a given dimension of pressure.
720 const RegUnitSet &getRegPressureSet(unsigned Idx) const {
721 return RegUnitSets[Idx];
724 // The number of pressure set lists may be larget than the number of
725 // register classes if some register units appeared in a list of sets that
726 // did not correspond to an existing register class.
727 unsigned getNumRegClassPressureSetLists() const {
728 return RegClassUnitSets.size();
731 // Get a list of pressure set IDs for a register class. Liveness of a
732 // register in this class impacts each pressure set in this list by the
733 // weight of the register. An exact solution requires all registers in a
734 // class to have the same class, but it is not strictly guaranteed.
735 ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
736 return RegClassUnitSets[RCIdx];
739 // Computed derived records such as missing sub-register indices.
740 void computeDerivedInfo();
742 // Compute the set of registers completely covered by the registers in Regs.
743 // The returned BitVector will have a bit set for each register in Regs,
744 // all sub-registers, and all super-registers that are covered by the
745 // registers in Regs.
747 // This is used to compute the mask of call-preserved registers from a list
749 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
751 // Bit mask of lanes that cover their registers. A sub-register index whose
752 // LaneMask is contained in CoveringLanes will be completely covered by
753 // another sub-register with the same or larger lane mask.
754 LaneBitmask CoveringLanes;
756 // Helper function for printing debug information. Handles artificial
757 // (non-native) reg units.
758 void printRegUnitName(unsigned Unit) const;
761 } // end namespace llvm
763 #endif // LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H