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(parent: f7c698e) | patch
Set-up proper TCR values for memory related to Translation Table Walking
authorZbigniew Bodek <zbb@FreeBSD.org>
Thu, 16 Jul 2015 10:22:57 +0000 (10:22 +0000)
committerZbigniew Bodek <zbb@FreeBSD.org>
Thu, 16 Jul 2015 10:22:57 +0000 (10:22 +0000)
commit1038d102c45f85100654325933ec11e170699b45
tree83c346aae53decabe0c8ddefc6cbb3b21922f922tree | snapshot
parentf7c698e20d1ae6bdd9625fc8b8b1ce58077f172dcommit | diff
Set-up proper TCR values for memory related to Translation Table Walking

This commit adds proper cache and shareability attributes to
the TCR register.
Set memory attributes to Normal, outer and inner cacheable WBWA.
Set shareability to inner and outer shareable when SMP is enabled.

Reviewed by:   andrew
Obtained from: Semihalf
Sponsored by:  The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D3093
sys/arm64/arm64/locore.S diff | blob | history
sys/arm64/include/armreg.h diff | blob | history
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