]> CyberLeo.Net >> Repos - FreeBSD/FreeBSD.git/commit
rk_pll: Add support for mode
authormanu <manu@FreeBSD.org>
Thu, 14 Jun 2018 05:43:45 +0000 (05:43 +0000)
committermanu <manu@FreeBSD.org>
Thu, 14 Jun 2018 05:43:45 +0000 (05:43 +0000)
commit2cdc5636762a18da6b89ce42a44b62359bf42d47
tree8c462aa33678855536400ee2c388be1319ce1d45
parentbb5d08a4d089ce90085a86d25c531e58eeb456ab
rk_pll: Add support for mode

RockChip PLL have two modes controlled by a register, a "slow mode" (the
default one) where the frequency is derived from the 24Mhz oscillator on the
board, and a "normal" one when the pll take it's input from the real PLL output.

Default the mode to normal for all the PLLs.
sys/arm64/rockchip/clk/rk3328_cru.c
sys/arm64/rockchip/clk/rk_clk_pll.c
sys/arm64/rockchip/clk/rk_clk_pll.h