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(parent: 3128806) | patch
Provide a complete A23 PLL1 factor table, from 60MHz to 1872MHz.
authorJared McNeill <jmcneill@FreeBSD.org>
Sat, 15 Oct 2016 12:23:54 +0000 (12:23 +0000)
committerJared McNeill <jmcneill@FreeBSD.org>
Sat, 15 Oct 2016 12:23:54 +0000 (12:23 +0000)
commit2ee32f3c7fd9b74931f29d4069edf076e08e73b7
treed63d49c5d78cd48d4a76e57c4a2892c06062b378tree | snapshot
parent31288065a31930b7fc787f5945f4ee27e5054507commit | diff
Provide a complete A23 PLL1 factor table, from 60MHz to 1872MHz.
sys/arm/allwinner/clk/aw_pll.c diff | blob | history
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