In agp(4) avoid the need to flush all cpu caches with wbinvd between

In agp(4) avoid the need to flush all cpu caches with wbinvd between
updating the GTT and flushing the AGP TLB by storing the GTT in
write-combining memory.

On x86 flushing the AGP TLB is done by an I/O operation or a store to a
MMIO register in uncacheable memory.  Both cases imply that WC buffers are
flushed so no memory barriers are needed.

On powerpc there is no WC memory type.  It maps to uncacheable memory and
two stores to uncacheable memory, such as to the GTT and then to an MMIO
register, are strongly ordered, so no memory barriers are needed either.

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