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(parent: 7324e86) | patch
Core i7 supports invaliant TSC and the presense is presented on
authortakawata <takawata@FreeBSD.org>
Tue, 25 Nov 2008 13:35:06 +0000 (13:35 +0000)
committertakawata <takawata@FreeBSD.org>
Tue, 25 Nov 2008 13:35:06 +0000 (13:35 +0000)
commit616fde5fbba3fd2d76649bbbe9013bdfbc1e2f9d
treef7920de36d4bf3705b3e94fbebcdf06daa40dd3etree | snapshot
parent7324e865076699cbd9e13c6c763112b1f4e9ad6dcommit | diff
Core i7 supports invaliant TSC and the presense is presented on
this CPUID information, according to recently updated AP485.
sys/i386/i386/identcpu.c diff | blob | history
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