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(parent: 4b1a9bd) | patch
Provide a template for busdma code for RISC-V.
authorbr <br@FreeBSD.org>
Tue, 7 May 2019 13:41:43 +0000 (13:41 +0000)
committerbr <br@FreeBSD.org>
Tue, 7 May 2019 13:41:43 +0000 (13:41 +0000)
commit64cb3b9636858172b70076288c80e9f0a8907bd1
tree0e79da0dd66c251744fa6bfa8c0d20afd5ddb02etree | snapshot
parent4b1a9bdef53ef8997ec798e79dc5959e24dba96fcommit | diff
Provide a template for busdma code for RISC-V.

RISC-V ISA specifies no cache management instructions so leave cache
operations in cpufunc.h as no-op for now.

Note some new hardware comes with their own memory-mapped cache
management controller.

Tested on HiFive Unleashed board with cgem(4).

Reviewed by: markj
Obtained from: arm64
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D20126
sys/conf/files.riscv diff | blob | history
sys/riscv/include/bus_dma.h diff | blob | history
sys/riscv/include/bus_dma_impl.h [new file with mode: 0644] blob
sys/riscv/include/cpufunc.h diff | blob | history
sys/riscv/riscv/busdma_bounce.c [new file with mode: 0644] blob
sys/riscv/riscv/busdma_machdep.c diff | blob | history
sys/riscv/riscv/machdep.c diff | blob | history
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