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(parent: d1cb8d1) | patch
msun fixes for SPE
authorJustin Hibbits <jhibbits@FreeBSD.org>
Wed, 5 May 2021 14:20:56 +0000 (09:20 -0500)
committerJustin Hibbits <jhibbits@FreeBSD.org>
Thu, 6 May 2021 01:57:33 +0000 (20:57 -0500)
commit6640579610856168a64e12c097ce012c46648e00
tree0bcea4610a3fd611751967ea186696d5476debd7tree | snapshot
parentd1cb8d11b0c09c35b87c144bab7b02b75c5725b6commit | diff
msun fixes for SPE

Summary:
Fix FPU exception management for powerpcspe.  Bits are in a different place from
the standard FPSCR, so we need to handle the shifting differences.  Also,
there's no concept of a "software exception" raise, so we need to do exceptional
math to trigger the exception from software.

Reviewed By: alfredo
Differential Revision: https://reviews.freebsd.org/D22824
lib/msun/powerpc/fenv.c diff | blob | history
lib/msun/powerpc/fenv.h diff | blob | history
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