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(parent: 42cb78b) | patch
Do not expose to scheduler caches of single CPU.
authorAlexander Motin <mav@FreeBSD.org>
Wed, 28 Jul 2021 20:15:43 +0000 (16:15 -0400)
committerAlexander Motin <mav@FreeBSD.org>
Wed, 11 Aug 2021 00:49:48 +0000 (20:49 -0400)
commit70a137b75e149611c101cb57e0322e370f669094
tree3157050a0a5ac606905123f1cb28c78de6b4d4bbtree | snapshot
parent42cb78bdd49cd9a3e834c1ba3a00c7413917c812commit | diff
Do not expose to scheduler caches of single CPU.

Before this change my dual-Xeon(R) Gold 6242R always reported 3 levels
or topology (root, package/L3 and core/L2).  But with SMT disabled
core/L2 matches thread, so additional topology level only causes more
traversal work.  With this change SMT case is reported same as before,
while non-SMT is reported with only 2 much more simple levels.

MFC after: 2 weeks

(cherry picked from commit 5a49f1914178c5275105f2ab0d23a98118cd585f)
sys/x86/x86/mp_x86.c diff | blob | history
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