Careful measurement of the ST Labs card shows that the pulse width of

Careful measurement of the ST Labs card shows that the pulse width of
transmitted bits was between 8.6180us and 8.6200us when we used a RCLK
of 16.500MHz.  This is a little low (should be 8.6805us).  This error
is exactly the error one would expect if it actually had a 16.384MHz
watch oscillator (as suggested by garrett) instead of using the PCI
RCLK.  Assume that the pci clock therefore wasn't really used, but
instead the cheap 16.384MH watch quartz oscillator.  This gives bits
in the 8.6800us to 8.6810us ranage, which matches theoretical.

Submitted by: garrett