jilles [Sun, 20 May 2018 17:25:52 +0000 (17:25 +0000)]
sh: Allow unquoted newlines in word in ${param+word} etc.
POSIX requires accepting unquoted newlines in word in parameter expansions
like ${param+word}, ${param#word}, although the Bourne shell did not support
it, it is not commonly used and might make it harder to find a missing
closing brace.
dumbbell [Sun, 20 May 2018 14:21:20 +0000 (14:21 +0000)]
teken, vt(4): Parse the "Cursor style" escape sequence
The escape sequence (e.g. `^[[2 q`) was unsupported before and the
letter `q` was displayed as a typed character. The sequence is used by
Neovim for instance.
Now, it is properly parsed. However, it is ignored, so it won't change
the cursor style.
Because the escape sequence contains a space character, the
`gensequences` script had to be modified to support that. In the
`sequences` file, a space is represented as the string `SP`.
eadler [Sun, 20 May 2018 05:06:42 +0000 (05:06 +0000)]
MFV: file 5.33
Merge the latest file(1) in.
Relevent Changelog:
- extend the support for ${x?:} expansions for magic descriptions
- add support for ${x?:} in mime types to handle pie binaries.
- add support for negative offsets (offsets from the end of file)
- close the file on error when writing magic
mjg [Sun, 20 May 2018 04:45:05 +0000 (04:45 +0000)]
vfs: simplify vop_stdlock/unlock
The interlock pointer is non-NULL by definition and the compiler see through
that and eliminates the NULL checks. Just remove them from the code as they
play no role.
mmacy [Sun, 20 May 2018 04:38:04 +0000 (04:38 +0000)]
inpcb: defer destruction of inpcb until after a grace period has elapsed
in_pcbfree will remove the incpb from the list and release the rtentry
while the vnet is set, but the actual destruction will be deferred
until any threads in a (not yet used) epoch section, no longer potentially
have references.
jhibbits [Sun, 20 May 2018 03:23:17 +0000 (03:23 +0000)]
Add support for the XIVE XICS emulation mode for POWER9 systems
Summary:
POWER9 systems use a new interrupt controller, XIVE, managed through OPAL
firmware calls. The OPAL firmware includes support for emulating the previous
generation XICS presentation layer in addition to a new "XIVE Exploitation"
mode. As a stopgap until we have XIVE exploitation mode, enable XICS emulation
mode so that we at least have an interrupt controller.
Since the CPPR is local to the current CPU, it cannot be updated for APs when
initializing on the BSP. This adds a new function, directly called by the
powernv platform code, to initialize the CPPR on AP bringup.
eadler [Sun, 20 May 2018 02:14:27 +0000 (02:14 +0000)]
top(1): Quiesce several warnings
This is all warnings at level six (6) that are not
char-subscripts, incompatible-pointer-types,
sign-compare, switch, int-conversion,
missing-variable-declarations, cast-qual, cast-align
Some warnings that are fixed by this commit are:
shadow, strict-prototypes, missing-prototypes, pointer-arith,
unused-parameter, unused-const-variable, and several others
mmacy [Sun, 20 May 2018 00:22:28 +0000 (00:22 +0000)]
ip(6)_freemoptions: defer imo destruction to epoch callback task
Avoid the ugly unlock / lock of the inpcbinfo where we need to
figure out what kind of lock we hold by simply deferring the
operation to another context. (Also a small dependency for
converting the pcbinfo read lock to epoch)
nwhitehorn [Sat, 19 May 2018 22:04:54 +0000 (22:04 +0000)]
Avoid writing to the frame buffer in early boot on PowerPC if the CPU's
MMU is disabled.
This expands some earlier logic and avoids a number of potential problems:
1. The CPU may not be able to access the framebuffer in real mode (real
mode does not necessarily encompass all available memory, especially
under a hypervisor).
2. Real mode accesses generally assume cacheability, so it might not
even have worked.
3. The difference in cacheability between real mode and later (and
potentially earlier) points in the boot with the MMU on may cause
ERAT parity problems, resulting in a machine check.
This fixes real-mode (usefdt=1) early boot on the G5 iMac, which was
previously broken as a result of issue #3. Late boot will require some
other fixups.
eadler [Sat, 19 May 2018 20:35:15 +0000 (20:35 +0000)]
my copyright: some minor adjustments
- remove "all rights reserved" from my copyright on my extensive
contributions
- belatedly add my name to tuning.7 which I was a large contributor to
several years ago
This commit can also serve as implicit permission for any formatting or
non-substantive changes that FreeBSD wishes to make in the future.
kib [Sat, 19 May 2018 20:28:59 +0000 (20:28 +0000)]
Fix PCID+PTI pmap operations on Xen/HVM.
Install appropriate pti-aware shootdown IPI handlers, otherwise user
page tables do not get enough invalidations. The non-pti handlers
were used so far.
Reported and tested by: cperciva
Sponsored by: The FreeBSD Foundation
MFC after: 3 days
markj [Sat, 19 May 2018 19:53:23 +0000 (19:53 +0000)]
Enable kernel dump features in GENERIC for most platforms.
This turns on support for kernel dump encryption and compression, and
netdump. arm and mips platforms are omitted for now, since they are more
constrained and don't benefit as much from these features.
imp [Sat, 19 May 2018 17:29:57 +0000 (17:29 +0000)]
Restore the all rights reserved language. Put it on each of the prior
two copyrights. The line originated with the Berkeely Regents, who
we have not approached about removing it (it's honestly too trivial
to be worth that fight). Restore it to rwatson's line as well. He
can decide if he wants it or not on his own. Matt clearly doesn't
want it, per project preference and his own statements on IRC.
mmacy [Sat, 19 May 2018 16:44:12 +0000 (16:44 +0000)]
mp_ring: fix i386
Even though 64-bit atomics are supported on i386 there are panics
indicating that the code does not work correctly there. Switch
to mutex based variant (and fix that while we're here).
jhibbits [Sat, 19 May 2018 04:21:50 +0000 (04:21 +0000)]
Add hypervisor trap handling, using HSRR0/HSRR1
Summary:
Some hypervisor exceptions on POWER architecture only save state to HSRR0/HSRR1.
Until we have bhyve on POWER, use a lightweight exception frontend which copies
HSRR0/HSRR1 into SRR0/SRR1, and run the normal trap handler.
The first user of this is the Hypervisor Virtualization Interrupt, which targets
the XIVE interrupt controller on POWER9.