Ed Maste [Thu, 26 Sep 2019 16:05:57 +0000 (16:05 +0000)]
Add WITH_PIE knob to build Position Independent Executables
MFC r344179: Add WITH_PIE knob to build Position Independent Executables
Building binaries as PIE allows the executable itself to be loaded at a
random address when ASLR is enabled (not just its shared libraries).
With this change PIE objects have a .pieo extension and INTERNALLIB
libraries libXXX_pie.a.
MK_PIE is disabled for some kerberos5 tools, Clang, and Subversion, as
they explicitly reference .a libraries in their Makefiles. These can
be addressed on an individual basis later. MK_PIE is also disabled for
rtld-elf because it is already position-independent using bespoke
Makefile rules.
Currently only dynamically linked binaries will be built as PIE.
MFC r344181: Fix Makefile conditional after r344179
MFC r344182: Use make's :tl instead of checking "no" and "NO"
MFC r344189: Fixup bsd.prog.mk after r344182
MFC r344211: wlandebug: disable PIE to fix build failure
libifconfig is built as a static-only PRIVATELIB (and there is no _pie.a
version) so disable PIE in libifconfig's consumer.
r345489: Fix GNU objdump build under WITH_PIE
Explicitly specified bare .a libraries need ${PIE_SUFFIX}.
r345490: Apply WITH_PIE changes to other binutils components
Followon to r345489, explicitly specified bare .a libraries need
${PIE_SUFFIX} (although these still built).
r345778: Fix gdb/kgdb build under WITH_PIE
Explicitly specified bare .a libraries need ${PIE_SUFFIX}.
Ed Maste [Thu, 26 Sep 2019 15:50:18 +0000 (15:50 +0000)]
Add a WITH_BIND_NOW build knob
MFC r340186: Add a WITH_BIND_NOW build knob
The linker's -z now flag sets the DF_BIND_NOW flag, which signals to the
runtime loader that all relocation processing should be performed at
process startup rather than on demand. In combination with lld's
default of enabling relro this causes the GOT to be made read-only when
the process starts, preventing straightforward GOT overwrite attacks.
MFC r341429: disable BIND_NOW in libc, libthr, and rtld
An issue remains with BIND_NOW and processes using threads. For now,
restore libc's BIND_NOW disable, and also disable BIND_NOW in rtld and
libthr.
MFC r345625: revert r341429 "disable BIND_NOW in libc, libthr, and rtld"
r345620 by kib@ fixed the rtld issue that caused a crash at startup
during resolution of libc's ifuncs with BIND_NOW.
MFC r345638: Revert change accidentally committed along with r345625
MFC r345640: Revert other accidentally committed part of r345625
Warner Losh [Thu, 26 Sep 2019 12:54:52 +0000 (12:54 +0000)]
mpr/mps crash badly. Part of the stability added use of atomic64 functions not
present on 32-bit powerpc. Merge the part that removes mps from the build
on this tier 2 platform. Working mpr/mps in 12 and 12.1 on our tier 1 platforms
is more important.
MFC r341754:
Remove the mps driver from powerpc 32bit GENERIC, and don't build it and mpr
as a module for powerpc or mips. An upcoming commit will cause these drivers
to rely on the presence of 64bit atomic operations. Discussed with jhibbits.
r341755:
Copy and clear the reply descriptor atomically. This prevents concurrency
in the interrupt handlers (usually due to timeout/error recovery) from
seeing and processing the same descriptor twice.
r342354:
mps(4), mpr(4): Fix lifetime of command buffer for mp?sas_get_sata_identify
r342355:
mps(4), mpr(4): remove SATA ID command cancellation hack
r342386:
First step in refactoring and fixing the error recovery and task management
code in the mpr and mps drivers. Eliminate duplicated code and fix some
comments.
r342387:
Commands for user-initated device resets should come from the high-priority
allocator. Prior to this change, they would leak from the normal
allocator.
r342388:
Further refactoring for task management commands. Also fix a related typo
from the previous commit.
r342526:
Update MPI header files version to 2.00.52 from 2.00.48
r342528:
Copy back the Sense data at proper location expected by the application
r342530:
Added support for NVMe Task Management
r342531:
Add Sea,Aero adapter support
r342533:
Enable atomic type descriptor support only for Sea & Aero cards
r342534:
On Aero/Sea A0 cards retry MPT Fusion registers reads for max three times
r342535:
Update copyright information
r342536:
Update mpr driver version to v23.00.00.00-fbsd
r342659:
Fix whitespace from r342528
r345479:
r329522 created problemss with commands that enter the TIMEDOUT state but
are successfully returned by the card (usually due to an abort being issued
as part of timeout recovery). Remove what amounts to an insufficient
KASSERT, and don't overwrite the state value. State should probably be
re-designed, and that will be done with a future commit.
r345485:
Add event table decoding for SAS Broadcast Primitive events.
r345573:
Add missing break statements. Coverity CID 1400446.
r347237:
Add missing newline to debug printf.
r349849:
Fix bugs in recovery path and improve cm tracking
r349909:
More fully implement the state machine.
The long double aliases of double functions are only exposed as aliases if
LDBL_MANT_DIG is 53 (same as DBL_MANT_DIG). Without float.h included these
files were not exposing weak aliases as expected, leading to link failures
if programs use the *l functions. This should fix editors/calligra on
targets with 64-bit long double, which uses erfl and erfcl. Found on
powerpc64.
MFC r352564: msdosfs: do not deget unlinked denodes
When a file is unlinked, the denode is not reclaimed until the last
reference is dropped, but the directory entry is immediately up for reuse.
This is a problem later when createde goes to grab a denode for the newly
created entry -- we search the hash and find a dead denode, then return that
without even bumping the reference count and the data later gets truncated
when the the last reference to the unlinked file is dropped.
This manifested itself as a broken in-place strip(1) on msdosfs.
The comment indicating that we want to skip these denodes has been updated
to reflect where this is actually done.
Michael Tuexen [Wed, 25 Sep 2019 10:46:05 +0000 (10:46 +0000)]
MFC r352594:
Don't hold the info lock when calling sctp_select_a_tag().
This avoids a double lock bug in the NAT colliding state processing
of SCTP. Thanks to Felix Weinrank for finding and reporting this issue in
https://github.com/sctplab/usrsctp/issues/374
He found this bug using fuzz testing.
Michael Tuexen [Wed, 25 Sep 2019 10:44:10 +0000 (10:44 +0000)]
MFC r352592:
Cleanup the RTO calculation and perform some consistency checks
before computing the RTO.
This should fix an overflow issue reported by Felix Weinrank in
https://github.com/sctplab/usrsctp/issues/375
for the userland stack and found by running a fuzz tester.
Michael Tuexen [Wed, 25 Sep 2019 10:42:34 +0000 (10:42 +0000)]
MFC r352550:
Fix the handling of invalid parameters in ASCONF chunks.
Thanks to Mark Wodrich from Google for reproting the issue in
https://github.com/sctplab/usrsctp/issues/376
for the userland stack.
Michael Tuexen [Wed, 25 Sep 2019 10:40:49 +0000 (10:40 +0000)]
MFC r352512:
When the RACK stack computes the space for user data in a TCP segment,
it wasn't taking the IP level options into account. This patch fixes this.
In addition, it also corrects a KASSERT and adds protection code to assure
that the IP header chain and the TCP head fit in the first fragment as
required by RFC 7112.
Reviewed by: rrs@
Sponsored by: Netflix, Inc.
Differential Revision: https://reviews.freebsd.org/D21666
Michael Tuexen [Wed, 25 Sep 2019 10:38:44 +0000 (10:38 +0000)]
MFC r352511:
When processing an incoming IPv6 packet over the loopback interface which
contains Hop-by-Hop options, the mbuf chain is potentially changed in
ip6_hopopts_input(), called by ip6_input_hbh().
This can happen, because of the the use of IP6_EXTHDR_CHECK, which might
call m_pullup().
So provide the updated pointer back to the called of ip6_input_hbh() to
avoid using a freed mbuf chain in`ip6_input()`.
Reviewed by: markj@
Sponsored by: Netflix, Inc.
Differential Revision: https://reviews.freebsd.org/D21664
Hiroki Sato [Sat, 21 Sep 2019 14:03:41 +0000 (14:03 +0000)]
MFC r352567:
Add a workaround for servers which respond RPC_PROGNOTREGISTERED
to a clnt_create() call even when it is actually a program
version mismatch.
Normally the server is supposed to return RPC_PROGVERSMISMATCH
when it supports the specified program but not support
the specified version. Some filers return RPC_PROGNOTREGISTERED
to RQUOTA v2 calls and FreeBSD does not retry with the old
v1 calls. This change fixes this failure scenario.
MFC r352246: SIOCSIFNAME: Do nothing if we're not actually changing
Instead of throwing EEXIST, just succeed if the name isn't actually
changing. We don't need to trigger departure or any of that because there's
no change from consumers' perspective.
Michael Zhilin [Fri, 20 Sep 2019 19:56:30 +0000 (19:56 +0000)]
MFC r352260:
[Bug 240473] add support of Ralink RT5390R Wireless Card
This commit adds PCI ID of Ralink RT5390R into ids table of driver ral.
Tests show stability of card during day. Network speed is reasonable (
around several megabytes per second).
PR: https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=240473
Reported by: zetrotrack000@gmail.com
Reviewed by: ray
Approved by: ray
Differential Revision: https://reviews.freebsd.org/D21604
Michael Zhilin [Fri, 20 Sep 2019 19:45:37 +0000 (19:45 +0000)]
MFC r352263:
[jail] removal by jid doesn't trigger pre/post stop scripts
This commit fixes bug: command "jail -r" didn't trigger pre/post stop
commands (and others) defined in config file if jid is specified insted of
name. Also it adds basic tests for usr.sbin/jail to avoid regression.
Reviewed by: jamie, kevans, ray
Differential Revision: https://reviews.freebsd.org/D21328
Alan Cox [Thu, 19 Sep 2019 20:45:23 +0000 (20:45 +0000)]
MF r349585
Tidy up pmap_copy(). Notably, deindent the innermost loop by making a
simple change to the control flow. Replace an unnecessary test by a
KASSERT. Add a comment explaining an obscure test.
MFC r352520 (partial):
The original commit was a direct commit to stable/12, as at the time it
was presumed it would not be necessary for head. However, when it is
time to create a releng branch or switch from PRERELEASE/STABLE to
BETA/RC, the pkg(7) Makefile needs further adjusting. This commit
includes those further adjustments, evaluating the BRANCH variable from
release/Makefile to determine the pkg(7) repository to use.
Alan Cox [Thu, 19 Sep 2019 15:12:32 +0000 (15:12 +0000)]
MFC r350335:
Simplify the handling of superpages in pmap_clear_modify(). Specifically,
if a demotion succeeds, then all of the 4KB page mappings within the
superpage-sized region must be valid, so there is no point in testing the
validity of the 4KB page mapping that is going to be write protected.
Alan Cox [Thu, 19 Sep 2019 14:36:30 +0000 (14:36 +0000)]
MFC r349526:
When we protect PTEs (as opposed to PDEs), we only call vm_page_dirty()
when, in fact, we are write protecting the page and the PTE has PG_M set.
However, pmap_protect_pde() was always calling vm_page_dirty() when the PDE
has PG_M set. So, adding PG_NX to a writeable PDE could result in
unnecessary (but harmless) calls to vm_page_dirty().
Simplify the loop calling vm_page_dirty() in pmap_protect_pde().
Jayachandran C. [Wed, 18 Sep 2019 23:30:27 +0000 (23:30 +0000)]
MFC r339517:
arm generic_timer: fix armv8 timer desc
In the FDT based probe, check for "arm,armv8-timer" before "arm,armv7-timer".
This gets the description right when the timer node has both entries in
compatible list.
Jayachandran C. [Wed, 18 Sep 2019 23:23:34 +0000 (23:23 +0000)]
MFC r348377-r348379, r349347
r348377:
gic_v3: consolidate per-cpu redistributor information
Update 'struct gic_redists' to consolidate all per-cpu redistributor
information into a new 'struct redist_pcpu'. Provide a new interface
(GICV3_IVAR_REDIST) for the GIC driver, which can be used to retrieve
the per-cpu data.
This per-cpu redistributor struct will be later used to improve the
GIC ITS setup.
While there, remove some unused fields in gic_v3_var.h interface.
No functional changes.
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D19842
r348378:
gicv3_its: refactor LPI init into a new function
Move the per-cpu LPI intialization to a separate function. This is
in preparation for a commit that does LPI init only once for a CPU,
even when there are multiple ITS blocks associated with the CPU.
No functional changes in this commit.
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D19843
r348379:
gicv3_its: do LPI init only once per CPU
The initialization required for LPIs (setting up pending tables etc.)
has to be done just once per CPU, even in the case where there are
multiple ITS blocks associated with the CPU.
Add a flag lpi_enabled in the per-cpu distributor info for this and
use it to ensure that we call its_init_cpu_lpi() just once.
This enables us to support platforms where multiple GIC ITS blocks
can generate LPIs to a CPU.
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D19844
r349347:
arm64 gicv3_its: enable all ITS blocks for a CPU
We now support multiple ITS blocks raising interrupts to a CPU.
Add all available CPUs to the ITS when no NUMA information is
available.
This reverts the check added in r340602, at that tim we did not
suppport multiple ITS blocks for a CPU.
Jayachandran C. [Wed, 18 Sep 2019 23:18:26 +0000 (23:18 +0000)]
MFC r349348:
arm64 acpi_iort: add some error handling
Print warnings for some bad kernel configurations (like NUMA disabled
with multiple domains). Check and report some firmware errors (like
incorrect proximity domain entries).
Jayachandran C. [Wed, 18 Sep 2019 23:12:07 +0000 (23:12 +0000)]
MFC r348291:
arm64 nexus: remove incorrect warning
acpi_config_intr() will be called when an arm64 system booted with ACPI.
We do the interrupt mapping for ACPI interrupts in nexus_acpi_map_intr()
on arm64, so acpi_config_intr() has to just return success without
printing this error message.
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D19432
Jayachandran C. [Wed, 18 Sep 2019 23:08:51 +0000 (23:08 +0000)]
MFC r343853, r343856, r343860
r343853:
arm64 acpi: Add support for IORT table
Add new file arm64/acpica/acpi_iort.c to support the "IO Remapping
Table" (IORT). The table is specified in ARM document "ARM DEN 0049D"
titled "IO Remapping Table Platform Design Document". The IORT table
has information on the associations between PCI root complexes, SMMU
blocks and GIC ITS blocks in the system.
The changes are to parse and save the information in the IORT table.
The API to use this information is added to sys/dev/acpica/acpivar.h.
The acpi_iort.c also has code to check the GIC ITS nodes seen in the
IORT table with corresponding entries in MADT table (for validity)
and with entries in SRAT table (for proximity information).
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D18002
r343856:
arm64 gicv3: add IORT and NUMA support
acpi_iort.c has added support to query GIC proximity and MSI XREF
ID for GIC ITS blocks. Use this when GIC ITS blocks are initialized
from ACPI.
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D18003
r343860:
pci_host_generic_acpi: use IORT data for MSI/MSI-X
Use the information from IORT parsing to translate the PCI RID to
GIC ITS device ID. And similarly, use the information to find the
PIC XREF identifier to be used for PCI devices.
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D18004
Jayachandran C. [Wed, 18 Sep 2019 22:55:24 +0000 (22:55 +0000)]
MFC r341743-r341744
r341743:
acpica: support parsing of arm64 affinity in acpi_pxm.c
ACPI SRAT table on arm64 uses GICC entries to provide CPU locality
information. These entries use an AcpiProcessorUid to identify the
CPU (unlike on x86 where the entries have an APIC ID).
Update acpi_pxm.c to extend the cpu_add/cpu_find/cpu_get_info
functions to handle AcpiProcessorUid. Use the updated functions
while parsing ACPI_SRAT_GICC_AFFINITY entry for arm64.
Also update sys/conf/files.arm64 to build acpi_pxm.c when ACPI is
enabled.
Jayachandran C. [Wed, 18 Sep 2019 22:44:59 +0000 (22:44 +0000)]
MFC r341741-r341742
r341741:
x86/acpica/srat.c: Add API for parsing proximity tables
The SLIT and SRAT ACPI tables needs to be parsed on arm64 as well, on
systems that use UEFI/ACPI firmware and support NUMA. To do this, we
need to move most of the logic of x86/acpica/srat.c to dev/acpica and
provide an API that architectures can use to parse and configure ACPI
NUMA information.
This commit adds the API in srat.c as a first step, without making any
functional changes. We will move the common code to sys/dev/acpica
as the next step.
The functions added are:
* int acpi_pxm_init(int ncpus, vm_paddr_t maxphys) - to allocate and
initialize data structures used
* void acpi_pxm_parse_tables(void) - parse SRAT/SLIT, save the cpu and
memory proximity information
* void acpi_pxm_set_mem_locality(void) - use the saved data to set
memory locality
* void acpi_pxm_set_cpu_locality(void) - use the saved data to set cpu
locality
* void acpi_pxm_free(void) - free data structures allocated by init
On arm64, we do not have an cpu APIC id that can be used as index to
store CPU data, we need to use the Processor Uid. To help with this,
define internal functions cpu_add, cpu_find, cpu_get_info to store
and get CPU proximity information.
r341742:
acpica : move SRAT/SLIT parsing to sys/dev/acpica
This moves the architecture independent parts of sys/x86/acpica/srat.c
to sys/dev/acpica/acpi_pxm.c, to be used later on arm64. The function
declarations are moved to sys/dev/acpica/acpivar.h
We also need to update sys/conf/files.{i386,amd64} to use the new file.
No functional changes.
MFC r351819: procstat/tests: Fix flakiness by waiting for program to start
Some of the procstat tests start a program "while1" and examine the process
using procstat, but did not wait properly for it to start (kill -0 will
succeed immediately after the child process has been created).
Instead, have "while1" write something when it starts, and use a fifo to
wait for that.
Alan Somers [Wed, 18 Sep 2019 17:18:09 +0000 (17:18 +0000)]
MFC r351192, r351203
r351192:
periodic: fix anticongestion for scripts run after security
Revision 316342, which introduced the anticongestion feature, failed to
consider that the periodic scripts are executed by a recursive invocation of
periodic. The recursive invocation wrongly cleaned up a temporary file that
should've been cleaned up only by the original invocation. The result is
that if the first script that requests an anticongestion sleep runs after
the security scripts, the sleep won't happen.
Fix this bug by delaying cleanup until the end of the original invocation.
Alan Cox [Wed, 18 Sep 2019 14:38:42 +0000 (14:38 +0000)]
MFC r349768
Restructure cache_handle_range to avoid repeated barriers. Specifically,
restructure cache_handle_range so that all of the data cache operations are
performed before any instruction cache operations. Then, we only need one
barrier between the data and instruction cache operations and one barrier
after the instruction cache operations.
On an Amazon EC2 a1.2xlarge instance, this simple change reduces the time
for a "make -j8 buildworld" by 9%.
Alan Cox [Wed, 18 Sep 2019 14:27:09 +0000 (14:27 +0000)]
MFC r350546
Because of AArch64's weak memory consistency model, we need to include a
memory barrier between the stores for initializing a page table page and
the store for adding that page to the page table. Otherwise, a page table
walk by another processor's MMU could see the page table page before it
sees the initialized entries.
Simplify pmap_growkernel(). In particular, eliminate an unnecessary TLB
invalidation.
Alan Cox [Wed, 18 Sep 2019 07:25:04 +0000 (07:25 +0000)]
MFC r350463
In pmap_advise(), when we encounter a superpage mapping, we first demote
the mapping and then destroy one of the 4 KB page mappings so that there
is a potential trigger for repromotion. Currently, we destroy the first
4 KB page mapping that falls within the (current) superpage mapping or the
virtual address range [sva, eva). However, I have found empirically that
destroying the last 4 KB mapping produces slightly better results,
specifically, more promotions and fewer failed promotion attempts.
Accordingly, this revision changes pmap_advise() to destroy the last 4 KB
page mapping. It also replaces some nearby uses of boolean_t with bool.
Jayachandran C. [Wed, 18 Sep 2019 07:22:37 +0000 (07:22 +0000)]
MFC r340602:
gitv3_its: fixes for multiple GIC ITS blocks
First pass of support for multiple GIC ITS blocks with ACPI.
Changes are to:
* register the correct subset of interrupts with pic_register
in case of ACPI.
* initialize just the cpu interface for the first ITS, when
domain information is not avialable. This has to be done
until we split the per-CPU init to do LPI setup just once.
* remove duplicate check for the GIC ITS domain, the sc_cpus
are setup from domain, so the check again in per-CPU init
seems unnecessary.
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D17841
This is a major update for pci_host_generic_acpi.c, the current
implementation has some gaps that are better fixed up in one go.
The changes are to:
* Follow x86 method of not adding PCI resources to PCI host bridge in
ACPI code. This has been moved to pci_host_generic_acpi.c, where we
walk thru its resources of the host bridge and add them.
* Fixup code in pci_host_generic_acpi.c to read all decoded ranges
and update the 'ranges' property. This allows us to share most of
the code with generic implementation (and the FDT one).
* Parse and setup IO ranges and bus ranges when walking the resources
above. Drop most of the changes related to this from acpica code.
* Add the ECAM memory area as mem resource 0. Implement the logic to
get the ECAM area from MCFG (using bus range which we now decode),
or from _CBA (using _BBN/bus range). Drop aarch64 ifdefs from acpica
code which did part of this.
* Switch resource activation to similar code as FDT implementation,
this can be moved into generic implementation in a later pass.
* Drop the mechanism of using the 7th bit of bus number as the domain,
this is not correct and will work only in very specific cases. Use
_SEG as PCI domain and use the bus ranges of the host bridge to
provide start bus number.
This commit should not make any functional change to dev/acpica/acpi.c
for other architectures, almost all the changes there are to revert
earlier additions in this file done for aarch64.
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D17791
r340600:
pci_host_generic, acpi_resource: drop unneeded code
Now that we are handling PCI resources in pci_host_generic_acpi.c, we
don't need these change (made by r336129)
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D17792
r340601:
pci_host_generic : move activate/release to generic code
Now that the ACPI and FDT implementations for activating and
deactivating resources are the same, we can move it to
pci_host_generic.c. No functional changes.
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D17793
Jayachandran C. [Wed, 18 Sep 2019 07:09:16 +0000 (07:09 +0000)]
MFC r340598:
acpica: rework INTRNG interrupts
On arm64 (where INTRNG is enabled), the interrupts have to be mapped
with ACPI_BUS_MAP_INTR() before adding them as resources to devices.
The earlier code did the mapping before calling acpi_set_resource(),
which bypassed code that checked for PCI link interrupts.
To fix this, move the call to map interrupts into acpi_set_resource()
and that requires additional work to lookup interrupt properties.
The changes here are to:
* extend acpi_lookup_irq_handler() to lookup an irq in the ACPI
resources
* create a helper function acpi_map_intr() which uses the updated
acpi_lookup_irq_handler() to look up an irq, and then map it
with ACPI_BUS_MAP_INTR()
* use acpi_map_intr() in acpi_pcib_route_interrupt() to map
pci link interrupts.
With these changes, we can drop the ifdefs in acpi_resource.c, and
we can also drop the call for mapping interrupts in generic_timer.c
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D17790
The current quirk implementation writes a fixed address to the PCI BAR
to fix a firmware bug. The PCI BARs are allocated by firmware and will
change depending on PCI devices present. So using a fixed address here
is not correct.
This quirk worked around a firmware bug that programmed the MSI-X bar
of the SATA controller incorrectly. The newer firmware does not have
this issue, so it is better to drop this quirk altogether.
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D17655
r340596:
pci_host_generic: allocate resources against devices
Fix up pci_host_generic.c and pci_host_generic_fdt.c to allocate
resources against devices that requested them. Currently the
allocation happens against the pcib, which is incorrect.
This is needed for the upcoming changes for fixing up
pci_host_generic_acpi.c
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D17656
r340597:
pci_host_generic*: basic implementation of bus range
Both ACPI and FDT support bus ranges for pci host bridges. Update
pci_host_generic*.[ch] with a default implementation to support this.
This will be used in the next set of changes for ACPI based host
bridge. No functional changes in this commit.
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D17657
r349117:
Three enhancements to arm64's pmap_protect():
Implement protection changes on superpage mappings. Previously, a superpage
mapping was unconditionally demoted by pmap_protect(), even if the
protection change applied to the entire superpage mapping.
Precompute the bit mask describing the protection changes rather than
recomputing it for every page table entry that is changed.
Skip page table entries that already have the requested protection changes
in place.
r349122:
Three changes to arm64's pmap_unwire():
Implement wiring changes on superpage mappings. Previously, a superpage
mapping was unconditionally demoted by pmap_unwire(), even if the wiring
change applied to the entire superpage mapping.
Rewrite a comment to use the arm64 names for bits in a page table entry.
Previously, the bits were referred to by their x86 names.
Use atomic_"op"_64() instead of atomic_"op"_long() to update a page table
entry in order to match the prevailing style in this file.
r349183:
Correct an error in r349122. pmap_unwire() should update the pmap's wired
count, not its resident count.
r349897: (by markj)
Rename pmap_page_dirty() to pmap_pte_dirty().
This is a precursor to implementing dirty bit management.
r349943: (by markj)
Apply some light cleanup to uses of pmap_pte_dirty().
- Check for ATTR_SW_MANAGED before anything else.
- Use pmap_pte_dirty() in pmap_remove_pages().
r350004: (by markj)
Implement software access and dirty bit management for arm64.
Previously the arm64 pmap did no reference or modification tracking;
all mappings were treated as referenced and all read-write mappings
were treated as dirty. This change implements software management
of these attributes.
Dirty bit management is implemented to emulate ARMv8.1's optional
hardware dirty bit modifier management, following a suggestion from alc.
In particular, a mapping with ATTR_SW_DBM set is logically writeable and
is dirty if the ATTR_AP_RW_BIT bit is clear. Mappings with
ATTR_AP_RW_BIT set are write-protected, and a write access will trigger
a permission fault. pmap_fault() handles permission faults for such
mappings and marks the page dirty by clearing ATTR_AP_RW_BIT, thus
mapping the page read-write.
r350029: (by markj)
Propagate attribute changes during demotion.
After r349117 and r349122, some mapping attribute changes do not trigger
superpage demotion. However, pmap_demote_l2() was not updated to ensure
that the replacement L3 entries carry any attribute changes that
occurred since promotion.
r350038: (by markj)
Always use the software DBM bit for now.
r350004 added most of the machinery needed to support hardware DBM
management, but it did not intend to actually enable use of the hardware
DBM bit.
r350191:
Introduce pmap_store(), and use it to replace pmap_load_store() in places
where the page table entry was previously invalid. (Note that I did not
replace pmap_load_store() when it was followed by a TLB invalidation, even
if we are not using the return value from pmap_load_store().)
Correct an error in pmap_enter(). A test for determining when to set
PGA_WRITEABLE was always true, even if the mapping was read only.
In pmap_enter_l2(), when replacing an empty kernel page table page by a
superpage mapping, clear the old l2 entry and issue a TLB invalidation. My
reading of the ARM architecture manual leads me to believe that the TLB
could hold an intermediate entry referencing the empty kernel page table
page even though it contains no valid mappings.
Replace a couple direct uses of atomic_clear_64() by the new
pmap_clear_bits().
In a couple comments, replace the term "paging-structure caches", which is
an Intel-specific term for the caches that hold intermediate entries in the
page table, with wording that is more consistent with the ARM architecture
manual.
r350202:
With the introduction of software dirty bit emulation for managed mappings,
we should test ATTR_SW_DBM, not ATTR_AP_RW, to determine whether to set
PGA_WRITEABLE. In effect, we are currently setting PGA_WRITEABLE based on
whether the dirty bit is preset, not whether the mapping is writeable.
Correct this mistake.
r350422: (by markj)
Remove an unneeded trunc_page() in pmap_fault().
r350427: (by markj)
Have arm64's pmap_fault() handle WnR faults on dirty PTEs.
If we take a WnR permission fault on a managed, writeable and dirty
PTE, simply return success without calling the main fault handler. This
situation can occur if multiple threads simultaneously access a clean
writeable mapping and trigger WnR faults; losers of the race to mark the
PTE dirty would end up calling the main fault handler, which had no work
to do.
r350525: (by markj)
Use ATTR_DBM even when hardware dirty bit management is not enabled.
The ARMv8 reference manual only states that the bit is reserved in
this case; following Linux's example, use it instead of a
software-defined bit for the purpose of indicating that a managed
mapping is writable.
Andrew Turner [Tue, 17 Sep 2019 10:09:59 +0000 (10:09 +0000)]
MFC r343042, r343875
r343042:
Ensure the I-Cache is correctly handled in arm64_icache_sync_range
The cache_handle_range macro to handle the arm64 instruction and data
cache operations would return when it was complete. This causes problems
for arm64_icache_sync_range and arm64_icache_sync_range_checked as they
assume they can execute the i-cache handling instruction after it has been
called.
Fix this by making this assumption correct.
While here add missing instruction barriers and adjust the style to
match the rest of the assembly.
Andrew Turner [Tue, 17 Sep 2019 10:00:53 +0000 (10:00 +0000)]
MFC r342552:
Pass VM_PROT_EXECUTE to vm_fault for instruction faults.
We need to tell vm_fault the reason for the fault was because we tried to
execute from the memory location. Without this it may return with success
as we only request read-only memory, then we return to the same location
and try to execute from the same memory address. This leads to an infinite
loop raising the same fault and returning to the same invalid location.
While here, mark all non-standard ones as FreeBSD-only as
other systems (at least, GNU/Linux and illumos) do not handle
them, so we should not encourage their use.
- make abday, day, abmon, mon, am_pm output quoting match linux
- workaround localeconv() issue for mon_grouping and grouping (PR172215)
- for other values not available in default locale, output -1 instead of
127 (CHAR_MAX) as returned by localeconv()
Andrew Turner [Mon, 16 Sep 2019 15:00:11 +0000 (15:00 +0000)]
MFC r342937:
Fix the location of td->td_frame at the top of the kernel stack.
In cpu_thread_alloc we would allocate space for the trap frame at the top of
the kernel stack. This is just below the pcb, however due to a missing cast
the pointer arithmetic would use the pcb size, not the trapframe size. As
the pcb is larger than the trapframe this is safe, however later in cpu_fork
we include the case leading to the two disagreeing on the location.
Fix by using the same arithmetic in both locations.
Found by: An early KASAN patch
Sponsored by: DARPA, AFRL
Andrew Turner [Mon, 16 Sep 2019 14:35:02 +0000 (14:35 +0000)]
MFC r339948:
Use pmap_invalidate_all rather than invalidating 512 level 2 entries in
the early pmap_mapbios/unmapbios code. It is even worse when there are
multiple L2 entries to handle as we would need to iterate over all pages.
Andrew Turner [Mon, 16 Sep 2019 14:25:51 +0000 (14:25 +0000)]
MFC r348323:
The alignment is passed into contigmalloc_domainset in the 7th argument.
KUBSAN was complaining the pointer contigmalloc_domainset returned was
misaligned. Fix this by using the correct argument to find the alignment
in the function signature.
Andrew Turner [Mon, 16 Sep 2019 14:07:30 +0000 (14:07 +0000)]
MFC r343876:
Add missing data barriers after storeing a new valid pagetable entry.
When moving from an invalid to a valid entry we don't need to invalidate
the tlb, however we do need to ensure the store is ordered before later
memory accesses. This is because this later access may be to a virtual
address within the newly mapped region.
Add the needed barriers to places where we don't later invalidate the
tlb. When we do invalidate the tlb there will be a barrier to correctly
order this.
This fixes a panic on boot on ThunderX2 when INVARIANTS is turned off:
panic: vm_fault_hold: fault on nofault entry, addr: 0xffff000040c11000
Andrew Turner [Mon, 16 Sep 2019 13:45:31 +0000 (13:45 +0000)]
MFC r346996:
Restore x18 in efi_arch_leave.
Some UEFI implementations trash this register and, as we use it as a
platform register, the kernel doesn't save it before calling into the UEFI
runtime services. As we have a copy in tpidr_el1 restore from there when
exiting the EFI environment.
MFC the BSD crtbegin to stable/12 but keep it disabled.
r339738:
Implement a BSD licensed crtbegin/crtend
These are needed for .ctors/.dtors and .jcr handling. The former needs
all the function pointers to be called in the correct order from the
.init/.fini section. The latter just needs to call a gcj specific function
if it exists with a pointer to the start of the .jcr section.
This is currently disabled until __dso_handle support is added.
r339744:
Add a missing include for src.opts.mk. Without it MK_TESTS isn't defined.
MFC with: r339738
Sponsored by: DARPA, AFRL
r339770:
Drop the csu tests WARNS to 5 to fix the powerpc64 build.
MFC with: r339738
Sponsored by: DARPA, AFRL
r339773:
Add __dso_handle to the BSD crtbegin. This is used to identify shared
objects.
MFC with: r339738
Sponsored by: DARPA, AFRL
r339864:
Check __dso_handle is NULL in non-DSO objects. It should only be non-NULL
when accessed from a shared object.
MFC with: r339738
Sponsored by: DARPA, AFRL
r339865:
Include the csu test directories in BSD.tests.dist
MFC with: r339738
Sponsored by: DARPA, AFRL
r339866:
Make the .ctors, .dtors, and .jcr markers as static. They shouldn't be
accessible from out of the files they are defined in.
MFC with: r339738
Sponsored by: DARPA, AFRL
r339907:
The jcr argument to _Jv_RegisterClasses is used, stop marking it otherwise.
MFC with: r339738
Sponsored by: DARPA, AFRL
r339908:
Run the csu tests on a DSO. This builds the tests into a shared library,
then runs these from the base test programs. With this we can check
crtbeginS.o and crtendS.o are working as expected.
MFC with: r339738
Sponsored by: DARPA, AFRL
r339912:
Fix the location of the static keyword.
MFC with: r339738
Sponsored by: DARPA, AFRL
r339913:
Disable the .preinit_array test in DSOs, ld.bfd fails to link objects with
the section.
MFC with: r339738
Sponsored by: DARPA, AFRL
r339916:
Build the csu tests on all architectures.
The tests haven't been run them, but this is enough to build them so I can
get feedback on if the various crt.h headers are correct.
MFC with: r339738
Sponsored by: DARPA, AFRL
r339954:
Add __used to __CTOR_LIST__ and __DTOR_LIST__
Enabling BSD_CRTBEGIN on amd64 resulted in
error: unused variable '__CTOR_LIST__'.
__CTOR_LIST__ is indeed unused in crtbegin.c; it marks the beginning of
the .ctors array and is used in crtend.c. Annotate __DTOR_LIST__ as
well for consistency.
Discussed with: andrew
MFC with: r339738
Sponsored by: The FreeBSD Foundation
r340213:
Add the (untested) mips and sparc64 .init call sequences.
The BSD crtbegin/crtend code now builds on all architectures, however
further work is needed to check if it works correctly.
MFC with: r339738
Sponsored by: DARPA, AFRL
r340395:
Run __cxa_finalize in shared objects in the destructor path.
When we have .dtors call them before .dtor handling, otherwise call from
a destructor.
r340840:
Mark the function called by the MIPS .init/.fini sequence with .local.
As with r328939 we need to mark local symbols as such. Without this the
assembly parser treats the symbols as global and created relocations
against these private symbols.
MFC with: r339738
Sponsored by: DARPA, AFRL
r340910:
Add the missing 0 at the end of the .jcr section.
Without this the dynamic library test was failing as it was calling
_Jv_RegisterClasses multiple times.
r340911:
Re-enable the dynamiclib tests. These should be fixed by r340910.
r341424:
Disable the BSD CRT code on powerpc and sparc64, they need extra crt*.o
files that haven't been implemented.
lib/csu/tests/dynamiclib requires libh_csu.so be built first. I'm not
sure this is the most correct/best way to address this but it solves
the issue in my testing.
PR: 233734
Sponsored by: The FreeBSD Foundation
r342974:
Create crtsavres.o for powerpc builds
Summary:
GCC expects to link in a crtsavres.o on powerpc platforms. On
powerpc64 this is an empty file, but on powerpc and powerpcspe this does contain
some save/restore functions, which may not actually be necessary for newer
modern GCC and clang. This appeases the in-tree gcc, though, and is needed in
order to switch to the BSD CRTRBEGIN.
PR: 233751
Reviewed By: andrew
Differential Revision: https://reviews.freebsd.org/D18826
r351027:
Enable BSD_CRTBEGIN on powerpc
In r342974 jhibbits added support to build crtsavres.o. This was the
blocker for BSD_CRTBEGIN to be enabled there. As such enable this
option again.
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