Michal Meloun [Fri, 8 Nov 2019 18:57:41 +0000 (18:57 +0000)]
Implement support for (soft)linked clocks.
This kind of clock nodes represent temporary placeholder for clocks
defined later in boot process. Also, these are necessary to break
circular dependencies occasionally occurring in complex clock graphs.
bhyve: add support for virtio-net mergeable rx buffers
Mergeable rx buffers is a virtio-net feature that allows the hypervisor
to use multiple RX descriptor chains to receive a single receive packet.
Without this feature, a TSO-enabled guest is compelled to publish only
64K (or 32K) long chains, and each of these large buffers is consumed
to receive a single packet, even a very short one. This is a waste of
memory, as a RX queue has room for 256 chains, which means up to 16MB
of buffer memory for each (single-queue) vtnet device.
With the feature on, the guest can publish 2K long chains, and the
hypervisor will merge them as needed.
This change also enables the feature in the netmap backend, which
supports virtio-net offloads. We plan to add support for the
tap backend too.
Note that differently from QEMU/KVM, here we implement one-copy receive,
while QEMU uses two copies.
Ed Maste [Fri, 8 Nov 2019 14:59:41 +0000 (14:59 +0000)]
elfcopy/strip: Ensure sections have required alignment on output
Object files may specify insufficient alignment on certain sections, for
example due to a bug in NASM[1]. When we detect that case in elfcopy or
strip, emit a warning and increase the alignment to the minimum
required.
The NASM bug was fixed in 2015[2], but we might as well have this fixup
(and warning) in elfcopy in case we encounter such a file for any other
reason.
This might be reworked somewhat upstream - see ELF Tool Chain
ticket 485[3].
Ed Maste [Fri, 8 Nov 2019 14:51:09 +0000 (14:51 +0000)]
kvm: fix types for cross-debugging
As with other libkvm interfaces use maximum-sized types to support
cross-debugging (e.g. a 64-bit vmcore on a 32-bit host). See
https://lists.freebsd.org/pipermail/svn-src-all/2019-February/176051.html
for further discussion.
This is an API-breaking change, but there are few consumers of this
interface today.
Reviewed by: will
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D21945
Bjoern A. Zeeb [Fri, 8 Nov 2019 14:36:44 +0000 (14:36 +0000)]
frag6: properly handle atomic fragments according to RFCs.
RFC 8200 says:
"If the fragment is a whole datagram (that is, both the Fragment
Offset field and the M flag are zero), then it does not need
any further reassembly and should be processed as a fully
reassembled packet (i.e., updating Next Header, adjust Payload
Length, removing the Fragment header, etc.). .."
That means we should remove the fragment header and make all the adjustments
rather than just skipping over the fragment header. The difference should
be noticeable in that a properly handled atomic fragment triggering an ICMPv6
message at an upper layer (e.g. dest unreach, unreachable port) will not
include the fragment header.
Update the test cases to also test for an unfragmentable part. That is
needed so that the next header is properly updated (not just lengths).
Kyle Evans [Fri, 8 Nov 2019 14:28:39 +0000 (14:28 +0000)]
csu: Fix dynamiclib/init_test:jcr_test on !HAVE_CTORS archs
.jcr still needs a 0-entry added in crtend, even on !HAVE_CTORS archs, as
we're still getting .jcr sections added -- presumably due to the reference
in crtbegin. Without this terminal, the .jcr section (without data) overlaps
with the next section and register_classes in crtbegin will be examining the
wrong item.
PR: 241439
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D22132
Ed Maste [Fri, 8 Nov 2019 14:25:26 +0000 (14:25 +0000)]
add reference to PR for sparc64 BSD_CRTBEGIN in BROKEN_OPTIONS
We will soon remove the BSD_CRTBEGIN option (and will use the new CRT
files always) as part of the GCC 4.2.1 removal. Right now BSD_CRTBEGIN
works everywhere but sparc64; add a reference to the PR in case anyone
stumbles across this and is looking for more information.
Ed Maste [Fri, 8 Nov 2019 14:11:25 +0000 (14:11 +0000)]
makefs: avoid warning when creating FAT filesystem on existing file
Previously the mkfs_msdos function (from newfs_msdos) emitted warnings
in the case that an image size is specified and the target is not a
file, or no size is specified and the target is not a character device.
The latter warning (not a character device) doesn't make sense when this
code is used in makefs, regardless of whether an image size is specified
or not.
Ed Maste [Fri, 8 Nov 2019 14:06:48 +0000 (14:06 +0000)]
suggest xtoolchain package if binutils and GCC bootstraps are both broken
Previously we checked for only BINUTILS_BOOTSTRAP as a broken option
and suggested installing the binutils package. This was originally done
for arm64 where we used the in-tree Clang with external binutils package.
Add a case to the warning to suggest instead the full xtoolchain package
if we have no in-tree compiler either.
Humanize more columns in the vmstat(8) output and adjust widths.
The few columns that are not humanized are usually 0. This makes
the output mostly aligned.
Rick Macklem [Fri, 8 Nov 2019 06:40:17 +0000 (06:40 +0000)]
Fix the man page to correctly describe the use of the "len" argument.
The man page incorrectly described the use of the"len" argument, which
is updated to the number of bytes copied and not reduced by the number
of bytes copied.
Justin Hibbits [Fri, 8 Nov 2019 04:26:19 +0000 (04:26 +0000)]
powerpc/booke: Only handle kernel page faults in KVA range
The memory range between VM_MAXUSER_ADDRESS and VM_MIN_KERNEL_ADDRESS is
reserved for devices currently, which are always mapped in TLB1, and
therefore do not exist in the kernel page table. Any page fault in this
range is therefore automatically a fatal fault.
Justin Hibbits [Fri, 8 Nov 2019 03:45:13 +0000 (03:45 +0000)]
powerpc/booke: Make the TLB save area and mask match
Since TLB_MAXNEST is 3, the insert mask should only be 2 bits. Given that 2
bits counts to 4, and that we already have plenty of space wasted in
padding, make the nest level 4 to match the mask.
Justin Hibbits [Fri, 8 Nov 2019 03:36:19 +0000 (03:36 +0000)]
powerpc/mpc85xx: Add MSI support for Freescale PowerPC SoCs
Freescale SoCs use a set of IRQs at the high end of the OpenPIC IRQ
list, not counted in the NIRQs of the Feature reporting register. Some
SoCs include a MSI inbound window in the PCIe controller configuration
registers as well, but some don't. Currently, this only handles the
SoCs *with* the MSI window.
There are 256 MSIs per MSI bank (32 per MSI IRQ, 8 IRQs per MSI bank).
The P5020 has 3 banks, yielding up to 768 MSIs; older SoCs have only one
bank.
Kyle Evans [Fri, 8 Nov 2019 03:27:56 +0000 (03:27 +0000)]
bcm2835_dma: Mark IRQs shareable
On the RPi4, some of these IRQs are shared. Start moving toward a mode where
we accept that shared IRQs happen and simply ignore interrupts that are
seemingly for no reason.
I would like to be more verbose here, but my 30-minute assessment of the
current world order is that mapping a resource/rid to an actual IRQ number
(as found in FDT) data is not a simple matter. Determining if more than one
handler is attached to an IRQ is closer to feasible, but it's unclear which
way is the cleaner path. Beyond that, we're only really using it to be
slightly more verbose when something's going wrong, so for now just suppress
and drop a complaint-comment.
This was originally submitted (via freebsd-arm@) by Robert Crowston; the
additional verbosity was dropped by kevans@.
Submitted by: Robert Crowston <crowston@protonmail.com>
Mark Johnston [Thu, 7 Nov 2019 23:37:17 +0000 (23:37 +0000)]
iwm: Fix scheduler configuration for aux and cmd queue configuration.
- Configure the scheduler only for the management queue.
- Fix a bug when enabling the schduler: the queues are specified using a
bitmask.
- Fix style in the area.
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Mark Johnston [Thu, 7 Nov 2019 23:37:02 +0000 (23:37 +0000)]
iwm: Implement the new receive path.
This is the multiqueue receive code required for 9000-series chips.
Note that we still only configure a single RX queue for now. Multiqueue
support will require MSI-X configuration and a scheme for managing a
global pool of RX buffers.
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Mark Johnston [Thu, 7 Nov 2019 23:36:46 +0000 (23:36 +0000)]
iwm: Enable all 31 tx queues.
For now iwm only ever uses queue 0 and the management queue, but my 9560
raises a software error interrupt during initialization if this flag is
not set. iwlwifi sets it for all 7000- and 8000-series hardware, so we
might as well do it unconditionally.
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Mark Johnston [Thu, 7 Nov 2019 23:35:54 +0000 (23:35 +0000)]
iwm: Add device configuration definitions for 9000-series chips.
Match such chips using the device ID. We should really be checking the
subdevice as well, since a smaller number of 9460 and 9560 devices
actually belong to a new series of devices and require different
firmware, but that will require some extra logic in iwm_attach().
Mark Johnston [Thu, 7 Nov 2019 23:29:43 +0000 (23:29 +0000)]
iwm: Call iwm_dev_check() earlier in iwm_attach().
This ensures that the driver softc reflects device capabilities as early
as possible, for use by device initialization code that is conditional
on certain capabilities.
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Mark Johnston [Thu, 7 Nov 2019 23:27:54 +0000 (23:27 +0000)]
iwm: Fix style in the TX path.
Also ensure that the htole* macros are applied correctly when specifying
the segment length and upper address bits. No functional change
intended (unless you use iwm(4) on a big-endian machine).
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Brooks Davis [Thu, 7 Nov 2019 22:58:10 +0000 (22:58 +0000)]
libcompat: build 32-bit rtld and ldd as part of "everything"
Alter bsd.compat.mk to set MACHINE and MACHINE_ARCH when included
directly so MD paths in Makefiles work. In the process centralize
setting them in LIBCOMPATWMAKEENV.
Alter .PATH and CFLAGS settings in work when the Makefile is included.
While here only support LIB32 on supported platforms rather than always
enabling it and requiring users of MK_LIB32 to filter based
TARGET/MACHINE_ARCH.
The net effect of this change is to make Makefile.libcompat only build
compatability libraries.
Changes relative to r354449:
Correct detection of the compiler type when bsd.compat.mk is used
outside Makefile.libcompat. Previously it always matched the clang
case.
Set LDFLAGS including the linker emulation for mips where -m32 seems to
be insufficent.
Reviewed by: imp, kib (origional version in r354449)
Obtained from: CheriBSD (conceptually)
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D22251
Kyle Evans [Thu, 7 Nov 2019 21:31:15 +0000 (21:31 +0000)]
bcm_lintc: don't attach if "interrupt-controller" is missing
This is a standard required property for interrupt controllers, and present
on the bcm_lintc nodes for currently supported RPi models. For the RPi4, we
have both bcm_lintc as well as GIC-400, but only one may be active at a
time.
Don't probe bcm_lintc if it's missing the "interrupt-controller" property --
in RPi 4 DTS, the bcm_lintc node is actually missing this along with other
required interrupt properties. Presumably, if the earlier boot stages will
support switching to the legacy interrupt controller (as is suggested
possible by the documentation), the DTS will need to be updated to indicate
the proper interrupt-parent and hopefully also mark this node as an
interrupt-controller instead.
Gleb Smirnoff [Thu, 7 Nov 2019 21:28:46 +0000 (21:28 +0000)]
Since pfslowtimo() runs in the network epoch, tcp_slowtimo()
also does. This allows to simplify tcp_tw_2msl_scan() and
always require the network epoch in it.
Gleb Smirnoff [Thu, 7 Nov 2019 21:27:32 +0000 (21:27 +0000)]
Now that there is no R/W lock on PCB list the pcblist sysctls
handlers can be greatly simplified. All the previous double
cycling and complex locking was added to avoid these functions
holding global PCB locks for extended period of time, preventing
addition of new entries.
Gleb Smirnoff [Thu, 7 Nov 2019 21:23:07 +0000 (21:23 +0000)]
Now that all of the tcp_input() and all its branches are executed
in the network epoch, we can greatly simplify synchronization.
Remove all unneccesary epoch enters hidden under INP_INFO_RLOCK macro.
Remove some unneccesary assertions and convert necessary ones into the
NET_EPOCH_ASSERT macro.
Andriy Gapon [Thu, 7 Nov 2019 21:14:59 +0000 (21:14 +0000)]
IPI_TRACE is not really supported on xen
x86 stack_save_td_running() can work safely only if IPI_TRACE is a
non-maskable interrupt. But at the moment FreeBSD/Xen does not provide
support for the NMI delivery mode. So, mark the functionality as
unsupported similarly to other platforms without NMI.
Maybe there is a way to provide a Xen-specific working
stack_save_td_running(), but I couldn't figure it out.
Gleb Smirnoff [Thu, 7 Nov 2019 21:01:36 +0000 (21:01 +0000)]
Now with epoch synchronized PCB lookup tables we can greatly simplify
locking in udp_output() and udp6_output().
First, we select if we need read or write lock in PCB itself, we take
the lock and enter network epoch. Then, we proceed for the rest of
the function. In case if we need to modify PCB hash, we would take
write lock on it for a short piece of code.
We could exit the epoch before allocating an mbuf, but with this
patch we are keeping it all the way into ip_output()/ip6_output().
Today this creates an epoch recursion, since ip_output() enters epoch
itself. However, once all protocols are reviewed, ip_output() and
ip6_output() would require epoch instead of entering it.
Note: I'm not 100% sure that in udp6_output() the epoch is required.
We don't do PCB hash lookup for a bound socket. And all branches of
in6_select_src() don't require epoch, at least they lack assertions.
Today inet6 address list is protected by rmlock, although it is CKLIST.
AFAIU, the future plan is to protect it by network epoch. That would
require epoch in in6_select_src(). Anyway, in future ip6_output()
would require epoch, udp6_output() would need to enter it.
Gleb Smirnoff [Thu, 7 Nov 2019 20:49:56 +0000 (20:49 +0000)]
Since r353292 on input path we are always in network epoch, when
we lookup PCBs. Thus, do not enter epoch recursively in
in_pcblookup_hash() and in6_pcblookup_hash(). Same applies to
tcp_ctlinput() and tcp6_ctlinput().
This leaves several sysctl(9) handlers that return PCB credentials
unprotected. Add epoch enter/exit to all of them.
Gleb Smirnoff [Thu, 7 Nov 2019 20:44:34 +0000 (20:44 +0000)]
Remove unnecessary recursive epoch enter via INP_INFO_RLOCK
macro in divert_packet(). This function is called only from
pfil(9) filters, which in their place always run in the
network epoch.
Gleb Smirnoff [Thu, 7 Nov 2019 20:40:44 +0000 (20:40 +0000)]
Remove unnecessary recursive epoch enter via INP_INFO_RLOCK
macro in raw input functions for IPv4 and IPv6. They shall
always run in the network epoch.
Andrew Gallatin [Thu, 7 Nov 2019 19:54:24 +0000 (19:54 +0000)]
hwpmc : fix AMD perf counter MSR access
- amd_intr() does not account for the offset (0x200) in the counter
MSR address and ends up accessing invalid regions while reading
counter value after the 4th counter (0xC001000[8,9,..]) and
erroneously updates the counter values for counters [1-4].
- amd_intr() should only check core pmcs for interrupts since
other types of pmcs (L3,DF) cannot generate interrupts.
- fix pmc NMI's being ignored due to NMI latency on newer AMD processors
Note that this fixes a kernel panic due to GPFs accessing MSRs on
higher core count AMD cpus (seen on both Rome 7502P, and
Threadripper 2990WX 32-core CPUs)
Dimitry Andric [Thu, 7 Nov 2019 19:54:08 +0000 (19:54 +0000)]
Merge commit f596f4507 from llvm git (by Sam Elliott):
[RISCV] Add Custom Parser for Atomic Memory Operands
Summary:
GCC Accepts both (reg) and 0(reg) for atomic instruction memory
operands. These instructions do not allow for an offset in their
encoding, so in the latter case, the 0 is silently dropped.
Due to how we have structured the RISCVAsmParser, the easiest way to
add support for parsing this offset is to add a custom AsmOperand and
parser. This parser drops all the parens, and just keeps the
register.
This commit also adds a custom printer for these operands, which
matches the GCC canonical printer, printing both `(a0)` and `0(a0)`
as `(a0)`.
Merge commit f596f4507 from llvm git (by Hsiangkai Wang):
[DebugInfo] Some fields do not need relocations even relax is enabled.
In debug frame information, some fields, e.g., Length in CIE/FDE and
Offset in FDE are attributes to describe the structure of CIE/FDE.
They are not related to the relaxed code. However, these attributes
are symbol differences. So, in current design, these attributes will
be filled as zero and LLVM generates relocations for them.
We only need to generate relocations for symbols in executable
sections. So, if the symbols are not located in executable sections,
we still evaluate their values under relaxation.
Merge commit f596f4507 from llvm git (by Alex Bradbury):
[RISCV] Don't force absolute FK_Data_X fixups to relocs
The current behavior of shouldForceRelocation forces relocations for
the majority of fixups when relaxation is enabled. This makes sense
for fixups which incorporate symbols but is unnecessary for simple
data fixups where the fixup target is already resolved to an absolute
value.
Differential Revision: https://reviews.llvm.org/D63404
Patch by Edward Jones.
llvm-svn: 369257
Merge commit f596f4507 from llvm git (by Alex Bradbury):
[RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is
used for the FDE location
Follow binutils in using RISCV_32_PCREL for the FDE initial location.
As explained in the relevant binutils commit
<https://github.com/riscv/riscv-binutils-gdb/commit/a6cbf936e3dce68114d28cdf60d510a3f78a6d40>,
the ADD/SUB pair of relocations is problematic in the presence of
linker relaxation.
This patch has the same end goal as D64715 but includes test changes
and avoids adding a new global VariantKind to MCExpr.h (preferring
RISCVMCExpr VKs like the rest of the RISC-V backend).
Ed Maste [Thu, 7 Nov 2019 19:37:26 +0000 (19:37 +0000)]
arch.7: claim 12.x as the last architecture with sparc64 support
GCC 4.2.1 is being removed before FreeBSD 13, as are some other
components required by FreeBSD/sparc64. Contemporary GCC does not build
and there is currently no indication that anyone is going to address
these issues.
Kyle Evans [Thu, 7 Nov 2019 19:13:53 +0000 (19:13 +0000)]
sys/conf/files.arm64: remove some unnecessary soc_* dependencies
These files already have 'device' lines that they require; adding a
dependency on SOC_* options is an extra restriction that adds extra
verbosity when future supported Broadcom-based SOC will also feature the
same compatible device.
Users wishing to not compile these devices in should remove the 'device'
lines from their config.
Bjoern A. Zeeb [Thu, 7 Nov 2019 18:29:51 +0000 (18:29 +0000)]
netinet*: variable cleanup
In preparation for another change factor out various variable cleanups.
These mainly include:
(1) do not assign values to variables during declaration: this makes
the code more readable and does allow for better grouping of
variable declarations,
(2) do not assign values to variables before need; e.g., if a variable
is only used in the 2nd half of a function and we have multiple
return paths before that, then do not set it before it is needed, and
(3) try to avoid assigning the same value multiple times.
Merge commit b92deded8 from llvm git (by Louis Dionne):
[libc++] Move __clamp_to_integral to <cmath>, and harden against
min()/max() macros
llvm-svn: 370900
Merge commit 0ec6a4882 from llvm git (by Louis Dionne):
[libc++] Fix potential OOB in poisson_distribution
See details in the original Chromium bug report:
https://bugs.chromium.org/p/chromium/issues/detail?id=994957
Together, these fix a security issue in libc++'s implementation of
std::poisson_distribution, which can be exploited to read data which is
out of bounds.
Note there are no programs in the FreeBSD base system that use
std::poisson_distribution, so this is only a possible issue for ports
and external programs which have been built against libc++. Therefore,
I am bumping __FreeBSD_version for the benefit of our port maintainers.
Andrew Turner [Thu, 7 Nov 2019 17:34:44 +0000 (17:34 +0000)]
Add more 8 and 16 bit variants of the the atomic(9) functions on arm64.
These are direct copies of the 32 bit functions, adjusted ad needed.
While here fix atomic_fcmpset_16 to use the valid load and store exclusive
instructions.
Brooks Davis [Thu, 7 Nov 2019 17:10:33 +0000 (17:10 +0000)]
libcompat: build 32-bit rtld and ldd as part of "everything"
Alter bsd.compat.mk to set MACHINE and MACHINE_ARCH when included
directly so MD paths in Makefiles work. In the process centralize
setting them in LIBCOMPATWMAKEENV.
Alter .PATH and CFLAGS settings in work when the Makefile is included.
While here only support LIB32 on supported platforms rather than always
enabling it and requiring users of MK_LIB32 to filter based
TARGET/MACHINE_ARCH.
The net effect of this change is to make Makefile.libcompat only build
compatability libraries.
Ed Maste [Thu, 7 Nov 2019 15:51:44 +0000 (15:51 +0000)]
linux_renameat2: improve flag checks
In the cases where Linux returns an error (e.g. passing in an undefined
flag) there's no need for us to emit a message. (The target of this
message is a developer working on the linuxulatorm, not the author of
presumably broken Linux software).
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D21606
Enqueue lladdr_task to update link level address of vlan, when its parent
interface has changed.
During vlan reconfiguration without destroying interface, it is possible,
that parent interface will be changed. This usually means, that link
layer address of vlan will be different. Therefore we need to update all
associated with vlan's addresses permanent llentries - NDP for IPv6
addresses, and ARP for IPv4 addresses. This is done via lladdr_task
execution. To avoid extra work, before execution do the check, that L2
address is different.
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