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(parent: 19285e4) | patch
MF11: r320898; MFC: r320577, r320620
authormarius <marius@FreeBSD.org>
Wed, 12 Jul 2017 21:46:16 +0000 (21:46 +0000)
committermarius <marius@FreeBSD.org>
Wed, 12 Jul 2017 21:46:16 +0000 (21:46 +0000)
commit3d6ec55b9b8b214178308cd956202d62953d8b52
treea7dc6a64b84698c92c34fe0741b953fa5710456etree | snapshot
parent19285e4939bf9d407078204de4e10a66650c6afacommit | diff
MF11: r320898; MFC: r320577, r320620

Retry up to 2 ms to enable bus power as at least with some Intel
SDHCI/eMMC controllers the first attempt after a D3 to D0 transition,
i. e. when the firmware has put the devices into D3 state before,
can fail.

Approved by: re (gjb)
sys/dev/sdhci/sdhci.c diff | blob | history
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