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Pull in r339734 from upstream llvm trunk (by Eli Friedman):
authordim <dim@FreeBSD.org>
Tue, 12 Feb 2019 18:32:14 +0000 (18:32 +0000)
committerdim <dim@FreeBSD.org>
Tue, 12 Feb 2019 18:32:14 +0000 (18:32 +0000)
commitcd43497b98594cd4e441c44c459b22d254aa52c0
tree00b14bd6d1cf810b7a73a1e5b2f24c26f63a5818
parent68c8581f772f7807fbc4017e4d894d84d5a170fc
Pull in r339734 from upstream llvm trunk (by Eli Friedman):

  [ARM] Make PerformSHLSimplify add nodes to the DAG worklist correctly.

  Intentionally excluding nodes from the DAGCombine worklist is likely
  to lead to weird optimizations and infinite loops, so it's generally
  a bad idea.

  To avoid the infinite loops, fix DAGCombine to use the
  isDesirableToCommuteWithShift target hook before performing the
  transforms in question, and implement the target hook in the ARM
  backend disable the transforms in question.

  Fixes https://bugs.llvm.org/show_bug.cgi?id=38530 . (I don't have a
  reduced testcase for that bug. But we should have sufficient test
  coverage for PerformSHLSimplify given that we're not playing weird
  tricks with the worklist. I can try to bugpoint it if necessary,
  though.)

  Differential Revision: https://reviews.llvm.org/D50667

This should fix a possible hang when compiling sys/dev/nxge/if_nxge.c
(which exists now only in the stable/11 branch) for arm.
contrib/llvm/include/llvm/CodeGen/TargetLowering.h
contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.h
contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp
contrib/llvm/lib/Target/ARM/ARMISelLowering.h