1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This header file implements the operating system Host concept.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Config/config.h"
20 #include "llvm/Support/DataStream.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the platform-specific parts of this class.
27 #include "Unix/Host.inc"
30 #include "Windows/Host.inc"
35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
36 #include <mach/mach.h>
37 #include <mach/mach_host.h>
38 #include <mach/host_info.h>
39 #include <mach/machine.h>
42 //===----------------------------------------------------------------------===//
44 // Implementations of the CPU detection routines
46 //===----------------------------------------------------------------------===//
50 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
51 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
53 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
54 /// specified arguments. If we can't run cpuid on the host, return true.
55 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
56 unsigned *rECX, unsigned *rEDX) {
57 #if defined(__GNUC__) || defined(__clang__)
58 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
59 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
60 asm ("movq\t%%rbx, %%rsi\n\t"
62 "xchgq\t%%rbx, %%rsi\n\t"
69 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
70 asm ("movl\t%%ebx, %%esi\n\t"
72 "xchgl\t%%ebx, %%esi\n\t"
79 // pedantic #else returns to appease -Wunreachable-code (so we don't generate
80 // postprocessed code that looks like "return true; return false;")
84 #elif defined(_MSC_VER)
85 // The MSVC intrinsic is portable across x86 and x64.
87 __cpuid(registers, value);
98 /// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
99 /// 4 values in the specified arguments. If we can't run cpuid on the host,
101 bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
102 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
103 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
104 #if defined(__GNUC__)
105 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
106 asm ("movq\t%%rbx, %%rsi\n\t"
108 "xchgq\t%%rbx, %%rsi\n\t"
116 #elif defined(_MSC_VER)
117 // __cpuidex was added in MSVC++ 9.0 SP1
118 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 && _MSC_FULL_VER >= 150030729)
120 __cpuidex(registers, value, subleaf);
121 *rEAX = registers[0];
122 *rEBX = registers[1];
123 *rECX = registers[2];
124 *rEDX = registers[3];
132 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
133 #if defined(__GNUC__)
134 asm ("movl\t%%ebx, %%esi\n\t"
136 "xchgl\t%%ebx, %%esi\n\t"
144 #elif defined(_MSC_VER)
150 mov dword ptr [esi],eax
152 mov dword ptr [esi],ebx
154 mov dword ptr [esi],ecx
156 mov dword ptr [esi],edx
167 static bool OSHasAVXSupport() {
168 #if defined(__GNUC__)
169 // Check xgetbv; this uses a .byte sequence instead of the instruction
170 // directly because older assemblers do not include support for xgetbv and
171 // there is no easy way to conditionally compile based on the assembler used.
173 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
174 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
175 unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
177 int rEAX = 0; // Ensures we return false
179 return (rEAX & 6) == 6;
182 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
184 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
185 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
186 if (Family == 6 || Family == 0xf) {
188 // Examine extended family ID if family ID is F.
189 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
190 // Examine extended model ID if family ID is 6 or F.
191 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
195 std::string sys::getHostCPUName() {
196 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
197 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
201 DetectX86FamilyModel(EAX, Family, Model);
208 GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
210 unsigned MaxLeaf = EAX;
211 bool HasSSE3 = (ECX & 0x1);
212 bool HasSSE41 = (ECX & 0x80000);
213 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
214 // indicates that the AVX registers will be saved and restored on context
215 // switch, then we have full AVX support.
216 const unsigned AVXBits = (1 << 27) | (1 << 28);
217 bool HasAVX = ((ECX & AVXBits) == AVXBits) && OSHasAVXSupport();
218 bool HasAVX2 = HasAVX && MaxLeaf >= 0x7 &&
219 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX) &&
221 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
222 bool Em64T = (EDX >> 29) & 0x1;
224 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
230 case 0: // Intel486 DX processors
231 case 1: // Intel486 DX processors
232 case 2: // Intel486 SX processors
233 case 3: // Intel487 processors, IntelDX2 OverDrive processors,
234 // IntelDX2 processors
235 case 4: // Intel486 SL processor
236 case 5: // IntelSX2 processors
237 case 7: // Write-Back Enhanced IntelDX2 processors
238 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
239 default: return "i486";
243 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
244 // Pentium processors (60, 66)
245 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
246 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
248 case 3: // Pentium OverDrive processors for Intel486 processor-based
252 case 4: // Pentium OverDrive processor with MMX technology for Pentium
253 // processor (75, 90, 100, 120, 133), Pentium processor with
254 // MMX technology (166, 200)
255 return "pentium-mmx";
257 default: return "pentium";
261 case 1: // Pentium Pro processor
264 case 3: // Intel Pentium II OverDrive processor, Pentium II processor,
266 case 5: // Pentium II processor, model 05, Pentium II Xeon processor,
267 // model 05, and Intel Celeron processor, model 05
268 case 6: // Celeron processor, model 06
271 case 7: // Pentium III processor, model 07, and Pentium III Xeon
272 // processor, model 07
273 case 8: // Pentium III processor, model 08, Pentium III Xeon processor,
274 // model 08, and Celeron processor, model 08
275 case 10: // Pentium III Xeon processor, model 0Ah
276 case 11: // Pentium III processor, model 0Bh
279 case 9: // Intel Pentium M processor, Intel Celeron M processor model 09.
280 case 13: // Intel Pentium M processor, Intel Celeron M processor, model
281 // 0Dh. All processors are manufactured using the 90 nm process.
284 case 14: // Intel Core Duo processor, Intel Core Solo processor, model
285 // 0Eh. All processors are manufactured using the 65 nm process.
288 case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
289 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
290 // mobile processor, Intel Core 2 Extreme processor, Intel
291 // Pentium Dual-Core processor, Intel Xeon processor, model
292 // 0Fh. All processors are manufactured using the 65 nm process.
293 case 22: // Intel Celeron processor model 16h. All processors are
294 // manufactured using the 65 nm process
297 case 21: // Intel EP80579 Integrated Processor and Intel EP80579
298 // Integrated Processor with Intel QuickAssist Technology
299 return "i686"; // FIXME: ???
301 case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
302 // 17h. All processors are manufactured using the 45 nm process.
304 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
305 // Not all Penryn processors support SSE 4.1 (such as the Pentium brand)
306 return HasSSE41 ? "penryn" : "core2";
308 case 26: // Intel Core i7 processor and Intel Xeon processor. All
309 // processors are manufactured using the 45 nm process.
310 case 29: // Intel Xeon processor MP. All processors are manufactured using
311 // the 45 nm process.
312 case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
313 // As found in a Summer 2010 model iMac.
314 case 37: // Intel Core i7, laptop version.
315 case 44: // Intel Core i7 processor and Intel Xeon processor. All
316 // processors are manufactured using the 32 nm process.
317 case 46: // Nehalem EX
318 case 47: // Westmere EX
322 case 42: // Intel Core i7 processor. All processors are manufactured
323 // using the 32 nm process.
325 // Not all Sandy Bridge processors support AVX (such as the Pentium
326 // versions instead of the i7 versions).
327 return HasAVX ? "corei7-avx" : "corei7";
331 case 62: // Ivy Bridge EP
332 // Not all Ivy Bridge processors support AVX (such as the Pentium
333 // versions instead of the i7 versions).
334 return HasAVX ? "core-avx-i" : "corei7";
341 // Not all Haswell processors support AVX too (such as the Pentium
342 // versions instead of the i7 versions).
343 return HasAVX2 ? "core-avx2" : "corei7";
345 case 28: // Most 45 nm Intel Atom processors
346 case 38: // 45 nm Atom Lincroft
347 case 39: // 32 nm Atom Medfield
348 case 53: // 32 nm Atom Midview
349 case 54: // 32 nm Atom Midview
352 // Atom Silvermont codes from the Intel software optimization guide.
358 default: return (Em64T) ? "x86-64" : "i686";
362 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
363 // model 00h and manufactured using the 0.18 micron process.
364 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
365 // processor MP, and Intel Celeron processor. All processors are
366 // model 01h and manufactured using the 0.18 micron process.
367 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
368 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
369 // processor, and Mobile Intel Celeron processor. All processors
370 // are model 02h and manufactured using the 0.13 micron process.
371 return (Em64T) ? "x86-64" : "pentium4";
373 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
374 // processor. All processors are model 03h and manufactured using
375 // the 90 nm process.
376 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
377 // Pentium D processor, Intel Xeon processor, Intel Xeon
378 // processor MP, Intel Celeron D processor. All processors are
379 // model 04h and manufactured using the 90 nm process.
380 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
381 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
382 // MP, Intel Celeron D processor. All processors are model 06h
383 // and manufactured using the 65 nm process.
384 return (Em64T) ? "nocona" : "prescott";
387 return (Em64T) ? "x86-64" : "pentium4";
394 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
395 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
396 // appears to be no way to generate the wide variety of AMD-specific targets
397 // from the information returned from CPUID.
405 case 8: return "k6-2";
407 case 13: return "k6-3";
408 case 10: return "geode";
409 default: return "pentium";
413 case 4: return "athlon-tbird";
416 case 8: return "athlon-mp";
417 case 10: return "athlon-xp";
418 default: return "athlon";
424 case 1: return "opteron";
425 case 5: return "athlon-fx"; // also opteron
426 default: return "athlon64";
433 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
436 return "bdver3"; // 30h-3Fh: Steamroller
438 return "bdver2"; // 10h-1Fh: Piledriver
439 return "bdver1"; // 00h-0Fh: Bulldozer
441 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
450 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
451 std::string sys::getHostCPUName() {
452 host_basic_info_data_t hostInfo;
453 mach_msg_type_number_t infoCount;
455 infoCount = HOST_BASIC_INFO_COUNT;
456 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
459 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
461 switch(hostInfo.cpu_subtype) {
462 case CPU_SUBTYPE_POWERPC_601: return "601";
463 case CPU_SUBTYPE_POWERPC_602: return "602";
464 case CPU_SUBTYPE_POWERPC_603: return "603";
465 case CPU_SUBTYPE_POWERPC_603e: return "603e";
466 case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
467 case CPU_SUBTYPE_POWERPC_604: return "604";
468 case CPU_SUBTYPE_POWERPC_604e: return "604e";
469 case CPU_SUBTYPE_POWERPC_620: return "620";
470 case CPU_SUBTYPE_POWERPC_750: return "750";
471 case CPU_SUBTYPE_POWERPC_7400: return "7400";
472 case CPU_SUBTYPE_POWERPC_7450: return "7450";
473 case CPU_SUBTYPE_POWERPC_970: return "970";
479 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
480 std::string sys::getHostCPUName() {
481 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
482 // and so we must use an operating-system interface to determine the current
483 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
484 const char *generic = "generic";
486 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
487 // memory buffer because the 'file' has 0 size (it can be read from only
491 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
493 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
497 // The cpu line is second (after the 'processor: 0' line), so if this
498 // buffer is too small then something has changed (or is wrong).
500 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
503 const char *CPUInfoStart = buffer;
504 const char *CPUInfoEnd = buffer + CPUInfoSize;
506 const char *CIP = CPUInfoStart;
508 const char *CPUStart = 0;
511 // We need to find the first line which starts with cpu, spaces, and a colon.
512 // After the colon, there may be some additional spaces and then the cpu type.
513 while (CIP < CPUInfoEnd && CPUStart == 0) {
514 if (CIP < CPUInfoEnd && *CIP == '\n')
517 if (CIP < CPUInfoEnd && *CIP == 'c') {
519 if (CIP < CPUInfoEnd && *CIP == 'p') {
521 if (CIP < CPUInfoEnd && *CIP == 'u') {
523 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
526 if (CIP < CPUInfoEnd && *CIP == ':') {
528 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
531 if (CIP < CPUInfoEnd) {
533 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
534 *CIP != ',' && *CIP != '\n'))
536 CPULen = CIP - CPUStart;
544 while (CIP < CPUInfoEnd && *CIP != '\n')
551 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
552 .Case("604e", "604e")
554 .Case("7400", "7400")
555 .Case("7410", "7400")
556 .Case("7447", "7400")
557 .Case("7455", "7450")
559 .Case("POWER4", "970")
560 .Case("PPC970FX", "970")
561 .Case("PPC970MP", "970")
563 .Case("POWER5", "g5")
565 .Case("POWER6", "pwr6")
566 .Case("POWER7", "pwr7")
569 #elif defined(__linux__) && defined(__arm__)
570 std::string sys::getHostCPUName() {
571 // The cpuid register on arm is not accessible from user space. On Linux,
572 // it is exposed through the /proc/cpuinfo file.
573 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
574 // memory buffer because the 'file' has 0 size (it can be read from only
578 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
580 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
584 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
587 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
590 StringRef Str(buffer, CPUInfoSize);
592 SmallVector<StringRef, 32> Lines;
593 Str.split(Lines, "\n");
595 // Look for the CPU implementer line.
596 StringRef Implementer;
597 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
598 if (Lines[I].startswith("CPU implementer"))
599 Implementer = Lines[I].substr(15).ltrim("\t :");
601 if (Implementer == "0x41") // ARM Ltd.
602 // Look for the CPU part line.
603 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
604 if (Lines[I].startswith("CPU part"))
605 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
606 // values correspond to the "Part number" in the CP15/c0 register. The
607 // contents are specified in the various processor manuals.
608 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
609 .Case("0x926", "arm926ej-s")
610 .Case("0xb02", "mpcore")
611 .Case("0xb36", "arm1136j-s")
612 .Case("0xb56", "arm1156t2-s")
613 .Case("0xb76", "arm1176jz-s")
614 .Case("0xc08", "cortex-a8")
615 .Case("0xc09", "cortex-a9")
616 .Case("0xc0f", "cortex-a15")
617 .Case("0xc20", "cortex-m0")
618 .Case("0xc23", "cortex-m3")
619 .Case("0xc24", "cortex-m4")
624 #elif defined(__linux__) && defined(__s390x__)
625 std::string sys::getHostCPUName() {
626 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
627 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
628 // memory buffer because the 'file' has 0 size (it can be read from only
632 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
634 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
638 // The "processor 0:" line comes after a fair amount of other information,
639 // including a cache breakdown, but this should be plenty.
641 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
644 StringRef Str(buffer, CPUInfoSize);
645 SmallVector<StringRef, 32> Lines;
646 Str.split(Lines, "\n");
647 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
648 if (Lines[I].startswith("processor ")) {
649 size_t Pos = Lines[I].find("machine = ");
650 if (Pos != StringRef::npos) {
651 Pos += sizeof("machine = ") - 1;
653 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
667 std::string sys::getHostCPUName() {
672 #if defined(__linux__) && defined(__arm__)
673 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
675 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
677 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
681 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
684 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
687 StringRef Str(buffer, CPUInfoSize);
689 SmallVector<StringRef, 32> Lines;
690 Str.split(Lines, "\n");
692 SmallVector<StringRef, 32> CPUFeatures;
694 // Look for the CPU features.
695 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
696 if (Lines[I].startswith("Features")) {
697 Lines[I].split(CPUFeatures, " ");
701 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
702 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
703 .Case("half", "fp16")
704 .Case("neon", "neon")
705 .Case("vfpv3", "vfp3")
706 .Case("vfpv3d16", "d16")
707 .Case("vfpv4", "vfp4")
708 .Case("idiva", "hwdiv-arm")
709 .Case("idivt", "hwdiv")
712 if (LLVMFeatureStr != "")
713 Features.GetOrCreateValue(LLVMFeatureStr).setValue(true);
719 bool sys::getHostCPUFeatures(StringMap<bool> &Features){
724 std::string sys::getProcessTriple() {
725 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE));
727 if (sizeof(void *) == 8 && PT.isArch32Bit())
728 PT = PT.get64BitArchVariant();
729 if (sizeof(void *) == 4 && PT.isArch64Bit())
730 PT = PT.get32BitArchVariant();