contrib/llvm/lib/Target/PowerPC/PPCScheduleE5500.td

   1 //===-- PPCScheduleE500mc.td - e5500 Scheduling Defs -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the Freescale e5500 64-bit
  11 // Power processor.
  12 //
  13 // All information is derived from the "e5500 Core Reference Manual",
  14 // Freescale Document Number e5500RM, Rev. 1, 03/2012.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 // Relevant functional units in the Freescale e5500 core
  18 // (These are the same as for the e500mc)
  19 //
  20 //  * Decode & Dispatch
  21 //    Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
  22 //    queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
  23 // def DIS0 : FuncUnit;
  24 // def DIS1 : FuncUnit;
  25
  26 //  * Execute
  27 //    6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
  28 //    The CFX has a bypass path, allowing non-divide instructions to execute
  29 //    while a divide instruction is being executed.
  30 // def SFX0  : FuncUnit; // Simple unit 0
  31 // def SFX1  : FuncUnit; // Simple unit 1
  32 // def BU    : FuncUnit; // Branch unit
  33 // def CFX_DivBypass
  34 //           : FuncUnit; // CFX divide bypass path
  35 // def CFX_0 : FuncUnit; // CFX pipeline stage 0
  36
  37 def CFX_1 : FuncUnit; // CFX pipeline stage 1
  38
  39 // def LSU_0 : FuncUnit; // LSU pipeline
  40 // def FPU_0 : FuncUnit; // FPU pipeline
  41
  42 // def CR_Bypass : Bypass;
  43
  44 def PPCE5500Itineraries : ProcessorItineraries<
  45   [DIS0, DIS1, SFX0, SFX1, BU, CFX_DivBypass, CFX_0, CFX_1,
  46    LSU_0, FPU_0],
  47   [CR_Bypass, GPR_Bypass, FPR_Bypass], [
  48   InstrItinData<IntSimple   , [InstrStage<1, [DIS0, DIS1], 0>,
  49                                InstrStage<1, [SFX0, SFX1]>],
  50                               [5, 2, 2], // Latency = 1
  51                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  52   InstrItinData<IntGeneral  , [InstrStage<1, [DIS0, DIS1], 0>,
  53                                InstrStage<1, [SFX0, SFX1]>],
  54                               [5, 2, 2], // Latency = 1
  55                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  56   InstrItinData<IntCompare  , [InstrStage<1, [DIS0, DIS1], 0>,
  57                                InstrStage<1, [SFX0, SFX1]>],
  58                               [6, 2, 2], // Latency = 1 or 2
  59                               [CR_Bypass, GPR_Bypass, GPR_Bypass]>,
  60   InstrItinData<IntDivD     , [InstrStage<1, [DIS0, DIS1], 0>,
  61                                InstrStage<1, [CFX_0], 0>,
  62                                InstrStage<26, [CFX_DivBypass]>],
  63                               [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
  64                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  65   InstrItinData<IntDivW     , [InstrStage<1, [DIS0, DIS1], 0>,
  66                                InstrStage<1, [CFX_0], 0>,
  67                                InstrStage<16, [CFX_DivBypass]>],
  68                               [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
  69                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  70   InstrItinData<IntMFFS     , [InstrStage<1, [DIS0, DIS1], 0>,
  71                                InstrStage<1, [FPU_0]>],
  72                               [11], // Latency = 7, Repeat rate = 1
  73                               [FPR_Bypass]>,
  74   InstrItinData<IntMTFSB0   , [InstrStage<1, [DIS0, DIS1], 0>,
  75                                InstrStage<7, [FPU_0]>],
  76                               [11, 2, 2], // Latency = 7, Repeat rate = 7
  77                               [NoBypass, NoBypass, NoBypass]>,
  78   InstrItinData<IntMulHD    , [InstrStage<1, [DIS0, DIS1], 0>,
  79                                InstrStage<1, [CFX_0], 0>,
  80                                InstrStage<2, [CFX_1]>],
  81                               [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
  82                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  83   InstrItinData<IntMulHW    , [InstrStage<1, [DIS0, DIS1], 0>,
  84                                InstrStage<1, [CFX_0], 0>,
  85                                InstrStage<1, [CFX_1]>],
  86                               [8, 2, 2], // Latency = 4, Repeat rate = 1
  87                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  88   InstrItinData<IntMulHWU   , [InstrStage<1, [DIS0, DIS1], 0>,
  89                                InstrStage<1, [CFX_0], 0>,
  90                                InstrStage<1, [CFX_1]>],
  91                               [8, 2, 2], // Latency = 4, Repeat rate = 1
  92                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  93   InstrItinData<IntMulLI    , [InstrStage<1, [DIS0, DIS1], 0>,
  94                                InstrStage<1, [CFX_0], 0>,
  95                                InstrStage<2, [CFX_1]>],
  96                               [8, 2, 2], // Latency = 4 or 5, Repeat = 2
  97                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  98   InstrItinData<IntRotate   , [InstrStage<1, [DIS0, DIS1], 0>,
  99                                InstrStage<1, [SFX0, SFX1]>],
 100                               [5, 2, 2], // Latency = 1
 101                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 102   InstrItinData<IntRotateD  , [InstrStage<1, [DIS0, DIS1], 0>,
 103                                InstrStage<2, [SFX0, SFX1]>],
 104                               [6, 2, 2], // Latency = 2, Repeat rate = 2
 105                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 106   InstrItinData<IntRotateDI , [InstrStage<1, [DIS0, DIS1], 0>,
 107                                InstrStage<1, [SFX0, SFX1]>],
 108                               [5, 2, 2], // Latency = 1, Repeat rate = 1
 109                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 110   InstrItinData<IntShift    , [InstrStage<1, [DIS0, DIS1], 0>,
 111                                InstrStage<2, [SFX0, SFX1]>],
 112                               [6, 2, 2], // Latency = 2, Repeat rate = 2
 113                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 114   InstrItinData<IntTrapW    , [InstrStage<1, [DIS0, DIS1], 0>,
 115                                InstrStage<2, [SFX0]>],
 116                               [6, 2], // Latency = 2, Repeat rate = 2
 117                               [GPR_Bypass, GPR_Bypass]>,
 118   InstrItinData<BrB         , [InstrStage<1, [DIS0, DIS1], 0>,
 119                                InstrStage<1, [BU]>],
 120                               [5, 2], // Latency = 1
 121                               [NoBypass, GPR_Bypass]>,
 122   InstrItinData<BrCR        , [InstrStage<1, [DIS0, DIS1], 0>,
 123                                InstrStage<1, [BU]>],
 124                               [5, 2, 2], // Latency = 1
 125                               [CR_Bypass, CR_Bypass, CR_Bypass]>,
 126   InstrItinData<BrMCR       , [InstrStage<1, [DIS0, DIS1], 0>,
 127                                InstrStage<1, [BU]>],
 128                               [5, 2], // Latency = 1
 129                               [CR_Bypass, CR_Bypass]>,
 130   InstrItinData<BrMCRX      , [InstrStage<1, [DIS0, DIS1], 0>,
 131                                InstrStage<1, [CFX_0]>],
 132                               [5, 2, 2], // Latency = 1
 133                               [CR_Bypass, GPR_Bypass]>,
 134   InstrItinData<LdStDCBA    , [InstrStage<1, [DIS0, DIS1], 0>,
 135                                InstrStage<1, [LSU_0]>],
 136                               [7, 2], // Latency = 3, Repeat rate = 1
 137                               [GPR_Bypass, GPR_Bypass]>,
 138   InstrItinData<LdStDCBF    , [InstrStage<1, [DIS0, DIS1], 0>,
 139                                InstrStage<1, [LSU_0]>],
 140                               [7, 2], // Latency = 3, Repeat rate = 1
 141                               [GPR_Bypass, GPR_Bypass]>,
 142   InstrItinData<LdStDCBI    , [InstrStage<1, [DIS0, DIS1], 0>,
 143                                InstrStage<1, [LSU_0]>],
 144                               [7, 2], // Latency = 3, Repeat rate = 1
 145                               [GPR_Bypass, GPR_Bypass]>,
 146   InstrItinData<LdStLoad    , [InstrStage<1, [DIS0, DIS1], 0>,
 147                                InstrStage<1, [LSU_0]>],
 148                               [7, 2], // Latency = 3
 149                               [GPR_Bypass, GPR_Bypass]>,
 150   InstrItinData<LdStLoadUpd , [InstrStage<1, [DIS0, DIS1], 0>,
 151                                InstrStage<1, [SFX0, SFX1], 0>,
 152                                InstrStage<1, [LSU_0]>],
 153                               [7, 2], // Latency = 3, Repeat rate = 1
 154                               [GPR_Bypass, GPR_Bypass],
 155                               2>, // 2 micro-ops
 156   InstrItinData<LdStLD      , [InstrStage<1, [DIS0, DIS1], 0>,
 157                                InstrStage<1, [LSU_0]>],
 158                               [7, 2], // Latency = 3, Repeat rate = 1
 159                               [GPR_Bypass, GPR_Bypass]>,
 160   InstrItinData<LdStLDARX   , [InstrStage<1, [DIS0, DIS1], 0>,
 161                                InstrStage<3, [LSU_0]>],
 162                               [7, 2], // Latency = 3, Repeat rate = 3
 163                               [GPR_Bypass, GPR_Bypass]>,
 164   InstrItinData<LdStLDU     , [InstrStage<1, [DIS0, DIS1], 0>,
 165                                InstrStage<1, [SFX0, SFX1], 0>,
 166                                InstrStage<1, [LSU_0]>],
 167                               [7, 2], // Latency = 3, Repeat rate = 1
 168                               [GPR_Bypass, GPR_Bypass],
 169                               2>, // 2 micro-ops
 170   InstrItinData<LdStStore   , [InstrStage<1, [DIS0, DIS1], 0>,
 171                                InstrStage<1, [LSU_0]>],
 172                               [7, 2], // Latency = 3, Repeat rate = 1
 173                               [NoBypass, GPR_Bypass]>,
 174   InstrItinData<LdStStoreUpd, [InstrStage<1, [DIS0, DIS1], 0>,
 175                                InstrStage<1, [SFX0, SFX1], 0>,
 176                                InstrStage<1, [LSU_0]>],
 177                               [7, 2], // Latency = 3, Repeat rate = 1
 178                               [NoBypass, GPR_Bypass],
 179                               2>, // 2 micro-ops
 180   InstrItinData<LdStICBI    , [InstrStage<1, [DIS0, DIS1], 0>,
 181                                InstrStage<1, [LSU_0]>],
 182                               [7, 2], // Latency = 3, Repeat rate = 1
 183                               [NoBypass, GPR_Bypass]>,
 184   InstrItinData<LdStSTFD    , [InstrStage<1, [DIS0, DIS1], 0>,
 185                                InstrStage<1, [LSU_0]>],
 186                               [7, 2, 2], // Latency = 3, Repeat rate = 1
 187                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 188   InstrItinData<LdStSTFDU   , [InstrStage<1, [DIS0, DIS1], 0>,
 189                                InstrStage<1, [SFX0, SFX1], 0>,
 190                                InstrStage<1, [LSU_0]>],
 191                               [7, 2, 2], // Latency = 3, Repeat rate = 1
 192                               [GPR_Bypass, GPR_Bypass, GPR_Bypass],
 193                               2>, // 2 micro-ops
 194   InstrItinData<LdStLFD     , [InstrStage<1, [DIS0, DIS1], 0>,
 195                                InstrStage<1, [LSU_0]>],
 196                               [8, 2, 2], // Latency = 4, Repeat rate = 1
 197                               [FPR_Bypass, GPR_Bypass, GPR_Bypass],
 198                               2>, // 2 micro-ops
 199   InstrItinData<LdStLFDU    , [InstrStage<1, [DIS0, DIS1], 0>,
 200                                InstrStage<1, [SFX0, SFX1], 0>,
 201                                InstrStage<1, [LSU_0]>],
 202                               [8, 2, 2], // Latency = 4, Repeat rate = 1
 203                               [FPR_Bypass, GPR_Bypass, GPR_Bypass],
 204                               2>, // 2 micro-ops
 205   InstrItinData<LdStLHA     , [InstrStage<1, [DIS0, DIS1], 0>,
 206                                InstrStage<1, [LSU_0]>],
 207                               [7, 2], // Latency = 3
 208                               [GPR_Bypass, GPR_Bypass]>,
 209   InstrItinData<LdStLHAU    , [InstrStage<1, [DIS0, DIS1], 0>,
 210                                InstrStage<1, [SFX0, SFX1], 0>,
 211                                InstrStage<1, [LSU_0]>],
 212                               [7, 2], // Latency = 3, Repeat rate = 1
 213                               [GPR_Bypass, GPR_Bypass],
 214                               2>, // 2 micro-ops
 215   InstrItinData<LdStLMW     , [InstrStage<1, [DIS0, DIS1], 0>,
 216                                InstrStage<4, [LSU_0]>],
 217                               [8, 2], // Latency = r+3, Repeat rate = r+3
 218                               [NoBypass, GPR_Bypass]>,
 219   InstrItinData<LdStLWARX   , [InstrStage<1, [DIS0, DIS1], 0>,
 220                                InstrStage<3, [LSU_0]>],
 221                               [7, 2, 2], // Latency = 3, Repeat rate = 3
 222                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 223   InstrItinData<LdStSTD     , [InstrStage<1, [DIS0, DIS1], 0>,
 224                                InstrStage<1, [LSU_0]>],
 225                               [7, 2], // Latency = 3, Repeat rate = 1
 226                               [NoBypass, GPR_Bypass]>,
 227   InstrItinData<LdStSTDCX   , [InstrStage<1, [DIS0, DIS1], 0>,
 228                                InstrStage<1, [LSU_0]>],
 229                               [7, 2], // Latency = 3, Repeat rate = 1
 230                               [NoBypass, GPR_Bypass]>,
 231   InstrItinData<LdStSTDU    , [InstrStage<1, [DIS0, DIS1], 0>,
 232                                InstrStage<1, [SFX0, SFX1], 0>,
 233                                InstrStage<1, [LSU_0]>],
 234                               [7, 2], // Latency = 3, Repeat rate = 1
 235                               [NoBypass, GPR_Bypass],
 236                               2>, // 2 micro-ops
 237   InstrItinData<LdStSTWCX   , [InstrStage<1, [DIS0, DIS1], 0>,
 238                                InstrStage<1, [LSU_0]>],
 239                               [7, 2], // Latency = 3, Repeat rate = 1
 240                               [NoBypass, GPR_Bypass]>,
 241   InstrItinData<LdStSync    , [InstrStage<1, [DIS0, DIS1], 0>,
 242                                InstrStage<1, [LSU_0]>]>,
 243   InstrItinData<SprMTMSR    , [InstrStage<1, [DIS0, DIS1], 0>,
 244                                InstrStage<2, [CFX_0]>],
 245                               [6, 2], // Latency = 2, Repeat rate = 4
 246                               [GPR_Bypass, GPR_Bypass]>,
 247   InstrItinData<SprTLBSYNC  , [InstrStage<1, [DIS0, DIS1], 0>,
 248                                InstrStage<1, [LSU_0], 0>]>,
 249   InstrItinData<SprMFCR     , [InstrStage<1, [DIS0, DIS1], 0>,
 250                                InstrStage<5, [CFX_0]>],
 251                               [9, 2], // Latency = 5, Repeat rate = 5
 252                               [GPR_Bypass, CR_Bypass]>,
 253   InstrItinData<SprMFMSR    , [InstrStage<1, [DIS0, DIS1], 0>,
 254                                InstrStage<4, [SFX0]>],
 255                               [8, 2], // Latency = 4, Repeat rate = 4
 256                               [GPR_Bypass, GPR_Bypass]>,
 257   InstrItinData<SprMFSPR    , [InstrStage<1, [DIS0, DIS1], 0>,
 258                                InstrStage<1, [CFX_0]>],
 259                               [5], // Latency = 1, Repeat rate = 1
 260                               [GPR_Bypass]>,
 261   InstrItinData<SprMFTB     , [InstrStage<1, [DIS0, DIS1], 0>,
 262                                InstrStage<4, [CFX_0]>],
 263                               [8, 2], // Latency = 4, Repeat rate = 4
 264                               [NoBypass, GPR_Bypass]>,
 265   InstrItinData<SprMTSPR    , [InstrStage<1, [DIS0, DIS1], 0>,
 266                                InstrStage<1, [SFX0, SFX1]>],
 267                               [5], // Latency = 1, Repeat rate = 1
 268                               [GPR_Bypass]>,
 269   InstrItinData<FPGeneral   , [InstrStage<1, [DIS0, DIS1], 0>,
 270                                InstrStage<1, [FPU_0]>],
 271                               [11, 2, 2], // Latency = 7, Repeat rate = 1
 272                               [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 273   InstrItinData<FPAddSub    , [InstrStage<1, [DIS0, DIS1], 0>,
 274                                InstrStage<1, [FPU_0]>],
 275                               [11, 2, 2], // Latency = 7, Repeat rate = 1
 276                               [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 277   InstrItinData<FPCompare   , [InstrStage<1, [DIS0, DIS1], 0>,
 278                                InstrStage<1, [FPU_0]>],
 279                               [11, 2, 2], // Latency = 7, Repeat rate = 1
 280                               [CR_Bypass, FPR_Bypass, FPR_Bypass]>,
 281   InstrItinData<FPDivD      , [InstrStage<1, [DIS0, DIS1], 0>,
 282                                InstrStage<31, [FPU_0]>],
 283                               [39, 2, 2], // Latency = 35, Repeat rate = 31
 284                               [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 285   InstrItinData<FPDivS      , [InstrStage<1, [DIS0, DIS1], 0>,
 286                                InstrStage<16, [FPU_0]>],
 287                               [24, 2, 2], // Latency = 20, Repeat rate = 16
 288                               [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 289   InstrItinData<FPFused     , [InstrStage<1, [DIS0, DIS1], 0>,
 290                                InstrStage<1, [FPU_0]>],
 291                               [11, 2, 2, 2], // Latency = 7, Repeat rate = 1
 292                               [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 293   InstrItinData<FPRes       , [InstrStage<1, [DIS0, DIS1], 0>,
 294                                InstrStage<2, [FPU_0]>],
 295                               [12, 2], // Latency = 8, Repeat rate = 2
 296                               [FPR_Bypass, FPR_Bypass]>
 297 ]>;
 298
 299 // ===---------------------------------------------------------------------===//
 300 // e5500 machine model for scheduling and other instruction cost heuristics.
 301
 302 def PPCE5500Model : SchedMachineModel {
 303   let IssueWidth = 2;  // 2 micro-ops are dispatched per cycle.
 304   let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
 305   let LoadLatency = 6; // Optimistic load latency assuming bypass.
 306                        // This is overriden by OperandCycles if the
 307                        // Itineraries are queried instead.
 308
 309   let Itineraries = PPCE5500Itineraries;
 310 }