contrib/llvm/lib/Target/R600/R600RegisterInfo.td

   1
   2 class R600Reg <string name, bits<16> encoding> : Register<name> {
   3   let Namespace = "AMDGPU";
   4   let HWEncoding = encoding;
   5 }
   6
   7 class R600RegWithChan <string name, bits<9> sel, string chan> :
   8     Register <name> {
   9
  10   field bits<2> chan_encoding = !if(!eq(chan, "X"), 0,
  11                                 !if(!eq(chan, "Y"), 1,
  12                                 !if(!eq(chan, "Z"), 2,
  13                                 !if(!eq(chan, "W"), 3, 0))));
  14   let HWEncoding{8-0}  = sel;
  15   let HWEncoding{10-9} = chan_encoding;
  16   let Namespace = "AMDGPU";
  17 }
  18
  19 class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
  20     RegisterWithSubRegs<n, subregs> {
  21   let Namespace = "AMDGPU";
  22   let SubRegIndices = [sub0, sub1, sub2, sub3];
  23   let HWEncoding = encoding;
  24 }
  25
  26 class R600Reg_64<string n, list<Register> subregs, bits<16> encoding> :
  27     RegisterWithSubRegs<n, subregs> {
  28   let Namespace = "AMDGPU";
  29   let SubRegIndices = [sub0, sub1];
  30   let HWEncoding = encoding;
  31 }
  32
  33
  34 foreach Index = 0-127 in {
  35   foreach Chan = [ "X", "Y", "Z", "W" ] in {
  36     // 32-bit Temporary Registers
  37     def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>;
  38
  39     // Indirect addressing offset registers
  40     def Addr#Index#_#Chan : R600RegWithChan <"T("#Index#" + AR.x)."#Chan,
  41                                               Index, Chan>;
  42   }
  43   // 128-bit Temporary Registers
  44   def T#Index#_XYZW : R600Reg_128 <"T"#Index#"",
  45                                    [!cast<Register>("T"#Index#"_X"),
  46                                     !cast<Register>("T"#Index#"_Y"),
  47                                     !cast<Register>("T"#Index#"_Z"),
  48                                     !cast<Register>("T"#Index#"_W")],
  49                                    Index>;
  50
  51   def T#Index#_XY : R600Reg_64 <"T"#Index#"",
  52                                    [!cast<Register>("T"#Index#"_X"),
  53                                     !cast<Register>("T"#Index#"_Y")],
  54                                    Index>;
  55 }
  56
  57 // KCACHE_BANK0
  58 foreach Index = 159-128 in {
  59   foreach Chan = [ "X", "Y", "Z", "W" ] in {
  60     // 32-bit Temporary Registers
  61     def KC0_#Index#_#Chan : R600RegWithChan <"KC0["#!add(Index,-128)#"]."#Chan, Index, Chan>;
  62   }
  63   // 128-bit Temporary Registers
  64   def KC0_#Index#_XYZW : R600Reg_128 <"KC0["#!add(Index, -128)#"].XYZW",
  65                                  [!cast<Register>("KC0_"#Index#"_X"),
  66                                   !cast<Register>("KC0_"#Index#"_Y"),
  67                                   !cast<Register>("KC0_"#Index#"_Z"),
  68                                   !cast<Register>("KC0_"#Index#"_W")],
  69                                  Index>;
  70 }
  71
  72 // KCACHE_BANK1
  73 foreach Index = 191-160 in {
  74   foreach Chan = [ "X", "Y", "Z", "W" ] in {
  75     // 32-bit Temporary Registers
  76     def KC1_#Index#_#Chan : R600RegWithChan <"KC1["#!add(Index,-160)#"]."#Chan, Index, Chan>;
  77   }
  78   // 128-bit Temporary Registers
  79   def KC1_#Index#_XYZW : R600Reg_128 <"KC1["#!add(Index, -160)#"].XYZW",
  80                                  [!cast<Register>("KC1_"#Index#"_X"),
  81                                   !cast<Register>("KC1_"#Index#"_Y"),
  82                                   !cast<Register>("KC1_"#Index#"_Z"),
  83                                   !cast<Register>("KC1_"#Index#"_W")],
  84                                  Index>;
  85 }
  86
  87
  88 // Array Base Register holding input in FS
  89 foreach Index = 448-480 in {
  90   def ArrayBase#Index :  R600Reg<"ARRAY_BASE", Index>;
  91 }
  92
  93
  94 // Special Registers
  95
  96 def OQA : R600Reg<"OQA", 219>;
  97 def OQB : R600Reg<"OQB", 220>;
  98 def OQAP : R600Reg<"OQAP", 221>;
  99 def OQBP : R600Reg<"OQAP", 222>;
 100 def LDS_DIRECT_A : R600Reg<"LDS_DIRECT_A", 223>;
 101 def LDS_DIRECT_B : R600Reg<"LDS_DIRECT_B", 224>;
 102 def ZERO : R600Reg<"0.0", 248>;
 103 def ONE : R600Reg<"1.0", 249>;
 104 def NEG_ONE : R600Reg<"-1.0", 249>;
 105 def ONE_INT : R600Reg<"1", 250>;
 106 def HALF : R600Reg<"0.5", 252>;
 107 def NEG_HALF : R600Reg<"-0.5", 252>;
 108 def ALU_LITERAL_X : R600RegWithChan<"literal.x", 253, "X">;
 109 def ALU_LITERAL_Y : R600RegWithChan<"literal.y", 253, "Y">;
 110 def ALU_LITERAL_Z : R600RegWithChan<"literal.z", 253, "Z">;
 111 def ALU_LITERAL_W : R600RegWithChan<"literal.w", 253, "W">;
 112 def PV_X : R600RegWithChan<"PV.X", 254, "X">;
 113 def PV_Y : R600RegWithChan<"PV.Y", 254, "Y">;
 114 def PV_Z : R600RegWithChan<"PV.Z", 254, "Z">;
 115 def PV_W : R600RegWithChan<"PV.W", 254, "W">;
 116 def PS: R600Reg<"PS", 255>;
 117 def PREDICATE_BIT : R600Reg<"PredicateBit", 0>;
 118 def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>;
 119 def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;
 120 def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
 121 def AR_X : R600Reg<"AR.x", 0>;
 122
 123 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
 124                           (add (sequence "ArrayBase%u", 448, 480))>;
 125 // special registers for ALU src operands
 126 // const buffer reference, SRCx_SEL contains index
 127 def ALU_CONST : R600Reg<"CBuf", 0>;
 128 // interpolation param reference, SRCx_SEL contains index
 129 def ALU_PARAM : R600Reg<"Param", 0>;
 130
 131 let isAllocatable = 0 in {
 132
 133 // XXX: Only use the X channel, until we support wider stack widths
 134 def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X", 0, 127))>;
 135
 136 def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32,
 137   (add OQA, OQB, OQAP, OQBP, LDS_DIRECT_A, LDS_DIRECT_B)>;
 138
 139 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
 140                               (add (sequence "KC0_%u_X", 128, 159))>;
 141
 142 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
 143                               (add (sequence "KC0_%u_Y", 128, 159))>;
 144
 145 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
 146                               (add (sequence "KC0_%u_Z", 128, 159))>;
 147
 148 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
 149                               (add (sequence "KC0_%u_W", 128, 159))>;
 150
 151 def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,
 152                                    (interleave R600_KC0_X, R600_KC0_Y,
 153                                                R600_KC0_Z, R600_KC0_W)>;
 154
 155 def R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32,
 156                               (add (sequence "KC1_%u_X", 160, 191))>;
 157
 158 def R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
 159                               (add (sequence "KC1_%u_Y", 160, 191))>;
 160
 161 def R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
 162                               (add (sequence "KC1_%u_Z", 160, 191))>;
 163
 164 def R600_KC1_W : RegisterClass <"AMDGPU", [f32, i32], 32,
 165                               (add (sequence "KC1_%u_W", 160, 191))>;
 166
 167 def R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32,
 168                                    (interleave R600_KC1_X, R600_KC1_Y,
 169                                                R600_KC1_Z, R600_KC1_W)>;
 170
 171 } // End isAllocatable = 0
 172
 173 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,
 174                                    (add (sequence "T%u_X", 0, 127), AR_X)>;
 175
 176 def R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
 177                                    (add (sequence "T%u_Y", 0, 127))>;
 178
 179 def R600_TReg32_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
 180                                    (add (sequence "T%u_Z", 0, 127))>;
 181
 182 def R600_TReg32_W : RegisterClass <"AMDGPU", [f32, i32], 32,
 183                                    (add (sequence "T%u_W", 0, 127))>;
 184
 185 def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32,
 186                                    (interleave R600_TReg32_X, R600_TReg32_Y,
 187                                                R600_TReg32_Z, R600_TReg32_W)>;
 188
 189 def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
 190     R600_TReg32,
 191     R600_ArrayBase,
 192     R600_Addr,
 193     R600_KC0, R600_KC1,
 194     ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF,
 195     ALU_CONST, ALU_PARAM, OQAP
 196     )>;
 197
 198 def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
 199     PRED_SEL_OFF, PRED_SEL_ZERO, PRED_SEL_ONE)>;
 200
 201 def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add
 202     PREDICATE_BIT)>;
 203
 204 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,
 205                                 (add (sequence "T%u_XYZW", 0, 127))> {
 206   let CopyCost = -1;
 207 }
 208
 209 def R600_Reg64 : RegisterClass<"AMDGPU", [v2f32, v2i32], 64,
 210                                 (add (sequence "T%u_XY", 0, 63))>;