1 Pull in r199786 from upstream llvm trunk (by Venkatraman Govindaraju):
3 [Sparc] Add support for inline assembly constraints which specify registers by their aliases.
5 Introduced here: http://svnweb.freebsd.org/changeset/base/262261
7 Index: lib/Target/Sparc/SparcISelLowering.cpp
8 ===================================================================
9 --- lib/Target/Sparc/SparcISelLowering.cpp
10 +++ lib/Target/Sparc/SparcISelLowering.cpp
11 @@ -2992,6 +2992,26 @@ SparcTargetLowering::getRegForInlineAsmConstraint(
13 return std::make_pair(0U, &SP::IntRegsRegClass);
15 + } else if (!Constraint.empty() && Constraint.size() <= 5
16 + && Constraint[0] == '{' && *(Constraint.end()-1) == '}') {
17 + // constraint = '{r<d>}'
18 + // Remove the braces from around the name.
19 + StringRef name(Constraint.data()+1, Constraint.size()-2);
20 + // Handle register aliases:
25 + uint64_t intVal = 0;
26 + if (name.substr(0, 1).equals("r")
27 + && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
28 + const char regTypes[] = { 'g', 'o', 'l', 'i' };
29 + char regType = regTypes[intVal/8];
30 + char regIdx = '0' + (intVal % 8);
31 + char tmp[] = { '{', regType, regIdx, '}', 0 };
32 + std::string newConstraint = std::string(tmp);
33 + return TargetLowering::getRegForInlineAsmConstraint(newConstraint, VT);
37 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
38 Index: test/CodeGen/SPARC/inlineasm.ll
39 ===================================================================
40 --- test/CodeGen/SPARC/inlineasm.ll
41 +++ test/CodeGen/SPARC/inlineasm.ll
42 @@ -33,3 +33,13 @@ entry:
43 %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 10000)
47 +; CHECK-LABEL: test_constraint_reg
48 +; CHECK: ldda [%o1] 43, %g2
49 +; CHECK: ldda [%o1] 43, %g3
50 +define void @test_constraint_reg(i32 %s, i32* %ptr) {
52 + %0 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={r2},r,n"(i32* %ptr, i32 43)
53 + %1 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={g3},r,n"(i32* %ptr, i32 43)