1 Pull in r216989 from upstream llvm trunk (by Renato Golin):
3 MFV: Only emit movw on ARMv6T2+
5 Pull in r216990 from upstream llvm trunk (by Renato Golin):
7 Missing test from r216989
9 Building for the FreeBSD default target ARMv6 was emitting movw ASM on certain
10 test cases (found building qmake4/5 for ARM). Don't do that, moreover, the AS
11 in base doesn't understand this instruction for this target. One would need
12 to use --integrated-as to get this to build if desired.
14 Introduced here: http://svnweb.freebsd.org/changeset/base/271025
16 Index: lib/Target/ARM/ARMInstrInfo.td
17 ===================================================================
18 --- lib/Target/ARM/ARMInstrInfo.td
19 +++ lib/Target/ARM/ARMInstrInfo.td
21 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
22 (SBCri GPR:$src, so_imm_not:$imm)>;
23 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
24 - (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
25 + (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
26 + Requires<[IsARM, HasV6T2]>;
28 // Note: These are implemented in C++ code, because they have to generate
29 // ADD/SUBrs instructions, which use a complex pattern that a xform function
30 Index: test/CodeGen/ARM/carry.ll
31 ===================================================================
32 --- test/CodeGen/ARM/carry.ll
33 +++ test/CodeGen/ARM/carry.ll
35 -; RUN: llc < %s -march=arm | FileCheck %s
36 +; RUN: llc < %s -mtriple=armv6t2-eabi | FileCheck %s
38 define i64 @f1(i64 %a, i64 %b) {
40 Index: test/CodeGen/ARM/pr18364-movw.ll
41 ===================================================================
42 --- test/CodeGen/ARM/pr18364-movw.ll
43 +++ test/CodeGen/ARM/pr18364-movw.ll
45 +; RUN: llc < %s -mtriple=armv5te | FileCheck %s --check-prefix=V5
46 +; RUN: llc < %s -mtriple=armv6 | FileCheck %s --check-prefix=V6
47 +; RUN: llc < %s -mtriple=armv6t2 | FileCheck %s --check-prefix=V6T2
48 +; RUN: llc < %s -mtriple=armv7 | FileCheck %s --check-prefix=V7
57 + %y = alloca i64, align 8
58 + %z = alloca i64, align 8
59 + store i64 1, i64* %y, align 8
60 + store i64 11579764786944, i64* %z, align 8
61 + %0 = load i64* %y, align 8
62 + %1 = load i64* %z, align 8
63 + %sub = sub i64 %0, %1
67 +define i64 @g(i64 %a, i32 %b) #0 {
73 + %0 = mul i64 %a, 86400000
74 + %mul = add i64 %0, -210866803200000
75 + %conv = sext i32 %b to i64
76 + %add = add nsw i64 %mul, %conv