1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "lldb/Core/ArchSpec.h"
17 #include "llvm/Support/COFF.h"
18 #include "llvm/Support/ELF.h"
19 #include "llvm/Support/Host.h"
20 #include "llvm/Support/MachO.h"
21 #include "lldb/Core/RegularExpression.h"
22 #include "lldb/Host/Endian.h"
23 #include "lldb/Host/Host.h"
24 #include "lldb/Target/Platform.h"
27 using namespace lldb_private;
29 #define ARCH_SPEC_SEPARATOR_CHAR '-'
32 static bool cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match);
34 namespace lldb_private {
38 ByteOrder default_byte_order;
39 uint32_t addr_byte_size;
40 uint32_t min_opcode_byte_size;
41 uint32_t max_opcode_byte_size;
42 llvm::Triple::ArchType machine;
49 // This core information can be looked using the ArchSpec::Core as the index
50 static const CoreDefinition g_core_definitions[ArchSpec::kNumCores] =
52 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_generic , "arm" },
53 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4 , "armv4" },
54 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4t , "armv4t" },
55 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5 , "armv5" },
56 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5e , "armv5e" },
57 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5t , "armv5t" },
58 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6 , "armv6" },
59 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6m , "armv6m" },
60 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7 , "armv7" },
61 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7f , "armv7f" },
62 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7s , "armv7s" },
63 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7k , "armv7k" },
64 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7m , "armv7m" },
65 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7em , "armv7em" },
66 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_xscale , "xscale" },
67 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumb , "thumb" },
68 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv4t , "thumbv4t" },
69 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5 , "thumbv5" },
70 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5e , "thumbv5e" },
71 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6 , "thumbv6" },
72 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6m , "thumbv6m" },
73 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7 , "thumbv7" },
74 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7f , "thumbv7f" },
75 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7s , "thumbv7s" },
76 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7k , "thumbv7k" },
77 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7m , "thumbv7m" },
78 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7em , "thumbv7em" },
80 { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" },
82 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_generic , "ppc" },
83 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc601 , "ppc601" },
84 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc602 , "ppc602" },
85 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603 , "ppc603" },
86 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603e , "ppc603e" },
87 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603ev , "ppc603ev" },
88 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604 , "ppc604" },
89 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604e , "ppc604e" },
90 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc620 , "ppc620" },
91 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc750 , "ppc750" },
92 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7400 , "ppc7400" },
93 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7450 , "ppc7450" },
94 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc970 , "ppc970" },
96 { eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_generic , "ppc64" },
97 { eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_ppc970_64 , "ppc970-64" },
99 { eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc , ArchSpec::eCore_sparc_generic , "sparc" },
100 { eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, ArchSpec::eCore_sparc9_generic , "sparcv9" },
102 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i386 , "i386" },
103 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486 , "i486" },
104 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486sx , "i486sx" },
106 { eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64 , "x86_64" },
107 { eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64h , "x86_64h" },
108 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_generic, "hexagon" },
109 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4" },
110 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5" },
112 { eByteOrderLittle, 4, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach32 , "unknown-mach-32" },
113 { eByteOrderLittle, 8, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach64 , "unknown-mach-64" }
116 struct ArchDefinitionEntry
125 struct ArchDefinition
127 ArchitectureType type;
129 const ArchDefinitionEntry *entries;
135 ArchSpec::AutoComplete (const char *name, StringList &matches)
140 for (i = 0; i < ArchSpec::kNumCores; ++i)
142 if (NameMatches(g_core_definitions[i].name, eNameMatchStartsWith, name))
143 matches.AppendString (g_core_definitions[i].name);
148 for (i = 0; i < ArchSpec::kNumCores; ++i)
149 matches.AppendString (g_core_definitions[i].name);
151 return matches.GetSize();
156 #define CPU_ANY (UINT32_MAX)
158 //===----------------------------------------------------------------------===//
159 // A table that gets searched linearly for matches. This table is used to
160 // convert cpu type and subtypes to architecture names, and to convert
161 // architecture names to cpu types and subtypes. The ordering is important and
162 // allows the precedence to be set when the table is built.
163 #define SUBTYPE_MASK 0x00FFFFFFu
164 static const ArchDefinitionEntry g_macho_arch_entries[] =
166 { ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , CPU_ANY, UINT32_MAX , UINT32_MAX },
167 { ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK },
168 { ArchSpec::eCore_arm_armv4 , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
169 { ArchSpec::eCore_arm_armv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
170 { ArchSpec::eCore_arm_armv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK },
171 { ArchSpec::eCore_arm_armv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK },
172 { ArchSpec::eCore_arm_armv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
173 { ArchSpec::eCore_arm_armv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
174 { ArchSpec::eCore_arm_armv5t , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
175 { ArchSpec::eCore_arm_xscale , llvm::MachO::CPU_TYPE_ARM , 8 , UINT32_MAX , SUBTYPE_MASK },
176 { ArchSpec::eCore_arm_armv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK },
177 { ArchSpec::eCore_arm_armv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK },
178 { ArchSpec::eCore_arm_armv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK },
179 { ArchSpec::eCore_arm_armv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK },
180 { ArchSpec::eCore_arm_armv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK },
181 { ArchSpec::eCore_arm_armv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK },
182 { ArchSpec::eCore_thumb , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK },
183 { ArchSpec::eCore_thumbv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
184 { ArchSpec::eCore_thumbv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
185 { ArchSpec::eCore_thumbv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
186 { ArchSpec::eCore_thumbv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK },
187 { ArchSpec::eCore_thumbv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK },
188 { ArchSpec::eCore_thumbv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK },
189 { ArchSpec::eCore_thumbv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK },
190 { ArchSpec::eCore_thumbv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK },
191 { ArchSpec::eCore_thumbv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK },
192 { ArchSpec::eCore_thumbv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK },
193 { ArchSpec::eCore_thumbv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK },
194 { ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , CPU_ANY, UINT32_MAX , UINT32_MAX },
195 { ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , 0 , UINT32_MAX , SUBTYPE_MASK },
196 { ArchSpec::eCore_ppc_ppc601 , llvm::MachO::CPU_TYPE_POWERPC , 1 , UINT32_MAX , SUBTYPE_MASK },
197 { ArchSpec::eCore_ppc_ppc602 , llvm::MachO::CPU_TYPE_POWERPC , 2 , UINT32_MAX , SUBTYPE_MASK },
198 { ArchSpec::eCore_ppc_ppc603 , llvm::MachO::CPU_TYPE_POWERPC , 3 , UINT32_MAX , SUBTYPE_MASK },
199 { ArchSpec::eCore_ppc_ppc603e , llvm::MachO::CPU_TYPE_POWERPC , 4 , UINT32_MAX , SUBTYPE_MASK },
200 { ArchSpec::eCore_ppc_ppc603ev , llvm::MachO::CPU_TYPE_POWERPC , 5 , UINT32_MAX , SUBTYPE_MASK },
201 { ArchSpec::eCore_ppc_ppc604 , llvm::MachO::CPU_TYPE_POWERPC , 6 , UINT32_MAX , SUBTYPE_MASK },
202 { ArchSpec::eCore_ppc_ppc604e , llvm::MachO::CPU_TYPE_POWERPC , 7 , UINT32_MAX , SUBTYPE_MASK },
203 { ArchSpec::eCore_ppc_ppc620 , llvm::MachO::CPU_TYPE_POWERPC , 8 , UINT32_MAX , SUBTYPE_MASK },
204 { ArchSpec::eCore_ppc_ppc750 , llvm::MachO::CPU_TYPE_POWERPC , 9 , UINT32_MAX , SUBTYPE_MASK },
205 { ArchSpec::eCore_ppc_ppc7400 , llvm::MachO::CPU_TYPE_POWERPC , 10 , UINT32_MAX , SUBTYPE_MASK },
206 { ArchSpec::eCore_ppc_ppc7450 , llvm::MachO::CPU_TYPE_POWERPC , 11 , UINT32_MAX , SUBTYPE_MASK },
207 { ArchSpec::eCore_ppc_ppc970 , llvm::MachO::CPU_TYPE_POWERPC , 100 , UINT32_MAX , SUBTYPE_MASK },
208 { ArchSpec::eCore_ppc64_generic , llvm::MachO::CPU_TYPE_POWERPC64 , 0 , UINT32_MAX , SUBTYPE_MASK },
209 { ArchSpec::eCore_ppc64_ppc970_64 , llvm::MachO::CPU_TYPE_POWERPC64 , 100 , UINT32_MAX , SUBTYPE_MASK },
210 { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , 3 , UINT32_MAX , SUBTYPE_MASK },
211 { ArchSpec::eCore_x86_32_i486 , llvm::MachO::CPU_TYPE_I386 , 4 , UINT32_MAX , SUBTYPE_MASK },
212 { ArchSpec::eCore_x86_32_i486sx , llvm::MachO::CPU_TYPE_I386 , 0x84 , UINT32_MAX , SUBTYPE_MASK },
213 { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , CPU_ANY, UINT32_MAX , UINT32_MAX },
214 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 3 , UINT32_MAX , SUBTYPE_MASK },
215 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 4 , UINT32_MAX , SUBTYPE_MASK },
216 { ArchSpec::eCore_x86_64_x86_64h , llvm::MachO::CPU_TYPE_X86_64 , 8 , UINT32_MAX , SUBTYPE_MASK },
217 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , CPU_ANY, UINT32_MAX , UINT32_MAX },
218 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
219 { ArchSpec::eCore_uknownMach32 , 0 , 0 , 0xFF000000u, 0x00000000u },
220 { ArchSpec::eCore_uknownMach64 , llvm::MachO::CPU_ARCH_ABI64 , 0 , 0xFF000000u, 0x00000000u }
222 static const ArchDefinition g_macho_arch_def = {
224 sizeof(g_macho_arch_entries)/sizeof(g_macho_arch_entries[0]),
225 g_macho_arch_entries,
229 //===----------------------------------------------------------------------===//
230 // A table that gets searched linearly for matches. This table is used to
231 // convert cpu type and subtypes to architecture names, and to convert
232 // architecture names to cpu types and subtypes. The ordering is important and
233 // allows the precedence to be set when the table is built.
234 static const ArchDefinitionEntry g_elf_arch_entries[] =
236 { ArchSpec::eCore_sparc_generic , llvm::ELF::EM_SPARC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Sparc
237 { ArchSpec::eCore_x86_32_i386 , llvm::ELF::EM_386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80386
238 { ArchSpec::eCore_x86_32_i486 , llvm::ELF::EM_486 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 486 (deprecated)
239 { ArchSpec::eCore_ppc_generic , llvm::ELF::EM_PPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC
240 { ArchSpec::eCore_ppc64_generic , llvm::ELF::EM_PPC64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC64
241 { ArchSpec::eCore_arm_generic , llvm::ELF::EM_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
242 { ArchSpec::eCore_sparc9_generic , llvm::ELF::EM_SPARCV9, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // SPARC V9
243 { ArchSpec::eCore_x86_64_x86_64 , llvm::ELF::EM_X86_64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // AMD64
244 { ArchSpec::eCore_mips64 , llvm::ELF::EM_MIPS , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // MIPS
245 { ArchSpec::eCore_hexagon_generic , llvm::ELF::EM_HEXAGON, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // HEXAGON
248 static const ArchDefinition g_elf_arch_def = {
250 sizeof(g_elf_arch_entries)/sizeof(g_elf_arch_entries[0]),
255 static const ArchDefinitionEntry g_coff_arch_entries[] =
257 { ArchSpec::eCore_x86_32_i386 , llvm::COFF::IMAGE_FILE_MACHINE_I386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80386
258 { ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC
259 { ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC (with FPU)
260 { ArchSpec::eCore_arm_generic , llvm::COFF::IMAGE_FILE_MACHINE_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
261 { ArchSpec::eCore_arm_armv7 , llvm::COFF::IMAGE_FILE_MACHINE_ARMV7 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7
262 { ArchSpec::eCore_thumb , llvm::COFF::IMAGE_FILE_MACHINE_THUMB , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7
263 { ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // AMD64
266 static const ArchDefinition g_coff_arch_def = {
268 sizeof(g_coff_arch_entries)/sizeof(g_coff_arch_entries[0]),
273 //===----------------------------------------------------------------------===//
274 // Table of all ArchDefinitions
275 static const ArchDefinition *g_arch_definitions[] = {
281 static const size_t k_num_arch_definitions =
282 sizeof(g_arch_definitions) / sizeof(g_arch_definitions[0]);
284 //===----------------------------------------------------------------------===//
285 // Static helper functions.
288 // Get the architecture definition for a given object type.
289 static const ArchDefinition *
290 FindArchDefinition (ArchitectureType arch_type)
292 for (unsigned int i = 0; i < k_num_arch_definitions; ++i)
294 const ArchDefinition *def = g_arch_definitions[i];
295 if (def->type == arch_type)
301 // Get an architecture definition by name.
302 static const CoreDefinition *
303 FindCoreDefinition (llvm::StringRef name)
305 for (unsigned int i = 0; i < ArchSpec::kNumCores; ++i)
307 if (name.equals_lower(g_core_definitions[i].name))
308 return &g_core_definitions[i];
313 static inline const CoreDefinition *
314 FindCoreDefinition (ArchSpec::Core core)
316 if (core >= 0 && core < ArchSpec::kNumCores)
317 return &g_core_definitions[core];
321 // Get a definition entry by cpu type and subtype.
322 static const ArchDefinitionEntry *
323 FindArchDefinitionEntry (const ArchDefinition *def, uint32_t cpu, uint32_t sub)
328 const ArchDefinitionEntry *entries = def->entries;
329 for (size_t i = 0; i < def->num_entries; ++i)
331 if (entries[i].cpu == (cpu & entries[i].cpu_mask))
332 if (entries[i].sub == (sub & entries[i].sub_mask))
338 static const ArchDefinitionEntry *
339 FindArchDefinitionEntry (const ArchDefinition *def, ArchSpec::Core core)
344 const ArchDefinitionEntry *entries = def->entries;
345 for (size_t i = 0; i < def->num_entries; ++i)
347 if (entries[i].core == core)
353 //===----------------------------------------------------------------------===//
354 // Constructors and destructors.
356 ArchSpec::ArchSpec() :
358 m_core (kCore_invalid),
359 m_byte_order (eByteOrderInvalid),
364 ArchSpec::ArchSpec (const char *triple_cstr, Platform *platform) :
366 m_core (kCore_invalid),
367 m_byte_order (eByteOrderInvalid),
371 SetTriple(triple_cstr, platform);
375 ArchSpec::ArchSpec (const char *triple_cstr) :
377 m_core (kCore_invalid),
378 m_byte_order (eByteOrderInvalid),
382 SetTriple(triple_cstr);
385 ArchSpec::ArchSpec(const llvm::Triple &triple) :
387 m_core (kCore_invalid),
388 m_byte_order (eByteOrderInvalid),
394 ArchSpec::ArchSpec (ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) :
396 m_core (kCore_invalid),
397 m_byte_order (eByteOrderInvalid),
400 SetArchitecture (arch_type, cpu, subtype);
403 ArchSpec::~ArchSpec()
407 //===----------------------------------------------------------------------===//
408 // Assignment and initialization.
411 ArchSpec::operator= (const ArchSpec& rhs)
415 m_triple = rhs.m_triple;
417 m_byte_order = rhs.m_byte_order;
418 m_distribution_id = rhs.m_distribution_id;
426 m_triple = llvm::Triple();
427 m_core = kCore_invalid;
428 m_byte_order = eByteOrderInvalid;
429 m_distribution_id.Clear ();
432 //===----------------------------------------------------------------------===//
437 ArchSpec::GetArchitectureName () const
439 const CoreDefinition *core_def = FindCoreDefinition (m_core);
441 return core_def->name;
446 ArchSpec::GetMachOCPUType () const
448 const CoreDefinition *core_def = FindCoreDefinition (m_core);
451 const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core);
454 return arch_def->cpu;
457 return LLDB_INVALID_CPUTYPE;
461 ArchSpec::GetMachOCPUSubType () const
463 const CoreDefinition *core_def = FindCoreDefinition (m_core);
466 const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core);
469 return arch_def->sub;
472 return LLDB_INVALID_CPUTYPE;
475 llvm::Triple::ArchType
476 ArchSpec::GetMachine () const
478 const CoreDefinition *core_def = FindCoreDefinition (m_core);
480 return core_def->machine;
482 return llvm::Triple::UnknownArch;
486 ArchSpec::GetDistributionId () const
488 return m_distribution_id;
492 ArchSpec::SetDistributionId (const char* distribution_id)
494 m_distribution_id.SetCString (distribution_id);
498 ArchSpec::GetAddressByteSize() const
500 const CoreDefinition *core_def = FindCoreDefinition (m_core);
502 return core_def->addr_byte_size;
507 ArchSpec::GetDefaultEndian () const
509 const CoreDefinition *core_def = FindCoreDefinition (m_core);
511 return core_def->default_byte_order;
512 return eByteOrderInvalid;
516 ArchSpec::GetByteOrder () const
518 if (m_byte_order == eByteOrderInvalid)
519 return GetDefaultEndian();
523 //===----------------------------------------------------------------------===//
527 ArchSpec::SetTriple (const llvm::Triple &triple)
531 llvm::StringRef arch_name (m_triple.getArchName());
532 const CoreDefinition *core_def = FindCoreDefinition (arch_name);
535 m_core = core_def->core;
536 // Set the byte order to the default byte order for an architecture.
537 // This can be modified if needed for cases when cores handle both
538 // big and little endian
539 m_byte_order = core_def->default_byte_order;
551 ParseMachCPUDashSubtypeTriple (const char *triple_cstr, ArchSpec &arch)
553 // Accept "12-10" or "12.10" as cpu type/subtype
554 if (isdigit(triple_cstr[0]))
558 uint32_t cpu = (uint32_t)::strtoul (triple_cstr, &end, 0);
559 if (errno == 0 && cpu != 0 && end && ((*end == '-') || (*end == '.')))
562 uint32_t sub = (uint32_t)::strtoul (end + 1, &end, 0);
563 if (errno == 0 && end && ((*end == '-') || (*end == '.') || (*end == '\0')))
565 if (arch.SetArchitecture (eArchTypeMachO, cpu, sub))
569 llvm::StringRef vendor_os (end + 1);
570 size_t dash_pos = vendor_os.find('-');
571 if (dash_pos != llvm::StringRef::npos)
573 llvm::StringRef vendor_str(vendor_os.substr(0, dash_pos));
574 arch.GetTriple().setVendorName(vendor_str);
575 const size_t vendor_start_pos = dash_pos+1;
576 dash_pos = vendor_os.find('-', vendor_start_pos);
577 if (dash_pos == llvm::StringRef::npos)
579 if (vendor_start_pos < vendor_os.size())
580 arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos));
584 arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos, dash_pos - vendor_start_pos));
596 ArchSpec::SetTriple (const char *triple_cstr)
598 if (triple_cstr && triple_cstr[0])
600 if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this))
603 llvm::StringRef triple_stref (triple_cstr);
604 if (triple_stref.startswith (LLDB_ARCH_DEFAULT))
606 // Special case for the current host default architectures...
607 if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT))
608 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture32);
609 else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT))
610 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture64);
611 else if (triple_stref.equals (LLDB_ARCH_DEFAULT))
612 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture);
616 std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref));
617 triple_stref = normalized_triple_sstr;
618 SetTriple (llvm::Triple (triple_stref));
627 ArchSpec::SetTriple (const char *triple_cstr, Platform *platform)
629 if (triple_cstr && triple_cstr[0])
631 if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this))
634 llvm::StringRef triple_stref (triple_cstr);
635 if (triple_stref.startswith (LLDB_ARCH_DEFAULT))
637 // Special case for the current host default architectures...
638 if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT))
639 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture32);
640 else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT))
641 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture64);
642 else if (triple_stref.equals (LLDB_ARCH_DEFAULT))
643 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture);
647 ArchSpec raw_arch (triple_cstr);
649 std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref));
650 triple_stref = normalized_triple_sstr;
651 llvm::Triple normalized_triple (triple_stref);
653 const bool os_specified = normalized_triple.getOSName().size() > 0;
654 const bool vendor_specified = normalized_triple.getVendorName().size() > 0;
655 const bool env_specified = normalized_triple.getEnvironmentName().size() > 0;
657 // If we got an arch only, then default the vendor, os, environment
658 // to match the platform if one is supplied
659 if (!(os_specified || vendor_specified || env_specified))
663 // If we were given a platform, use the platform's system
664 // architecture. If this is not available (might not be
665 // connected) use the first supported architecture.
666 ArchSpec compatible_arch;
667 if (platform->IsCompatibleArchitecture (raw_arch, false, &compatible_arch))
669 if (compatible_arch.IsValid())
671 const llvm::Triple &compatible_triple = compatible_arch.GetTriple();
672 if (!vendor_specified)
673 normalized_triple.setVendor(compatible_triple.getVendor());
675 normalized_triple.setOS(compatible_triple.getOS());
676 if (!env_specified && compatible_triple.getEnvironmentName().size())
677 normalized_triple.setEnvironment(compatible_triple.getEnvironment());
688 // No platform specified, fall back to the host system for
689 // the default vendor, os, and environment.
690 llvm::Triple host_triple(llvm::sys::getDefaultTargetTriple());
691 if (!vendor_specified)
692 normalized_triple.setVendor(host_triple.getVendor());
693 if (!vendor_specified)
694 normalized_triple.setOS(host_triple.getOS());
695 if (!env_specified && host_triple.getEnvironmentName().size())
696 normalized_triple.setEnvironment(host_triple.getEnvironment());
699 SetTriple (normalized_triple);
708 ArchSpec::SetArchitecture (ArchitectureType arch_type, uint32_t cpu, uint32_t sub)
710 m_core = kCore_invalid;
711 bool update_triple = true;
712 const ArchDefinition *arch_def = FindArchDefinition(arch_type);
715 const ArchDefinitionEntry *arch_def_entry = FindArchDefinitionEntry (arch_def, cpu, sub);
718 const CoreDefinition *core_def = FindCoreDefinition (arch_def_entry->core);
721 m_core = core_def->core;
722 update_triple = false;
723 // Always use the architecture name because it might be more descriptive
724 // than the architecture enum ("armv7" -> llvm::Triple::arm).
725 m_triple.setArchName(llvm::StringRef(core_def->name));
726 if (arch_type == eArchTypeMachO)
728 m_triple.setVendor (llvm::Triple::Apple);
730 switch (core_def->machine)
732 case llvm::Triple::arm:
733 case llvm::Triple::thumb:
734 m_triple.setOS (llvm::Triple::IOS);
737 case llvm::Triple::x86:
738 case llvm::Triple::x86_64:
740 m_triple.setOS (llvm::Triple::MacOSX);
746 m_triple.setVendor (llvm::Triple::UnknownVendor);
747 m_triple.setOS (llvm::Triple::UnknownOS);
749 // Fall back onto setting the machine type if the arch by name failed...
750 if (m_triple.getArch () == llvm::Triple::UnknownArch)
751 m_triple.setArch (core_def->machine);
755 CoreUpdated(update_triple);
760 ArchSpec::GetMinimumOpcodeByteSize() const
762 const CoreDefinition *core_def = FindCoreDefinition (m_core);
764 return core_def->min_opcode_byte_size;
769 ArchSpec::GetMaximumOpcodeByteSize() const
771 const CoreDefinition *core_def = FindCoreDefinition (m_core);
773 return core_def->max_opcode_byte_size;
778 ArchSpec::IsExactMatch (const ArchSpec& rhs) const
780 return IsEqualTo (rhs, true);
784 ArchSpec::IsCompatibleMatch (const ArchSpec& rhs) const
786 return IsEqualTo (rhs, false);
790 ArchSpec::IsEqualTo (const ArchSpec& rhs, bool exact_match) const
792 // explicitly ignoring m_distribution_id in this method.
794 if (GetByteOrder() != rhs.GetByteOrder())
797 const ArchSpec::Core lhs_core = GetCore ();
798 const ArchSpec::Core rhs_core = rhs.GetCore ();
800 const bool core_match = cores_match (lhs_core, rhs_core, true, exact_match);
804 const llvm::Triple &lhs_triple = GetTriple();
805 const llvm::Triple &rhs_triple = rhs.GetTriple();
807 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
808 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
809 if (lhs_triple_vendor != rhs_triple_vendor)
813 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
814 const bool lhs_vendor_specified = TripleVendorWasSpecified();
815 // Both architectures had the vendor specified, so if they aren't
816 // equal then we return false
817 if (rhs_vendor_specified && lhs_vendor_specified)
821 // Only fail if both vendor types are not unknown
822 if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
823 rhs_triple_vendor != llvm::Triple::UnknownVendor)
827 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
828 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
829 if (lhs_triple_os != rhs_triple_os)
833 const bool rhs_os_specified = rhs.TripleOSWasSpecified();
834 const bool lhs_os_specified = TripleOSWasSpecified();
835 // Both architectures had the OS specified, so if they aren't
836 // equal then we return false
837 if (rhs_os_specified && lhs_os_specified)
840 // Only fail if both os types are not unknown
841 if (lhs_triple_os != llvm::Triple::UnknownOS &&
842 rhs_triple_os != llvm::Triple::UnknownOS)
846 const llvm::Triple::EnvironmentType lhs_triple_env = lhs_triple.getEnvironment();
847 const llvm::Triple::EnvironmentType rhs_triple_env = rhs_triple.getEnvironment();
849 if (lhs_triple_env != rhs_triple_env)
851 // Only fail if both environment types are not unknown
852 if (lhs_triple_env != llvm::Triple::UnknownEnvironment &&
853 rhs_triple_env != llvm::Triple::UnknownEnvironment)
861 //===----------------------------------------------------------------------===//
865 ArchSpec::CoreUpdated (bool update_triple)
867 const CoreDefinition *core_def = FindCoreDefinition (m_core);
871 m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
872 m_byte_order = core_def->default_byte_order;
877 m_triple = llvm::Triple();
878 m_byte_order = eByteOrderInvalid;
882 //===----------------------------------------------------------------------===//
886 cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match)
893 case ArchSpec::kCore_any:
896 case ArchSpec::kCore_arm_any:
897 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
899 if (core2 >= ArchSpec::kCore_thumb_first && core2 <= ArchSpec::kCore_thumb_last)
901 if (core2 == ArchSpec::kCore_arm_any)
905 case ArchSpec::kCore_x86_32_any:
906 if ((core2 >= ArchSpec::kCore_x86_32_first && core2 <= ArchSpec::kCore_x86_32_last) || (core2 == ArchSpec::kCore_x86_32_any))
910 case ArchSpec::kCore_ppc_any:
911 if ((core2 >= ArchSpec::kCore_ppc_first && core2 <= ArchSpec::kCore_ppc_last) || (core2 == ArchSpec::kCore_ppc_any))
915 case ArchSpec::kCore_ppc64_any:
916 if ((core2 >= ArchSpec::kCore_ppc64_first && core2 <= ArchSpec::kCore_ppc64_last) || (core2 == ArchSpec::kCore_ppc64_any))
920 case ArchSpec::eCore_arm_armv6m:
921 if (!enforce_exact_match)
924 if (core2 == ArchSpec::eCore_arm_armv7)
928 case ArchSpec::kCore_hexagon_any:
929 if ((core2 >= ArchSpec::kCore_hexagon_first && core2 <= ArchSpec::kCore_hexagon_last) || (core2 == ArchSpec::kCore_hexagon_any))
933 case ArchSpec::eCore_arm_armv7m:
934 case ArchSpec::eCore_arm_armv7em:
935 case ArchSpec::eCore_arm_armv7f:
936 case ArchSpec::eCore_arm_armv7k:
937 case ArchSpec::eCore_arm_armv7s:
938 if (!enforce_exact_match)
941 if (core2 == ArchSpec::eCore_arm_armv7)
950 return cores_match (core2, core1, false, enforce_exact_match);
955 lldb_private::operator<(const ArchSpec& lhs, const ArchSpec& rhs)
957 const ArchSpec::Core lhs_core = lhs.GetCore ();
958 const ArchSpec::Core rhs_core = rhs.GetCore ();
959 return lhs_core < rhs_core;