1 //===-- EmulateInstructionARM.cpp -------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 #include "EmulateInstructionARM.h"
13 #include "EmulationStateARM.h"
14 #include "lldb/Core/ArchSpec.h"
15 #include "lldb/Core/Address.h"
16 #include "lldb/Core/ConstString.h"
17 #include "lldb/Core/PluginManager.h"
18 #include "lldb/Core/Stream.h"
19 #include "lldb/Interpreter/OptionValueArray.h"
20 #include "lldb/Interpreter/OptionValueDictionary.h"
21 #include "lldb/Symbol/UnwindPlan.h"
23 #include "Plugins/Process/Utility/ARMDefines.h"
24 #include "Plugins/Process/Utility/ARMUtils.h"
25 #include "Utility/ARM_DWARF_Registers.h"
27 #include "llvm/Support/MathExtras.h" // for SignExtend32 template function
28 // and countTrailingZeros function
31 using namespace lldb_private;
33 // Convenient macro definitions.
34 #define APSR_C Bit32(m_opcode_cpsr, CPSR_C_POS)
35 #define APSR_V Bit32(m_opcode_cpsr, CPSR_V_POS)
37 #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC)
39 //----------------------------------------------------------------------
41 // ITSession implementation
43 //----------------------------------------------------------------------
46 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
48 CountITSize (uint32_t ITMask) {
49 // First count the trailing zeros of the IT mask.
50 uint32_t TZ = llvm::countTrailingZeros(ITMask);
53 #ifdef LLDB_CONFIGURATION_DEBUG
54 printf("Encoding error: IT Mask '0000'\n");
61 // Init ITState. Note that at least one bit is always 1 in mask.
62 bool ITSession::InitIT(uint32_t bits7_0)
64 ITCounter = CountITSize(Bits32(bits7_0, 3, 0));
69 unsigned short FirstCond = Bits32(bits7_0, 7, 4);
72 #ifdef LLDB_CONFIGURATION_DEBUG
73 printf("Encoding error: IT FirstCond '1111'\n");
77 if (FirstCond == 0xE && ITCounter != 1)
79 #ifdef LLDB_CONFIGURATION_DEBUG
80 printf("Encoding error: IT FirstCond '1110' && Mask != '1000'\n");
89 // Update ITState if necessary.
90 void ITSession::ITAdvance()
98 unsigned short NewITState4_0 = Bits32(ITState, 4, 0) << 1;
99 SetBits32(ITState, 4, 0, NewITState4_0);
103 // Return true if we're inside an IT Block.
104 bool ITSession::InITBlock()
106 return ITCounter != 0;
109 // Return true if we're the last instruction inside an IT Block.
110 bool ITSession::LastInITBlock()
112 return ITCounter == 1;
115 // Get condition bits for the current thumb instruction.
116 uint32_t ITSession::GetCond()
119 return Bits32(ITState, 7, 4);
124 // ARM constants used during decoding
126 #define LDM_REGLIST 1
130 #define PC_REGLIST_BIT 0x8000
132 #define ARMv4 (1u << 0)
133 #define ARMv4T (1u << 1)
134 #define ARMv5T (1u << 2)
135 #define ARMv5TE (1u << 3)
136 #define ARMv5TEJ (1u << 4)
137 #define ARMv6 (1u << 5)
138 #define ARMv6K (1u << 6)
139 #define ARMv6T2 (1u << 7)
140 #define ARMv7 (1u << 8)
141 #define ARMv7S (1u << 9)
142 #define ARMv8 (1u << 10)
143 #define ARMvAll (0xffffffffu)
145 #define ARMV4T_ABOVE (ARMv4T|ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
146 #define ARMV5_ABOVE (ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
147 #define ARMV5TE_ABOVE (ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
148 #define ARMV5J_ABOVE (ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
149 #define ARMV6_ABOVE (ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
150 #define ARMV6T2_ABOVE (ARMv6T2|ARMv7|ARMv7S|ARMv8)
151 #define ARMV7_ABOVE (ARMv7|ARMv7S|ARMv8)
154 #define VFPv1 (1u << 1)
155 #define VFPv2 (1u << 2)
156 #define VFPv3 (1u << 3)
157 #define AdvancedSIMD (1u << 4)
159 #define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD)
160 #define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD)
161 #define VFPv2v3 (VFPv2 | VFPv3)
163 //----------------------------------------------------------------------
165 // EmulateInstructionARM implementation
167 //----------------------------------------------------------------------
170 EmulateInstructionARM::Initialize ()
172 PluginManager::RegisterPlugin (GetPluginNameStatic (),
173 GetPluginDescriptionStatic (),
178 EmulateInstructionARM::Terminate ()
180 PluginManager::UnregisterPlugin (CreateInstance);
184 EmulateInstructionARM::GetPluginNameStatic ()
186 static ConstString g_name("arm");
191 EmulateInstructionARM::GetPluginDescriptionStatic ()
193 return "Emulate instructions for the ARM architecture.";
197 EmulateInstructionARM::CreateInstance (const ArchSpec &arch, InstructionType inst_type)
199 if (EmulateInstructionARM::SupportsEmulatingInstructionsOfTypeStatic(inst_type))
201 if (arch.GetTriple().getArch() == llvm::Triple::arm)
203 std::unique_ptr<EmulateInstructionARM> emulate_insn_ap (new EmulateInstructionARM (arch));
205 if (emulate_insn_ap.get())
206 return emulate_insn_ap.release();
208 else if (arch.GetTriple().getArch() == llvm::Triple::thumb)
210 std::unique_ptr<EmulateInstructionARM> emulate_insn_ap (new EmulateInstructionARM (arch));
212 if (emulate_insn_ap.get())
213 return emulate_insn_ap.release();
221 EmulateInstructionARM::SetTargetTriple (const ArchSpec &arch)
223 if (arch.GetTriple().getArch () == llvm::Triple::arm)
225 else if (arch.GetTriple().getArch () == llvm::Triple::thumb)
231 // Write "bits (32) UNKNOWN" to memory address "address". Helper function for many ARM instructions.
233 EmulateInstructionARM::WriteBits32UnknownToMemory (addr_t address)
235 EmulateInstruction::Context context;
236 context.type = EmulateInstruction::eContextWriteMemoryRandomBits;
237 context.SetNoArgs ();
239 uint32_t random_data = rand ();
240 const uint32_t addr_byte_size = GetAddressByteSize();
242 if (!MemAWrite (context, address, random_data, addr_byte_size))
248 // Write "bits (32) UNKNOWN" to register n. Helper function for many ARM instructions.
250 EmulateInstructionARM::WriteBits32Unknown (int n)
252 EmulateInstruction::Context context;
253 context.type = EmulateInstruction::eContextWriteRegisterRandomBits;
254 context.SetNoArgs ();
257 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
262 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
269 EmulateInstructionARM::GetRegisterInfo (uint32_t reg_kind, uint32_t reg_num, RegisterInfo ®_info)
271 if (reg_kind == eRegisterKindGeneric)
275 case LLDB_REGNUM_GENERIC_PC: reg_kind = eRegisterKindDWARF; reg_num = dwarf_pc; break;
276 case LLDB_REGNUM_GENERIC_SP: reg_kind = eRegisterKindDWARF; reg_num = dwarf_sp; break;
277 case LLDB_REGNUM_GENERIC_FP: reg_kind = eRegisterKindDWARF; reg_num = dwarf_r7; break;
278 case LLDB_REGNUM_GENERIC_RA: reg_kind = eRegisterKindDWARF; reg_num = dwarf_lr; break;
279 case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = dwarf_cpsr; break;
280 default: return false;
284 if (reg_kind == eRegisterKindDWARF)
285 return GetARMDWARFRegisterInfo(reg_num, reg_info);
290 EmulateInstructionARM::GetFramePointerRegisterNumber () const
292 bool is_apple = false;
293 if (m_arch.GetTriple().getVendor() == llvm::Triple::Apple)
295 switch (m_arch.GetTriple().getOS())
297 case llvm::Triple::Darwin:
298 case llvm::Triple::MacOSX:
299 case llvm::Triple::IOS:
306 /* On Apple iOS et al, the frame pointer register is always r7.
307 * Typically on other ARM systems, thumb code uses r7; arm code uses r11.
310 uint32_t fp_regnum = 11;
315 if (m_opcode_mode == eModeThumb)
322 EmulateInstructionARM::GetFramePointerDWARFRegisterNumber () const
324 bool is_apple = false;
325 if (m_arch.GetTriple().getVendor() == llvm::Triple::Apple)
327 switch (m_arch.GetTriple().getOS())
329 case llvm::Triple::Darwin:
330 case llvm::Triple::MacOSX:
331 case llvm::Triple::IOS:
338 /* On Apple iOS et al, the frame pointer register is always r7.
339 * Typically on other ARM systems, thumb code uses r7; arm code uses r11.
342 uint32_t fp_regnum = dwarf_r11;
345 fp_regnum = dwarf_r7;
347 if (m_opcode_mode == eModeThumb)
348 fp_regnum = dwarf_r7;
353 // Push Multiple Registers stores multiple registers to the stack, storing to
354 // consecutive memory locations ending just below the address in SP, and updates
355 // SP to point to the start of the stored data.
357 EmulateInstructionARM::EmulatePUSH (const uint32_t opcode, const ARMEncoding encoding)
360 // ARM pseudo code...
361 if (ConditionPassed())
363 EncodingSpecificOperations();
364 NullCheckIfThumbEE(13);
365 address = SP - 4*BitCount(registers);
369 if (registers<i> == '1')
371 if i == 13 && i != LowestSetBit(registers) // Only possible for encoding A1
372 MemA[address,4] = bits(32) UNKNOWN;
374 MemA[address,4] = R[i];
375 address = address + 4;
379 if (registers<15> == '1') // Only possible for encoding A1 or A2
380 MemA[address,4] = PCStoreValue();
382 SP = SP - 4*BitCount(registers);
386 bool conditional = false;
387 bool success = false;
388 if (ConditionPassed(opcode, &conditional))
390 const uint32_t addr_byte_size = GetAddressByteSize();
391 const addr_t sp = ReadCoreReg (SP_REG, &success);
394 uint32_t registers = 0;
395 uint32_t Rt; // the source register
398 registers = Bits32(opcode, 7, 0);
399 // The M bit represents LR.
400 if (Bit32(opcode, 8))
401 registers |= (1u << 14);
402 // if BitCount(registers) < 1 then UNPREDICTABLE;
403 if (BitCount(registers) < 1)
407 // Ignore bits 15 & 13.
408 registers = Bits32(opcode, 15, 0) & ~0xa000;
409 // if BitCount(registers) < 2 then UNPREDICTABLE;
410 if (BitCount(registers) < 2)
414 Rt = Bits32(opcode, 15, 12);
415 // if BadReg(t) then UNPREDICTABLE;
418 registers = (1u << Rt);
421 registers = Bits32(opcode, 15, 0);
422 // Instead of return false, let's handle the following case as well,
423 // which amounts to pushing one reg onto the full descending stacks.
424 // if BitCount(register_list) < 2 then SEE STMDB / STMFD;
427 Rt = Bits32(opcode, 15, 12);
428 // if t == 13 then UNPREDICTABLE;
431 registers = (1u << Rt);
436 addr_t sp_offset = addr_byte_size * BitCount (registers);
437 addr_t addr = sp - sp_offset;
440 EmulateInstruction::Context context;
442 context.type = EmulateInstruction::eContextRegisterStore;
444 context.type = EmulateInstruction::eContextPushRegisterOnStack;
445 RegisterInfo reg_info;
447 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
450 if (BitIsSet (registers, i))
452 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, reg_info);
453 context.SetRegisterToRegisterPlusOffset (reg_info, sp_reg, addr - sp);
454 uint32_t reg_value = ReadCoreReg(i, &success);
457 if (!MemAWrite (context, addr, reg_value, addr_byte_size))
459 addr += addr_byte_size;
463 if (BitIsSet (registers, 15))
465 GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, reg_info);
466 context.SetRegisterToRegisterPlusOffset (reg_info, sp_reg, addr - sp);
467 const uint32_t pc = ReadCoreReg(PC_REG, &success);
470 if (!MemAWrite (context, addr, pc, addr_byte_size))
474 context.type = EmulateInstruction::eContextAdjustStackPointer;
475 context.SetImmediateSigned (-sp_offset);
477 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset))
483 // Pop Multiple Registers loads multiple registers from the stack, loading from
484 // consecutive memory locations staring at the address in SP, and updates
485 // SP to point just above the loaded data.
487 EmulateInstructionARM::EmulatePOP (const uint32_t opcode, const ARMEncoding encoding)
490 // ARM pseudo code...
491 if (ConditionPassed())
493 EncodingSpecificOperations(); NullCheckIfThumbEE(13);
496 if registers<i> == '1' then
497 R[i] = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4;
498 if registers<15> == '1' then
499 if UnalignedAllowed then
500 LoadWritePC(MemU[address,4]);
502 LoadWritePC(MemA[address,4]);
503 if registers<13> == '0' then SP = SP + 4*BitCount(registers);
504 if registers<13> == '1' then SP = bits(32) UNKNOWN;
508 bool success = false;
510 bool conditional = false;
511 if (ConditionPassed(opcode, &conditional))
513 const uint32_t addr_byte_size = GetAddressByteSize();
514 const addr_t sp = ReadCoreReg (SP_REG, &success);
517 uint32_t registers = 0;
518 uint32_t Rt; // the destination register
521 registers = Bits32(opcode, 7, 0);
522 // The P bit represents PC.
523 if (Bit32(opcode, 8))
524 registers |= (1u << 15);
525 // if BitCount(registers) < 1 then UNPREDICTABLE;
526 if (BitCount(registers) < 1)
531 registers = Bits32(opcode, 15, 0) & ~0x2000;
532 // if BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
533 if (BitCount(registers) < 2 || (Bit32(opcode, 15) && Bit32(opcode, 14)))
535 // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
536 if (BitIsSet(registers, 15) && InITBlock() && !LastInITBlock())
540 Rt = Bits32(opcode, 15, 12);
541 // if t == 13 || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE;
544 if (Rt == 15 && InITBlock() && !LastInITBlock())
546 registers = (1u << Rt);
549 registers = Bits32(opcode, 15, 0);
550 // Instead of return false, let's handle the following case as well,
551 // which amounts to popping one reg from the full descending stacks.
552 // if BitCount(register_list) < 2 then SEE LDM / LDMIA / LDMFD;
554 // if registers<13> == '1' && ArchVersion() >= 7 then UNPREDICTABLE;
555 if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7)
559 Rt = Bits32(opcode, 15, 12);
560 // if t == 13 then UNPREDICTABLE;
563 registers = (1u << Rt);
568 addr_t sp_offset = addr_byte_size * BitCount (registers);
572 EmulateInstruction::Context context;
574 context.type = EmulateInstruction::eContextRegisterLoad;
576 context.type = EmulateInstruction::eContextPopRegisterOffStack;
579 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
583 if (BitIsSet (registers, i))
585 context.SetRegisterPlusOffset (sp_reg, addr - sp);
586 data = MemARead(context, addr, 4, 0, &success);
589 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i, data))
591 addr += addr_byte_size;
595 if (BitIsSet (registers, 15))
597 context.SetRegisterPlusOffset (sp_reg, addr - sp);
598 data = MemARead(context, addr, 4, 0, &success);
601 // In ARMv5T and above, this is an interworking branch.
602 if (!LoadWritePC(context, data))
604 //addr += addr_byte_size;
607 context.type = EmulateInstruction::eContextAdjustStackPointer;
608 context.SetImmediateSigned (sp_offset);
610 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset))
616 // Set r7 or ip to point to saved value residing within the stack.
617 // ADD (SP plus immediate)
619 EmulateInstructionARM::EmulateADDRdSPImm (const uint32_t opcode, const ARMEncoding encoding)
622 // ARM pseudo code...
623 if (ConditionPassed())
625 EncodingSpecificOperations();
626 (result, carry, overflow) = AddWithCarry(SP, imm32, '0');
628 ALUWritePC(result); // setflags is always FALSE here
633 APSR.Z = IsZeroBit(result);
639 bool success = false;
641 if (ConditionPassed(opcode))
643 const addr_t sp = ReadCoreReg (SP_REG, &success);
646 uint32_t Rd; // the destination register
651 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32)
654 Rd = Bits32(opcode, 15, 12);
655 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
660 addr_t sp_offset = imm32;
661 addr_t addr = sp + sp_offset; // a pointer to the stack area
663 EmulateInstruction::Context context;
664 context.type = eContextSetFramePointer;
666 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
667 context.SetRegisterPlusOffset (sp_reg, sp_offset);
669 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, addr))
675 // Set r7 or ip to the current stack pointer.
678 EmulateInstructionARM::EmulateMOVRdSP (const uint32_t opcode, const ARMEncoding encoding)
681 // ARM pseudo code...
682 if (ConditionPassed())
684 EncodingSpecificOperations();
687 ALUWritePC(result); // setflags is always FALSE here
692 APSR.Z = IsZeroBit(result);
698 bool success = false;
700 if (ConditionPassed(opcode))
702 const addr_t sp = ReadCoreReg (SP_REG, &success);
705 uint32_t Rd; // the destination register
717 EmulateInstruction::Context context;
718 if (Rd == GetFramePointerRegisterNumber())
719 context.type = EmulateInstruction::eContextSetFramePointer;
721 context.type = EmulateInstruction::eContextRegisterPlusOffset;
723 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
724 context.SetRegisterPlusOffset (sp_reg, 0);
726 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, sp))
732 // Move from high register (r8-r15) to low register (r0-r7).
735 EmulateInstructionARM::EmulateMOVLowHigh (const uint32_t opcode, const ARMEncoding encoding)
737 return EmulateMOVRdRm (opcode, encoding);
740 // Move from register to register.
743 EmulateInstructionARM::EmulateMOVRdRm (const uint32_t opcode, const ARMEncoding encoding)
746 // ARM pseudo code...
747 if (ConditionPassed())
749 EncodingSpecificOperations();
752 ALUWritePC(result); // setflags is always FALSE here
757 APSR.Z = IsZeroBit(result);
763 bool success = false;
765 if (ConditionPassed(opcode))
767 uint32_t Rm; // the source register
768 uint32_t Rd; // the destination register
772 Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
773 Rm = Bits32(opcode, 6, 3);
775 if (Rd == 15 && InITBlock() && !LastInITBlock())
779 Rd = Bits32(opcode, 2, 0);
780 Rm = Bits32(opcode, 5, 3);
786 Rd = Bits32(opcode, 11, 8);
787 Rm = Bits32(opcode, 3, 0);
788 setflags = BitIsSet(opcode, 20);
789 // if setflags && (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
790 if (setflags && (BadReg(Rd) || BadReg(Rm)))
792 // if !setflags && (d == 15 || m == 15 || (d == 13 && m == 13)) then UNPREDICTABLE;
793 if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13)))
797 Rd = Bits32(opcode, 15, 12);
798 Rm = Bits32(opcode, 3, 0);
799 setflags = BitIsSet(opcode, 20);
801 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
802 if (Rd == 15 && setflags)
803 return EmulateSUBSPcLrEtc (opcode, encoding);
808 uint32_t result = ReadCoreReg(Rm, &success);
812 // The context specifies that Rm is to be moved into Rd.
813 EmulateInstruction::Context context;
814 context.type = EmulateInstruction::eContextRegisterLoad;
815 RegisterInfo dwarf_reg;
816 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
817 context.SetRegister (dwarf_reg);
819 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags))
825 // Move (immediate) writes an immediate value to the destination register. It
826 // can optionally update the condition flags based on the value.
829 EmulateInstructionARM::EmulateMOVRdImm (const uint32_t opcode, const ARMEncoding encoding)
832 // ARM pseudo code...
833 if (ConditionPassed())
835 EncodingSpecificOperations();
837 if d == 15 then // Can only occur for ARM encoding
838 ALUWritePC(result); // setflags is always FALSE here
843 APSR.Z = IsZeroBit(result);
849 if (ConditionPassed(opcode))
851 uint32_t Rd; // the destination register
852 uint32_t imm32; // the immediate value to be written to Rd
853 uint32_t carry = 0; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C.
854 // for setflags == false, this value is a don't care
855 // initialized to 0 to silence the static analyzer
859 Rd = Bits32(opcode, 10, 8);
860 setflags = !InITBlock();
861 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
867 Rd = Bits32(opcode, 11, 8);
868 setflags = BitIsSet(opcode, 20);
869 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
877 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:i:imm3:imm8, 32);
878 Rd = Bits32 (opcode, 11, 8);
880 uint32_t imm4 = Bits32 (opcode, 19, 16);
881 uint32_t imm3 = Bits32 (opcode, 14, 12);
882 uint32_t i = Bit32 (opcode, 26);
883 uint32_t imm8 = Bits32 (opcode, 7, 0);
884 imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8;
886 // if BadReg(d) then UNPREDICTABLE;
893 // d = UInt(Rd); setflags = (S == Ô1Õ); (imm32, carry) = ARMExpandImm_C(imm12, APSR.C);
894 Rd = Bits32 (opcode, 15, 12);
895 setflags = BitIsSet (opcode, 20);
896 imm32 = ARMExpandImm_C (opcode, APSR_C, carry);
898 // if Rd == Ô1111Õ && S == Ô1Õ then SEE SUBS PC, LR and related instructions;
899 if ((Rd == 15) && setflags)
900 return EmulateSUBSPcLrEtc (opcode, encoding);
906 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:imm12, 32);
907 Rd = Bits32 (opcode, 15, 12);
909 uint32_t imm4 = Bits32 (opcode, 19, 16);
910 uint32_t imm12 = Bits32 (opcode, 11, 0);
911 imm32 = (imm4 << 12) | imm12;
913 // if d == 15 then UNPREDICTABLE;
922 uint32_t result = imm32;
924 // The context specifies that an immediate is to be moved into Rd.
925 EmulateInstruction::Context context;
926 context.type = EmulateInstruction::eContextImmediate;
927 context.SetNoArgs ();
929 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
935 // MUL multiplies two register values. The least significant 32 bits of the result are written to the destination
936 // register. These 32 bits do not depend on whether the source register values are considered to be signed values or
939 // Optionally, it can update the condition flags based on the result. In the Thumb instruction set, this option is
940 // limited to only a few forms of the instruction.
942 EmulateInstructionARM::EmulateMUL (const uint32_t opcode, const ARMEncoding encoding)
945 if ConditionPassed() then
946 EncodingSpecificOperations();
947 operand1 = SInt(R[n]); // operand1 = UInt(R[n]) produces the same final results
948 operand2 = SInt(R[m]); // operand2 = UInt(R[m]) produces the same final results
949 result = operand1 * operand2;
953 APSR.Z = IsZeroBit(result);
954 if ArchVersion() == 4 then
955 APSR.C = bit UNKNOWN;
956 // else APSR.C unchanged
957 // APSR.V always unchanged
960 if (ConditionPassed(opcode))
967 // EncodingSpecificOperations();
971 // d = UInt(Rdm); n = UInt(Rn); m = UInt(Rdm); setflags = !InITBlock();
972 d = Bits32 (opcode, 2, 0);
973 n = Bits32 (opcode, 5, 3);
974 m = Bits32 (opcode, 2, 0);
975 setflags = !InITBlock();
977 // if ArchVersion() < 6 && d == n then UNPREDICTABLE;
978 if ((ArchVersion() < ARMv6) && (d == n))
984 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
985 d = Bits32 (opcode, 11, 8);
986 n = Bits32 (opcode, 19, 16);
987 m = Bits32 (opcode, 3, 0);
990 // if BadReg(d) || BadReg(n) || BadReg(m) then UNPREDICTABLE;
991 if (BadReg (d) || BadReg (n) || BadReg (m))
997 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
998 d = Bits32 (opcode, 19, 16);
999 n = Bits32 (opcode, 3, 0);
1000 m = Bits32 (opcode, 11, 8);
1001 setflags = BitIsSet (opcode, 20);
1003 // if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
1004 if ((d == 15) || (n == 15) || (m == 15))
1007 // if ArchVersion() < 6 && d == n then UNPREDICTABLE;
1008 if ((ArchVersion() < ARMv6) && (d == n))
1017 bool success = false;
1019 // operand1 = SInt(R[n]); // operand1 = UInt(R[n]) produces the same final results
1020 uint64_t operand1 = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
1024 // operand2 = SInt(R[m]); // operand2 = UInt(R[m]) produces the same final results
1025 uint64_t operand2 = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
1029 // result = operand1 * operand2;
1030 uint64_t result = operand1 * operand2;
1032 // R[d] = result<31:0>;
1033 RegisterInfo op1_reg;
1034 RegisterInfo op2_reg;
1035 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, op1_reg);
1036 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, op2_reg);
1038 EmulateInstruction::Context context;
1039 context.type = eContextArithmetic;
1040 context.SetRegisterRegisterOperands (op1_reg, op2_reg);
1042 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, (0x0000ffff & result)))
1048 // APSR.N = result<31>;
1049 // APSR.Z = IsZeroBit(result);
1050 m_new_inst_cpsr = m_opcode_cpsr;
1051 SetBit32 (m_new_inst_cpsr, CPSR_N_POS, Bit32 (result, 31));
1052 SetBit32 (m_new_inst_cpsr, CPSR_Z_POS, result == 0 ? 1 : 0);
1053 if (m_new_inst_cpsr != m_opcode_cpsr)
1055 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr))
1059 // if ArchVersion() == 4 then
1060 // APSR.C = bit UNKNOWN;
1066 // Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register.
1067 // It can optionally update the condition flags based on the value.
1069 EmulateInstructionARM::EmulateMVNImm (const uint32_t opcode, const ARMEncoding encoding)
1072 // ARM pseudo code...
1073 if (ConditionPassed())
1075 EncodingSpecificOperations();
1076 result = NOT(imm32);
1077 if d == 15 then // Can only occur for ARM encoding
1078 ALUWritePC(result); // setflags is always FALSE here
1082 APSR.N = result<31>;
1083 APSR.Z = IsZeroBit(result);
1089 if (ConditionPassed(opcode))
1091 uint32_t Rd; // the destination register
1092 uint32_t imm32; // the output after ThumbExpandImm_C or ARMExpandImm_C
1093 uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C
1097 Rd = Bits32(opcode, 11, 8);
1098 setflags = BitIsSet(opcode, 20);
1099 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
1102 Rd = Bits32(opcode, 15, 12);
1103 setflags = BitIsSet(opcode, 20);
1104 imm32 = ARMExpandImm_C(opcode, APSR_C, carry);
1106 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
1107 if (Rd == 15 && setflags)
1108 return EmulateSUBSPcLrEtc (opcode, encoding);
1113 uint32_t result = ~imm32;
1115 // The context specifies that an immediate is to be moved into Rd.
1116 EmulateInstruction::Context context;
1117 context.type = EmulateInstruction::eContextImmediate;
1118 context.SetNoArgs ();
1120 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1126 // Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register.
1127 // It can optionally update the condition flags based on the result.
1129 EmulateInstructionARM::EmulateMVNReg (const uint32_t opcode, const ARMEncoding encoding)
1132 // ARM pseudo code...
1133 if (ConditionPassed())
1135 EncodingSpecificOperations();
1136 (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
1137 result = NOT(shifted);
1138 if d == 15 then // Can only occur for ARM encoding
1139 ALUWritePC(result); // setflags is always FALSE here
1143 APSR.N = result<31>;
1144 APSR.Z = IsZeroBit(result);
1150 if (ConditionPassed(opcode))
1152 uint32_t Rm; // the source register
1153 uint32_t Rd; // the destination register
1154 ARM_ShifterType shift_t;
1155 uint32_t shift_n; // the shift applied to the value read from Rm
1157 uint32_t carry; // the carry bit after the shift operation
1160 Rd = Bits32(opcode, 2, 0);
1161 Rm = Bits32(opcode, 5, 3);
1162 setflags = !InITBlock();
1163 shift_t = SRType_LSL;
1169 Rd = Bits32(opcode, 11, 8);
1170 Rm = Bits32(opcode, 3, 0);
1171 setflags = BitIsSet(opcode, 20);
1172 shift_n = DecodeImmShiftThumb(opcode, shift_t);
1173 // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
1174 if (BadReg(Rd) || BadReg(Rm))
1178 Rd = Bits32(opcode, 15, 12);
1179 Rm = Bits32(opcode, 3, 0);
1180 setflags = BitIsSet(opcode, 20);
1181 shift_n = DecodeImmShiftARM(opcode, shift_t);
1186 bool success = false;
1187 uint32_t value = ReadCoreReg(Rm, &success);
1191 uint32_t shifted = Shift_C(value, shift_t, shift_n, APSR_C, carry, &success);
1194 uint32_t result = ~shifted;
1196 // The context specifies that an immediate is to be moved into Rd.
1197 EmulateInstruction::Context context;
1198 context.type = EmulateInstruction::eContextImmediate;
1199 context.SetNoArgs ();
1201 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1207 // PC relative immediate load into register, possibly followed by ADD (SP plus register).
1210 EmulateInstructionARM::EmulateLDRRtPCRelative (const uint32_t opcode, const ARMEncoding encoding)
1213 // ARM pseudo code...
1214 if (ConditionPassed())
1216 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
1218 address = if add then (base + imm32) else (base - imm32);
1219 data = MemU[address,4];
1221 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
1222 elsif UnalignedSupport() || address<1:0> = '00' then
1224 else // Can only apply before ARMv7
1225 if CurrentInstrSet() == InstrSet_ARM then
1226 R[t] = ROR(data, 8*UInt(address<1:0>));
1228 R[t] = bits(32) UNKNOWN;
1232 if (ConditionPassed(opcode))
1234 bool success = false;
1235 const uint32_t pc = ReadCoreReg(PC_REG, &success);
1239 // PC relative immediate load context
1240 EmulateInstruction::Context context;
1241 context.type = EmulateInstruction::eContextRegisterPlusOffset;
1242 RegisterInfo pc_reg;
1243 GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
1244 context.SetRegisterPlusOffset (pc_reg, 0);
1246 uint32_t Rt; // the destination register
1247 uint32_t imm32; // immediate offset from the PC
1248 bool add; // +imm32 or -imm32?
1249 addr_t base; // the base address
1250 addr_t address; // the PC relative address
1251 uint32_t data; // the literal data value from the PC relative load
1254 Rt = Bits32(opcode, 10, 8);
1255 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32);
1259 Rt = Bits32(opcode, 15, 12);
1260 imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32);
1261 add = BitIsSet(opcode, 23);
1262 if (Rt == 15 && InITBlock() && !LastInITBlock())
1269 base = Align(pc, 4);
1271 address = base + imm32;
1273 address = base - imm32;
1275 context.SetRegisterPlusOffset(pc_reg, address - base);
1276 data = MemURead(context, address, 4, 0, &success);
1282 if (Bits32(address, 1, 0) == 0)
1284 // In ARMv5T and above, this is an interworking branch.
1285 if (!LoadWritePC(context, data))
1291 else if (UnalignedSupport() || Bits32(address, 1, 0) == 0)
1293 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data))
1296 else // We don't handle ARM for now.
1303 // An add operation to adjust the SP.
1304 // ADD (SP plus immediate)
1306 EmulateInstructionARM::EmulateADDSPImm (const uint32_t opcode, const ARMEncoding encoding)
1309 // ARM pseudo code...
1310 if (ConditionPassed())
1312 EncodingSpecificOperations();
1313 (result, carry, overflow) = AddWithCarry(SP, imm32, '0');
1314 if d == 15 then // Can only occur for ARM encoding
1315 ALUWritePC(result); // setflags is always FALSE here
1319 APSR.N = result<31>;
1320 APSR.Z = IsZeroBit(result);
1326 bool success = false;
1328 if (ConditionPassed(opcode))
1330 const addr_t sp = ReadCoreReg (SP_REG, &success);
1333 uint32_t imm32; // the immediate operand
1335 //bool setflags = false; // Add this back if/when support eEncodingT3 eEncodingA1
1339 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm8:'00', 32);
1340 d = Bits32 (opcode, 10, 8);
1341 imm32 = (Bits32 (opcode, 7, 0) << 2);
1346 // d = 13; setflags = FALSE; imm32 = ZeroExtend(imm7:'00', 32);
1348 imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
1355 addr_t sp_offset = imm32;
1356 addr_t addr = sp + sp_offset; // the adjusted stack pointer value
1358 EmulateInstruction::Context context;
1359 context.type = EmulateInstruction::eContextAdjustStackPointer;
1360 RegisterInfo sp_reg;
1361 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
1362 context.SetRegisterPlusOffset (sp_reg, sp_offset);
1366 if (!ALUWritePC (context, addr))
1371 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, addr))
1374 // Add this back if/when support eEncodingT3 eEncodingA1
1377 // APSR.N = result<31>;
1378 // APSR.Z = IsZeroBit(result);
1380 // APSR.V = overflow;
1387 // An add operation to adjust the SP.
1388 // ADD (SP plus register)
1390 EmulateInstructionARM::EmulateADDSPRm (const uint32_t opcode, const ARMEncoding encoding)
1393 // ARM pseudo code...
1394 if (ConditionPassed())
1396 EncodingSpecificOperations();
1397 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
1398 (result, carry, overflow) = AddWithCarry(SP, shifted, '0');
1400 ALUWritePC(result); // setflags is always FALSE here
1404 APSR.N = result<31>;
1405 APSR.Z = IsZeroBit(result);
1411 bool success = false;
1413 if (ConditionPassed(opcode))
1415 const addr_t sp = ReadCoreReg (SP_REG, &success);
1418 uint32_t Rm; // the second operand
1421 Rm = Bits32(opcode, 6, 3);
1426 int32_t reg_value = ReadCoreReg(Rm, &success);
1430 addr_t addr = (int32_t)sp + reg_value; // the adjusted stack pointer value
1432 EmulateInstruction::Context context;
1433 context.type = eContextArithmetic;
1434 RegisterInfo sp_reg;
1435 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
1437 RegisterInfo other_reg;
1438 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, other_reg);
1439 context.SetRegisterRegisterOperands (sp_reg, other_reg);
1441 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr))
1447 // Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine
1448 // at a PC-relative address, and changes instruction set from ARM to Thumb, or
1449 // from Thumb to ARM.
1452 EmulateInstructionARM::EmulateBLXImmediate (const uint32_t opcode, const ARMEncoding encoding)
1455 // ARM pseudo code...
1456 if (ConditionPassed())
1458 EncodingSpecificOperations();
1459 if CurrentInstrSet() == InstrSet_ARM then
1462 LR = PC<31:1> : '1';
1463 if targetInstrSet == InstrSet_ARM then
1464 targetAddress = Align(PC,4) + imm32;
1466 targetAddress = PC + imm32;
1467 SelectInstrSet(targetInstrSet);
1468 BranchWritePC(targetAddress);
1472 bool success = true;
1474 if (ConditionPassed(opcode))
1476 EmulateInstruction::Context context;
1477 context.type = EmulateInstruction::eContextRelativeBranchImmediate;
1478 const uint32_t pc = ReadCoreReg(PC_REG, &success);
1481 addr_t lr; // next instruction address
1482 addr_t target; // target address
1483 int32_t imm32; // PC-relative offset
1487 lr = pc | 1u; // return address
1488 uint32_t S = Bit32(opcode, 26);
1489 uint32_t imm10 = Bits32(opcode, 25, 16);
1490 uint32_t J1 = Bit32(opcode, 13);
1491 uint32_t J2 = Bit32(opcode, 11);
1492 uint32_t imm11 = Bits32(opcode, 10, 0);
1493 uint32_t I1 = !(J1 ^ S);
1494 uint32_t I2 = !(J2 ^ S);
1495 uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
1496 imm32 = llvm::SignExtend32<25>(imm25);
1497 target = pc + imm32;
1498 context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
1499 if (InITBlock() && !LastInITBlock())
1505 lr = pc | 1u; // return address
1506 uint32_t S = Bit32(opcode, 26);
1507 uint32_t imm10H = Bits32(opcode, 25, 16);
1508 uint32_t J1 = Bit32(opcode, 13);
1509 uint32_t J2 = Bit32(opcode, 11);
1510 uint32_t imm10L = Bits32(opcode, 10, 1);
1511 uint32_t I1 = !(J1 ^ S);
1512 uint32_t I2 = !(J2 ^ S);
1513 uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) | (imm10L << 2);
1514 imm32 = llvm::SignExtend32<25>(imm25);
1515 target = Align(pc, 4) + imm32;
1516 context.SetISAAndImmediateSigned (eModeARM, 4 + imm32);
1517 if (InITBlock() && !LastInITBlock())
1522 lr = pc - 4; // return address
1523 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
1524 target = Align(pc, 4) + imm32;
1525 context.SetISAAndImmediateSigned (eModeARM, 8 + imm32);
1528 lr = pc - 4; // return address
1529 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | Bits32(opcode, 24, 24) << 1);
1530 target = pc + imm32;
1531 context.SetISAAndImmediateSigned (eModeThumb, 8 + imm32);
1536 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
1538 if (!BranchWritePC(context, target))
1544 // Branch with Link and Exchange (register) calls a subroutine at an address and
1545 // instruction set specified by a register.
1548 EmulateInstructionARM::EmulateBLXRm (const uint32_t opcode, const ARMEncoding encoding)
1551 // ARM pseudo code...
1552 if (ConditionPassed())
1554 EncodingSpecificOperations();
1556 if CurrentInstrSet() == InstrSet_ARM then
1557 next_instr_addr = PC - 4;
1558 LR = next_instr_addr;
1560 next_instr_addr = PC - 2;
1561 LR = next_instr_addr<31:1> : '1';
1566 bool success = false;
1568 if (ConditionPassed(opcode))
1570 EmulateInstruction::Context context;
1571 context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
1572 const uint32_t pc = ReadCoreReg(PC_REG, &success);
1573 addr_t lr; // next instruction address
1576 uint32_t Rm; // the register with the target address
1579 lr = (pc - 2) | 1u; // return address
1580 Rm = Bits32(opcode, 6, 3);
1581 // if m == 15 then UNPREDICTABLE;
1584 if (InITBlock() && !LastInITBlock())
1588 lr = pc - 4; // return address
1589 Rm = Bits32(opcode, 3, 0);
1590 // if m == 15 then UNPREDICTABLE;
1597 addr_t target = ReadCoreReg (Rm, &success);
1600 RegisterInfo dwarf_reg;
1601 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
1602 context.SetRegister (dwarf_reg);
1603 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
1605 if (!BXWritePC(context, target))
1611 // Branch and Exchange causes a branch to an address and instruction set specified by a register.
1613 EmulateInstructionARM::EmulateBXRm (const uint32_t opcode, const ARMEncoding encoding)
1616 // ARM pseudo code...
1617 if (ConditionPassed())
1619 EncodingSpecificOperations();
1624 if (ConditionPassed(opcode))
1626 EmulateInstruction::Context context;
1627 context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
1628 uint32_t Rm; // the register with the target address
1631 Rm = Bits32(opcode, 6, 3);
1632 if (InITBlock() && !LastInITBlock())
1636 Rm = Bits32(opcode, 3, 0);
1641 bool success = false;
1642 addr_t target = ReadCoreReg (Rm, &success);
1646 RegisterInfo dwarf_reg;
1647 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
1648 context.SetRegister (dwarf_reg);
1649 if (!BXWritePC(context, target))
1655 // Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an
1656 // address and instruction set specified by a register as though it were a BX instruction.
1658 // TODO: Emulate Jazelle architecture?
1659 // We currently assume that switching to Jazelle state fails, thus treating BXJ as a BX operation.
1661 EmulateInstructionARM::EmulateBXJRm (const uint32_t opcode, const ARMEncoding encoding)
1664 // ARM pseudo code...
1665 if (ConditionPassed())
1667 EncodingSpecificOperations();
1668 if JMCR.JE == '0' || CurrentInstrSet() == InstrSet_ThumbEE then
1671 if JazelleAcceptsExecution() then
1672 SwitchToJazelleExecution();
1674 SUBARCHITECTURE_DEFINED handler call;
1678 if (ConditionPassed(opcode))
1680 EmulateInstruction::Context context;
1681 context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
1682 uint32_t Rm; // the register with the target address
1685 Rm = Bits32(opcode, 19, 16);
1688 if (InITBlock() && !LastInITBlock())
1692 Rm = Bits32(opcode, 3, 0);
1699 bool success = false;
1700 addr_t target = ReadCoreReg (Rm, &success);
1704 RegisterInfo dwarf_reg;
1705 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
1706 context.SetRegister (dwarf_reg);
1707 if (!BXWritePC(context, target))
1713 // Set r7 to point to some ip offset.
1716 EmulateInstructionARM::EmulateSUBR7IPImm (const uint32_t opcode, const ARMEncoding encoding)
1719 // ARM pseudo code...
1720 if (ConditionPassed())
1722 EncodingSpecificOperations();
1723 (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
1724 if d == 15 then // Can only occur for ARM encoding
1725 ALUWritePC(result); // setflags is always FALSE here
1729 APSR.N = result<31>;
1730 APSR.Z = IsZeroBit(result);
1736 if (ConditionPassed(opcode))
1738 bool success = false;
1739 const addr_t ip = ReadCoreReg (12, &success);
1745 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1750 addr_t ip_offset = imm32;
1751 addr_t addr = ip - ip_offset; // the adjusted ip value
1753 EmulateInstruction::Context context;
1754 context.type = EmulateInstruction::eContextRegisterPlusOffset;
1755 RegisterInfo dwarf_reg;
1756 GetRegisterInfo (eRegisterKindDWARF, dwarf_r12, dwarf_reg);
1757 context.SetRegisterPlusOffset (dwarf_reg, -ip_offset);
1759 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r7, addr))
1765 // Set ip to point to some stack offset.
1766 // SUB (SP minus immediate)
1768 EmulateInstructionARM::EmulateSUBIPSPImm (const uint32_t opcode, const ARMEncoding encoding)
1771 // ARM pseudo code...
1772 if (ConditionPassed())
1774 EncodingSpecificOperations();
1775 (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
1776 if d == 15 then // Can only occur for ARM encoding
1777 ALUWritePC(result); // setflags is always FALSE here
1781 APSR.N = result<31>;
1782 APSR.Z = IsZeroBit(result);
1788 if (ConditionPassed(opcode))
1790 bool success = false;
1791 const addr_t sp = ReadCoreReg (SP_REG, &success);
1797 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1802 addr_t sp_offset = imm32;
1803 addr_t addr = sp - sp_offset; // the adjusted stack pointer value
1805 EmulateInstruction::Context context;
1806 context.type = EmulateInstruction::eContextRegisterPlusOffset;
1807 RegisterInfo dwarf_reg;
1808 GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, dwarf_reg);
1809 context.SetRegisterPlusOffset (dwarf_reg, -sp_offset);
1811 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r12, addr))
1817 // This instruction subtracts an immediate value from the SP value, and writes
1818 // the result to the destination register.
1820 // If Rd == 13 => A sub operation to adjust the SP -- allocate space for local storage.
1822 EmulateInstructionARM::EmulateSUBSPImm (const uint32_t opcode, const ARMEncoding encoding)
1825 // ARM pseudo code...
1826 if (ConditionPassed())
1828 EncodingSpecificOperations();
1829 (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
1830 if d == 15 then // Can only occur for ARM encoding
1831 ALUWritePC(result); // setflags is always FALSE here
1835 APSR.N = result<31>;
1836 APSR.Z = IsZeroBit(result);
1842 bool success = false;
1843 if (ConditionPassed(opcode))
1845 const addr_t sp = ReadCoreReg (SP_REG, &success);
1856 imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
1859 Rd = Bits32(opcode, 11, 8);
1860 setflags = BitIsSet(opcode, 20);
1861 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
1862 if (Rd == 15 && setflags)
1863 return EmulateCMPImm(opcode, eEncodingT2);
1864 if (Rd == 15 && !setflags)
1868 Rd = Bits32(opcode, 11, 8);
1870 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
1875 Rd = Bits32(opcode, 15, 12);
1876 setflags = BitIsSet(opcode, 20);
1877 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1879 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
1880 if (Rd == 15 && setflags)
1881 return EmulateSUBSPcLrEtc (opcode, encoding);
1886 AddWithCarryResult res = AddWithCarry(sp, ~imm32, 1);
1888 EmulateInstruction::Context context;
1891 uint64_t imm64 = imm32; // Need to expand it to 64 bits before attempting to negate it, or the wrong
1892 // value gets passed down to context.SetImmediateSigned.
1893 context.type = EmulateInstruction::eContextAdjustStackPointer;
1894 context.SetImmediateSigned (-imm64); // the stack pointer offset
1898 context.type = EmulateInstruction::eContextImmediate;
1899 context.SetNoArgs ();
1902 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
1908 // A store operation to the stack that also updates the SP.
1910 EmulateInstructionARM::EmulateSTRRtSP (const uint32_t opcode, const ARMEncoding encoding)
1913 // ARM pseudo code...
1914 if (ConditionPassed())
1916 EncodingSpecificOperations();
1917 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
1918 address = if index then offset_addr else R[n];
1919 MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
1920 if wback then R[n] = offset_addr;
1924 bool conditional = false;
1925 bool success = false;
1926 if (ConditionPassed(opcode, &conditional))
1928 const uint32_t addr_byte_size = GetAddressByteSize();
1929 const addr_t sp = ReadCoreReg (SP_REG, &success);
1932 uint32_t Rt; // the source register
1934 uint32_t Rn; // This function assumes Rn is the SP, but we should verify that.
1941 Rt = Bits32(opcode, 15, 12);
1942 imm12 = Bits32(opcode, 11, 0);
1943 Rn = Bits32 (opcode, 19, 16);
1945 if (Rn != 13) // 13 is the SP reg on ARM. Verify that Rn == SP.
1948 index = BitIsSet (opcode, 24);
1949 add = BitIsSet (opcode, 23);
1950 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
1952 if (wback && ((Rn == 15) || (Rn == Rt)))
1960 offset_addr = sp + imm12;
1962 offset_addr = sp - imm12;
1970 EmulateInstruction::Context context;
1972 context.type = EmulateInstruction::eContextRegisterStore;
1974 context.type = EmulateInstruction::eContextPushRegisterOnStack;
1975 RegisterInfo sp_reg;
1976 RegisterInfo dwarf_reg;
1978 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
1979 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rt, dwarf_reg);
1980 context.SetRegisterToRegisterPlusOffset ( dwarf_reg, sp_reg, addr - sp);
1983 uint32_t reg_value = ReadCoreReg(Rt, &success);
1986 if (!MemUWrite (context, addr, reg_value, addr_byte_size))
1991 const uint32_t pc = ReadCoreReg(PC_REG, &success);
1994 if (!MemUWrite (context, addr, pc, addr_byte_size))
2001 context.type = EmulateInstruction::eContextAdjustStackPointer;
2002 context.SetImmediateSigned (addr - sp);
2003 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, offset_addr))
2010 // Vector Push stores multiple extension registers to the stack.
2011 // It also updates SP to point to the start of the stored data.
2013 EmulateInstructionARM::EmulateVPUSH (const uint32_t opcode, const ARMEncoding encoding)
2016 // ARM pseudo code...
2017 if (ConditionPassed())
2019 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13);
2020 address = SP - imm32;
2024 MemA[address,4] = S[d+r]; address = address+4;
2027 // Store as two word-aligned words in the correct order for current endianness.
2028 MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
2029 MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
2030 address = address+8;
2034 bool success = false;
2035 bool conditional = false;
2036 if (ConditionPassed(opcode, &conditional))
2038 const uint32_t addr_byte_size = GetAddressByteSize();
2039 const addr_t sp = ReadCoreReg (SP_REG, &success);
2043 uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register
2044 uint32_t imm32; // stack offset
2045 uint32_t regs; // number of registers
2049 single_regs = false;
2050 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
2051 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2052 // If UInt(imm8) is odd, see "FSTMX".
2053 regs = Bits32(opcode, 7, 0) / 2;
2054 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2055 if (regs == 0 || regs > 16 || (d + regs) > 32)
2061 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22);
2062 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2063 regs = Bits32(opcode, 7, 0);
2064 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2065 if (regs == 0 || regs > 16 || (d + regs) > 32)
2071 uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
2072 uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
2073 addr_t sp_offset = imm32;
2074 addr_t addr = sp - sp_offset;
2077 EmulateInstruction::Context context;
2079 context.type = EmulateInstruction::eContextRegisterStore;
2081 context.type = EmulateInstruction::eContextPushRegisterOnStack;
2082 RegisterInfo dwarf_reg;
2083 RegisterInfo sp_reg;
2084 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
2085 for (i=0; i<regs; ++i)
2087 GetRegisterInfo (eRegisterKindDWARF, start_reg + d + i, dwarf_reg);
2088 context.SetRegisterToRegisterPlusOffset ( dwarf_reg, sp_reg, addr - sp);
2089 // uint64_t to accommodate 64-bit registers.
2090 uint64_t reg_value = ReadRegisterUnsigned (&dwarf_reg, 0, &success);
2093 if (!MemAWrite (context, addr, reg_value, reg_byte_size))
2095 addr += reg_byte_size;
2098 context.type = EmulateInstruction::eContextAdjustStackPointer;
2099 context.SetImmediateSigned (-sp_offset);
2101 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset))
2107 // Vector Pop loads multiple extension registers from the stack.
2108 // It also updates SP to point just above the loaded data.
2110 EmulateInstructionARM::EmulateVPOP (const uint32_t opcode, const ARMEncoding encoding)
2113 // ARM pseudo code...
2114 if (ConditionPassed())
2116 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13);
2121 S[d+r] = MemA[address,4]; address = address+4;
2124 word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;
2125 // Combine the word-aligned words in the correct order for current endianness.
2126 D[d+r] = if BigEndian() then word1:word2 else word2:word1;
2130 bool success = false;
2131 bool conditional = false;
2132 if (ConditionPassed(opcode, &conditional))
2134 const uint32_t addr_byte_size = GetAddressByteSize();
2135 const addr_t sp = ReadCoreReg (SP_REG, &success);
2139 uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register
2140 uint32_t imm32; // stack offset
2141 uint32_t regs; // number of registers
2145 single_regs = false;
2146 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
2147 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2148 // If UInt(imm8) is odd, see "FLDMX".
2149 regs = Bits32(opcode, 7, 0) / 2;
2150 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2151 if (regs == 0 || regs > 16 || (d + regs) > 32)
2157 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22);
2158 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2159 regs = Bits32(opcode, 7, 0);
2160 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2161 if (regs == 0 || regs > 16 || (d + regs) > 32)
2167 uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
2168 uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
2169 addr_t sp_offset = imm32;
2172 uint64_t data; // uint64_t to accomodate 64-bit registers.
2174 EmulateInstruction::Context context;
2176 context.type = EmulateInstruction::eContextRegisterLoad;
2178 context.type = EmulateInstruction::eContextPopRegisterOffStack;
2179 RegisterInfo dwarf_reg;
2180 RegisterInfo sp_reg;
2181 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
2182 for (i=0; i<regs; ++i)
2184 GetRegisterInfo (eRegisterKindDWARF, start_reg + d + i, dwarf_reg);
2185 context.SetRegisterPlusOffset (sp_reg, addr - sp);
2186 data = MemARead(context, addr, reg_byte_size, 0, &success);
2189 if (!WriteRegisterUnsigned(context, &dwarf_reg, data))
2191 addr += reg_byte_size;
2194 context.type = EmulateInstruction::eContextAdjustStackPointer;
2195 context.SetImmediateSigned (sp_offset);
2197 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset))
2203 // SVC (previously SWI)
2205 EmulateInstructionARM::EmulateSVC (const uint32_t opcode, const ARMEncoding encoding)
2208 // ARM pseudo code...
2209 if (ConditionPassed())
2211 EncodingSpecificOperations();
2216 bool success = false;
2218 if (ConditionPassed(opcode))
2220 const uint32_t pc = ReadCoreReg(PC_REG, &success);
2221 addr_t lr; // next instruction address
2224 uint32_t imm32; // the immediate constant
2225 uint32_t mode; // ARM or Thumb mode
2228 lr = (pc + 2) | 1u; // return address
2229 imm32 = Bits32(opcode, 7, 0);
2233 lr = pc + 4; // return address
2234 imm32 = Bits32(opcode, 23, 0);
2241 EmulateInstruction::Context context;
2242 context.type = EmulateInstruction::eContextSupervisorCall;
2243 context.SetISAAndImmediate (mode, imm32);
2244 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
2250 // If Then makes up to four following instructions (the IT block) conditional.
2252 EmulateInstructionARM::EmulateIT (const uint32_t opcode, const ARMEncoding encoding)
2255 // ARM pseudo code...
2256 EncodingSpecificOperations();
2257 ITSTATE.IT<7:0> = firstcond:mask;
2260 m_it_session.InitIT(Bits32(opcode, 7, 0));
2265 EmulateInstructionARM::EmulateNop (const uint32_t opcode, const ARMEncoding encoding)
2267 // NOP, nothing to do...
2271 // Branch causes a branch to a target address.
2273 EmulateInstructionARM::EmulateB (const uint32_t opcode, const ARMEncoding encoding)
2276 // ARM pseudo code...
2277 if (ConditionPassed())
2279 EncodingSpecificOperations();
2280 BranchWritePC(PC + imm32);
2284 bool success = false;
2286 if (ConditionPassed(opcode))
2288 EmulateInstruction::Context context;
2289 context.type = EmulateInstruction::eContextRelativeBranchImmediate;
2290 const uint32_t pc = ReadCoreReg(PC_REG, &success);
2293 addr_t target; // target address
2294 int32_t imm32; // PC-relative offset
2297 // The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
2298 imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1);
2299 target = pc + imm32;
2300 context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
2303 imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0));
2304 target = pc + imm32;
2305 context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
2308 // The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
2310 uint32_t S = Bit32(opcode, 26);
2311 uint32_t imm6 = Bits32(opcode, 21, 16);
2312 uint32_t J1 = Bit32(opcode, 13);
2313 uint32_t J2 = Bit32(opcode, 11);
2314 uint32_t imm11 = Bits32(opcode, 10, 0);
2315 uint32_t imm21 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1);
2316 imm32 = llvm::SignExtend32<21>(imm21);
2317 target = pc + imm32;
2318 context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
2323 uint32_t S = Bit32(opcode, 26);
2324 uint32_t imm10 = Bits32(opcode, 25, 16);
2325 uint32_t J1 = Bit32(opcode, 13);
2326 uint32_t J2 = Bit32(opcode, 11);
2327 uint32_t imm11 = Bits32(opcode, 10, 0);
2328 uint32_t I1 = !(J1 ^ S);
2329 uint32_t I2 = !(J2 ^ S);
2330 uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
2331 imm32 = llvm::SignExtend32<25>(imm25);
2332 target = pc + imm32;
2333 context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
2337 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
2338 target = pc + imm32;
2339 context.SetISAAndImmediateSigned (eModeARM, 8 + imm32);
2344 if (!BranchWritePC(context, target))
2350 // Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with
2351 // zero and conditionally branch forward a constant value. They do not affect the condition flags.
2354 EmulateInstructionARM::EmulateCB (const uint32_t opcode, const ARMEncoding encoding)
2357 // ARM pseudo code...
2358 EncodingSpecificOperations();
2359 if nonzero ^ IsZero(R[n]) then
2360 BranchWritePC(PC + imm32);
2363 bool success = false;
2365 // Read the register value from the operand register Rn.
2366 uint32_t reg_val = ReadCoreReg(Bits32(opcode, 2, 0), &success);
2370 EmulateInstruction::Context context;
2371 context.type = EmulateInstruction::eContextRelativeBranchImmediate;
2372 const uint32_t pc = ReadCoreReg(PC_REG, &success);
2376 addr_t target; // target address
2377 uint32_t imm32; // PC-relative offset to branch forward
2381 imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1;
2382 nonzero = BitIsSet(opcode, 11);
2383 target = pc + imm32;
2384 context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
2389 if (nonzero ^ (reg_val == 0))
2390 if (!BranchWritePC(context, target))
2396 // Table Branch Byte causes a PC-relative forward branch using a table of single byte offsets.
2397 // A base register provides a pointer to the table, and a second register supplies an index into the table.
2398 // The branch length is twice the value of the byte returned from the table.
2400 // Table Branch Halfword causes a PC-relative forward branch using a table of single halfword offsets.
2401 // A base register provides a pointer to the table, and a second register supplies an index into the table.
2402 // The branch length is twice the value of the halfword returned from the table.
2405 EmulateInstructionARM::EmulateTB (const uint32_t opcode, const ARMEncoding encoding)
2408 // ARM pseudo code...
2409 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
2411 halfwords = UInt(MemU[R[n]+LSL(R[m],1), 2]);
2413 halfwords = UInt(MemU[R[n]+R[m], 1]);
2414 BranchWritePC(PC + 2*halfwords);
2417 bool success = false;
2419 uint32_t Rn; // the base register which contains the address of the table of branch lengths
2420 uint32_t Rm; // the index register which contains an integer pointing to a byte/halfword in the table
2421 bool is_tbh; // true if table branch halfword
2424 Rn = Bits32(opcode, 19, 16);
2425 Rm = Bits32(opcode, 3, 0);
2426 is_tbh = BitIsSet(opcode, 4);
2427 if (Rn == 13 || BadReg(Rm))
2429 if (InITBlock() && !LastInITBlock())
2436 // Read the address of the table from the operand register Rn.
2437 // The PC can be used, in which case the table immediately follows this instruction.
2438 uint32_t base = ReadCoreReg(Rm, &success);
2443 uint32_t index = ReadCoreReg(Rm, &success);
2447 // the offsetted table address
2448 addr_t addr = base + (is_tbh ? index*2 : index);
2450 // PC-relative offset to branch forward
2451 EmulateInstruction::Context context;
2452 context.type = EmulateInstruction::eContextTableBranchReadMemory;
2453 uint32_t offset = MemURead(context, addr, is_tbh ? 2 : 1, 0, &success) * 2;
2457 const uint32_t pc = ReadCoreReg(PC_REG, &success);
2462 addr_t target = pc + offset;
2463 context.type = EmulateInstruction::eContextRelativeBranchImmediate;
2464 context.SetISAAndImmediateSigned (eModeThumb, 4 + offset);
2466 if (!BranchWritePC(context, target))
2472 // This instruction adds an immediate value to a register value, and writes the result to the destination register.
2473 // It can optionally update the condition flags based on the result.
2475 EmulateInstructionARM::EmulateADDImmThumb (const uint32_t opcode, const ARMEncoding encoding)
2478 if ConditionPassed() then
2479 EncodingSpecificOperations();
2480 (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
2483 APSR.N = result<31>;
2484 APSR.Z = IsZeroBit(result);
2489 bool success = false;
2491 if (ConditionPassed(opcode))
2499 //EncodingSpecificOperations();
2503 // d = UInt(Rd); n = UInt(Rn); setflags = !InITBlock(); imm32 = ZeroExtend(imm3, 32);
2504 d = Bits32 (opcode, 2, 0);
2505 n = Bits32 (opcode, 5, 3);
2506 setflags = !InITBlock();
2507 imm32 = Bits32 (opcode, 8,6);
2512 // d = UInt(Rdn); n = UInt(Rdn); setflags = !InITBlock(); imm32 = ZeroExtend(imm8, 32);
2513 d = Bits32 (opcode, 10, 8);
2514 n = Bits32 (opcode, 10, 8);
2515 setflags = !InITBlock();
2516 imm32 = Bits32 (opcode, 7, 0);
2521 // if Rd == '1111' && S == '1' then SEE CMN (immediate);
2522 // if Rn == '1101' then SEE ADD (SP plus immediate);
2523 // d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); imm32 = ThumbExpandImm(i:imm3:imm8);
2524 d = Bits32 (opcode, 11, 8);
2525 n = Bits32 (opcode, 19, 16);
2526 setflags = BitIsSet (opcode, 20);
2527 imm32 = ThumbExpandImm_C (opcode, APSR_C, carry_out);
2529 // if BadReg(d) || n == 15 then UNPREDICTABLE;
2530 if (BadReg (d) || (n == 15))
2537 // if Rn == '1111' then SEE ADR;
2538 // if Rn == '1101' then SEE ADD (SP plus immediate);
2539 // d = UInt(Rd); n = UInt(Rn); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32);
2540 d = Bits32 (opcode, 11, 8);
2541 n = Bits32 (opcode, 19, 16);
2543 uint32_t i = Bit32 (opcode, 26);
2544 uint32_t imm3 = Bits32 (opcode, 14, 12);
2545 uint32_t imm8 = Bits32 (opcode, 7, 0);
2546 imm32 = (i << 11) | (imm3 << 8) | imm8;
2548 // if BadReg(d) then UNPREDICTABLE;
2558 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
2562 //(result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
2563 AddWithCarryResult res = AddWithCarry (Rn, imm32, 0);
2566 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, reg_n);
2568 EmulateInstruction::Context context;
2569 context.type = eContextArithmetic;
2570 context.SetRegisterPlusOffset (reg_n, imm32);
2574 //APSR.N = result<31>;
2575 //APSR.Z = IsZeroBit(result);
2577 //APSR.V = overflow;
2578 if (!WriteCoreRegOptionalFlags (context, res.result, d, setflags, res.carry_out, res.overflow))
2585 // This instruction adds an immediate value to a register value, and writes the result to the destination
2586 // register. It can optionally update the condition flags based on the result.
2588 EmulateInstructionARM::EmulateADDImmARM (const uint32_t opcode, const ARMEncoding encoding)
2591 // ARM pseudo code...
2592 if ConditionPassed() then
2593 EncodingSpecificOperations();
2594 (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
2596 ALUWritePC(result); // setflags is always FALSE here
2600 APSR.N = result<31>;
2601 APSR.Z = IsZeroBit(result);
2606 bool success = false;
2608 if (ConditionPassed(opcode))
2611 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
2616 Rd = Bits32(opcode, 15, 12);
2617 Rn = Bits32(opcode, 19, 16);
2618 setflags = BitIsSet(opcode, 20);
2619 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2625 // Read the first operand.
2626 uint32_t val1 = ReadCoreReg(Rn, &success);
2630 AddWithCarryResult res = AddWithCarry(val1, imm32, 0);
2632 EmulateInstruction::Context context;
2633 context.type = eContextArithmetic;
2634 RegisterInfo dwarf_reg;
2635 GetRegisterInfo (eRegisterKindDWARF, Rn, dwarf_reg);
2636 context.SetRegisterPlusOffset (dwarf_reg, imm32);
2638 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
2644 // This instruction adds a register value and an optionally-shifted register value, and writes the result
2645 // to the destination register. It can optionally update the condition flags based on the result.
2647 EmulateInstructionARM::EmulateADDReg (const uint32_t opcode, const ARMEncoding encoding)
2650 // ARM pseudo code...
2651 if ConditionPassed() then
2652 EncodingSpecificOperations();
2653 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
2654 (result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
2656 ALUWritePC(result); // setflags is always FALSE here
2660 APSR.N = result<31>;
2661 APSR.Z = IsZeroBit(result);
2666 bool success = false;
2668 if (ConditionPassed(opcode))
2670 uint32_t Rd, Rn, Rm;
2671 ARM_ShifterType shift_t;
2672 uint32_t shift_n; // the shift applied to the value read from Rm
2677 Rd = Bits32(opcode, 2, 0);
2678 Rn = Bits32(opcode, 5, 3);
2679 Rm = Bits32(opcode, 8, 6);
2680 setflags = !InITBlock();
2681 shift_t = SRType_LSL;
2685 Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
2686 Rm = Bits32(opcode, 6, 3);
2688 shift_t = SRType_LSL;
2690 if (Rn == 15 && Rm == 15)
2692 if (Rd == 15 && InITBlock() && !LastInITBlock())
2696 Rd = Bits32(opcode, 15, 12);
2697 Rn = Bits32(opcode, 19, 16);
2698 Rm = Bits32(opcode, 3, 0);
2699 setflags = BitIsSet(opcode, 20);
2700 shift_n = DecodeImmShiftARM(opcode, shift_t);
2706 // Read the first operand.
2707 uint32_t val1 = ReadCoreReg(Rn, &success);
2711 // Read the second operand.
2712 uint32_t val2 = ReadCoreReg(Rm, &success);
2716 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
2719 AddWithCarryResult res = AddWithCarry(val1, shifted, 0);
2721 EmulateInstruction::Context context;
2722 context.type = eContextArithmetic;
2723 RegisterInfo op1_reg;
2724 RegisterInfo op2_reg;
2725 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rn, op1_reg);
2726 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, op2_reg);
2727 context.SetRegisterRegisterOperands (op1_reg, op2_reg);
2729 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
2735 // Compare Negative (immediate) adds a register value and an immediate value.
2736 // It updates the condition flags based on the result, and discards the result.
2738 EmulateInstructionARM::EmulateCMNImm (const uint32_t opcode, const ARMEncoding encoding)
2741 // ARM pseudo code...
2742 if ConditionPassed() then
2743 EncodingSpecificOperations();
2744 (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
2745 APSR.N = result<31>;
2746 APSR.Z = IsZeroBit(result);
2751 bool success = false;
2753 uint32_t Rn; // the first operand
2754 uint32_t imm32; // the immediate value to be compared with
2757 Rn = Bits32(opcode, 19, 16);
2758 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
2763 Rn = Bits32(opcode, 19, 16);
2764 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2769 // Read the register value from the operand register Rn.
2770 uint32_t reg_val = ReadCoreReg(Rn, &success);
2774 AddWithCarryResult res = AddWithCarry(reg_val, imm32, 0);
2776 EmulateInstruction::Context context;
2777 context.type = EmulateInstruction::eContextImmediate;
2778 context.SetNoArgs ();
2779 if (!WriteFlags(context, res.result, res.carry_out, res.overflow))
2785 // Compare Negative (register) adds a register value and an optionally-shifted register value.
2786 // It updates the condition flags based on the result, and discards the result.
2788 EmulateInstructionARM::EmulateCMNReg (const uint32_t opcode, const ARMEncoding encoding)
2791 // ARM pseudo code...
2792 if ConditionPassed() then
2793 EncodingSpecificOperations();
2794 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
2795 (result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
2796 APSR.N = result<31>;
2797 APSR.Z = IsZeroBit(result);
2802 bool success = false;
2804 uint32_t Rn; // the first operand
2805 uint32_t Rm; // the second operand
2806 ARM_ShifterType shift_t;
2807 uint32_t shift_n; // the shift applied to the value read from Rm
2810 Rn = Bits32(opcode, 2, 0);
2811 Rm = Bits32(opcode, 5, 3);
2812 shift_t = SRType_LSL;
2816 Rn = Bits32(opcode, 19, 16);
2817 Rm = Bits32(opcode, 3, 0);
2818 shift_n = DecodeImmShiftThumb(opcode, shift_t);
2819 // if n == 15 || BadReg(m) then UNPREDICTABLE;
2820 if (Rn == 15 || BadReg(Rm))
2824 Rn = Bits32(opcode, 19, 16);
2825 Rm = Bits32(opcode, 3, 0);
2826 shift_n = DecodeImmShiftARM(opcode, shift_t);
2831 // Read the register value from register Rn.
2832 uint32_t val1 = ReadCoreReg(Rn, &success);
2836 // Read the register value from register Rm.
2837 uint32_t val2 = ReadCoreReg(Rm, &success);
2841 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
2844 AddWithCarryResult res = AddWithCarry(val1, shifted, 0);
2846 EmulateInstruction::Context context;
2847 context.type = EmulateInstruction::eContextImmediate;
2848 context.SetNoArgs();
2849 if (!WriteFlags(context, res.result, res.carry_out, res.overflow))
2855 // Compare (immediate) subtracts an immediate value from a register value.
2856 // It updates the condition flags based on the result, and discards the result.
2858 EmulateInstructionARM::EmulateCMPImm (const uint32_t opcode, const ARMEncoding encoding)
2861 // ARM pseudo code...
2862 if ConditionPassed() then
2863 EncodingSpecificOperations();
2864 (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1');
2865 APSR.N = result<31>;
2866 APSR.Z = IsZeroBit(result);
2871 bool success = false;
2873 uint32_t Rn; // the first operand
2874 uint32_t imm32; // the immediate value to be compared with
2877 Rn = Bits32(opcode, 10, 8);
2878 imm32 = Bits32(opcode, 7, 0);
2881 Rn = Bits32(opcode, 19, 16);
2882 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
2887 Rn = Bits32(opcode, 19, 16);
2888 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2893 // Read the register value from the operand register Rn.
2894 uint32_t reg_val = ReadCoreReg(Rn, &success);
2898 AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1);
2900 EmulateInstruction::Context context;
2901 context.type = EmulateInstruction::eContextImmediate;
2902 context.SetNoArgs ();
2903 if (!WriteFlags(context, res.result, res.carry_out, res.overflow))
2909 // Compare (register) subtracts an optionally-shifted register value from a register value.
2910 // It updates the condition flags based on the result, and discards the result.
2912 EmulateInstructionARM::EmulateCMPReg (const uint32_t opcode, const ARMEncoding encoding)
2915 // ARM pseudo code...
2916 if ConditionPassed() then
2917 EncodingSpecificOperations();
2918 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
2919 (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), '1');
2920 APSR.N = result<31>;
2921 APSR.Z = IsZeroBit(result);
2926 bool success = false;
2928 uint32_t Rn; // the first operand
2929 uint32_t Rm; // the second operand
2930 ARM_ShifterType shift_t;
2931 uint32_t shift_n; // the shift applied to the value read from Rm
2934 Rn = Bits32(opcode, 2, 0);
2935 Rm = Bits32(opcode, 5, 3);
2936 shift_t = SRType_LSL;
2940 Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
2941 Rm = Bits32(opcode, 6, 3);
2942 shift_t = SRType_LSL;
2944 if (Rn < 8 && Rm < 8)
2946 if (Rn == 15 || Rm == 15)
2950 Rn = Bits32(opcode, 19, 16);
2951 Rm = Bits32(opcode, 3, 0);
2952 shift_n = DecodeImmShiftARM(opcode, shift_t);
2957 // Read the register value from register Rn.
2958 uint32_t val1 = ReadCoreReg(Rn, &success);
2962 // Read the register value from register Rm.
2963 uint32_t val2 = ReadCoreReg(Rm, &success);
2967 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
2970 AddWithCarryResult res = AddWithCarry(val1, ~shifted, 1);
2972 EmulateInstruction::Context context;
2973 context.type = EmulateInstruction::eContextImmediate;
2974 context.SetNoArgs();
2975 if (!WriteFlags(context, res.result, res.carry_out, res.overflow))
2981 // Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits,
2982 // shifting in copies of its sign bit, and writes the result to the destination register. It can
2983 // optionally update the condition flags based on the result.
2985 EmulateInstructionARM::EmulateASRImm (const uint32_t opcode, const ARMEncoding encoding)
2988 // ARM pseudo code...
2989 if ConditionPassed() then
2990 EncodingSpecificOperations();
2991 (result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C);
2992 if d == 15 then // Can only occur for ARM encoding
2993 ALUWritePC(result); // setflags is always FALSE here
2997 APSR.N = result<31>;
2998 APSR.Z = IsZeroBit(result);
3003 return EmulateShiftImm (opcode, encoding, SRType_ASR);
3006 // Arithmetic Shift Right (register) shifts a register value right by a variable number of bits,
3007 // shifting in copies of its sign bit, and writes the result to the destination register.
3008 // The variable number of bits is read from the bottom byte of a register. It can optionally update
3009 // the condition flags based on the result.
3011 EmulateInstructionARM::EmulateASRReg (const uint32_t opcode, const ARMEncoding encoding)
3014 // ARM pseudo code...
3015 if ConditionPassed() then
3016 EncodingSpecificOperations();
3017 shift_n = UInt(R[m]<7:0>);
3018 (result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C);
3021 APSR.N = result<31>;
3022 APSR.Z = IsZeroBit(result);
3027 return EmulateShiftReg (opcode, encoding, SRType_ASR);
3030 // Logical Shift Left (immediate) shifts a register value left by an immediate number of bits,
3031 // shifting in zeros, and writes the result to the destination register. It can optionally
3032 // update the condition flags based on the result.
3034 EmulateInstructionARM::EmulateLSLImm (const uint32_t opcode, const ARMEncoding encoding)
3037 // ARM pseudo code...
3038 if ConditionPassed() then
3039 EncodingSpecificOperations();
3040 (result, carry) = Shift_C(R[m], SRType_LSL, shift_n, APSR.C);
3041 if d == 15 then // Can only occur for ARM encoding
3042 ALUWritePC(result); // setflags is always FALSE here
3046 APSR.N = result<31>;
3047 APSR.Z = IsZeroBit(result);
3052 return EmulateShiftImm (opcode, encoding, SRType_LSL);
3055 // Logical Shift Left (register) shifts a register value left by a variable number of bits,
3056 // shifting in zeros, and writes the result to the destination register. The variable number
3057 // of bits is read from the bottom byte of a register. It can optionally update the condition
3058 // flags based on the result.
3060 EmulateInstructionARM::EmulateLSLReg (const uint32_t opcode, const ARMEncoding encoding)
3063 // ARM pseudo code...
3064 if ConditionPassed() then
3065 EncodingSpecificOperations();
3066 shift_n = UInt(R[m]<7:0>);
3067 (result, carry) = Shift_C(R[m], SRType_LSL, shift_n, APSR.C);
3070 APSR.N = result<31>;
3071 APSR.Z = IsZeroBit(result);
3076 return EmulateShiftReg (opcode, encoding, SRType_LSL);
3079 // Logical Shift Right (immediate) shifts a register value right by an immediate number of bits,
3080 // shifting in zeros, and writes the result to the destination register. It can optionally
3081 // update the condition flags based on the result.
3083 EmulateInstructionARM::EmulateLSRImm (const uint32_t opcode, const ARMEncoding encoding)
3086 // ARM pseudo code...
3087 if ConditionPassed() then
3088 EncodingSpecificOperations();
3089 (result, carry) = Shift_C(R[m], SRType_LSR, shift_n, APSR.C);
3090 if d == 15 then // Can only occur for ARM encoding
3091 ALUWritePC(result); // setflags is always FALSE here
3095 APSR.N = result<31>;
3096 APSR.Z = IsZeroBit(result);
3101 return EmulateShiftImm (opcode, encoding, SRType_LSR);
3104 // Logical Shift Right (register) shifts a register value right by a variable number of bits,
3105 // shifting in zeros, and writes the result to the destination register. The variable number
3106 // of bits is read from the bottom byte of a register. It can optionally update the condition
3107 // flags based on the result.
3109 EmulateInstructionARM::EmulateLSRReg (const uint32_t opcode, const ARMEncoding encoding)
3112 // ARM pseudo code...
3113 if ConditionPassed() then
3114 EncodingSpecificOperations();
3115 shift_n = UInt(R[m]<7:0>);
3116 (result, carry) = Shift_C(R[m], SRType_LSR, shift_n, APSR.C);
3119 APSR.N = result<31>;
3120 APSR.Z = IsZeroBit(result);
3125 return EmulateShiftReg (opcode, encoding, SRType_LSR);
3128 // Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value.
3129 // The bits that are rotated off the right end are inserted into the vacated bit positions on the left.
3130 // It can optionally update the condition flags based on the result.
3132 EmulateInstructionARM::EmulateRORImm (const uint32_t opcode, const ARMEncoding encoding)
3135 // ARM pseudo code...
3136 if ConditionPassed() then
3137 EncodingSpecificOperations();
3138 (result, carry) = Shift_C(R[m], SRType_ROR, shift_n, APSR.C);
3139 if d == 15 then // Can only occur for ARM encoding
3140 ALUWritePC(result); // setflags is always FALSE here
3144 APSR.N = result<31>;
3145 APSR.Z = IsZeroBit(result);
3150 return EmulateShiftImm (opcode, encoding, SRType_ROR);
3153 // Rotate Right (register) provides the value of the contents of a register rotated by a variable number of bits.
3154 // The bits that are rotated off the right end are inserted into the vacated bit positions on the left.
3155 // The variable number of bits is read from the bottom byte of a register. It can optionally update the condition
3156 // flags based on the result.
3158 EmulateInstructionARM::EmulateRORReg (const uint32_t opcode, const ARMEncoding encoding)
3161 // ARM pseudo code...
3162 if ConditionPassed() then
3163 EncodingSpecificOperations();
3164 shift_n = UInt(R[m]<7:0>);
3165 (result, carry) = Shift_C(R[m], SRType_ROR, shift_n, APSR.C);
3168 APSR.N = result<31>;
3169 APSR.Z = IsZeroBit(result);
3174 return EmulateShiftReg (opcode, encoding, SRType_ROR);
3177 // Rotate Right with Extend provides the value of the contents of a register shifted right by one place,
3178 // with the carry flag shifted into bit [31].
3180 // RRX can optionally update the condition flags based on the result.
3181 // In that case, bit [0] is shifted into the carry flag.
3183 EmulateInstructionARM::EmulateRRX (const uint32_t opcode, const ARMEncoding encoding)
3186 // ARM pseudo code...
3187 if ConditionPassed() then
3188 EncodingSpecificOperations();
3189 (result, carry) = Shift_C(R[m], SRType_RRX, 1, APSR.C);
3190 if d == 15 then // Can only occur for ARM encoding
3191 ALUWritePC(result); // setflags is always FALSE here
3195 APSR.N = result<31>;
3196 APSR.Z = IsZeroBit(result);
3201 return EmulateShiftImm (opcode, encoding, SRType_RRX);
3205 EmulateInstructionARM::EmulateShiftImm (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type)
3207 // assert(shift_type == SRType_ASR
3208 // || shift_type == SRType_LSL
3209 // || shift_type == SRType_LSR
3210 // || shift_type == SRType_ROR
3211 // || shift_type == SRType_RRX);
3213 bool success = false;
3215 if (ConditionPassed(opcode))
3217 uint32_t Rd; // the destination register
3218 uint32_t Rm; // the first operand register
3219 uint32_t imm5; // encoding for the shift amount
3220 uint32_t carry; // the carry bit after the shift operation
3223 // Special case handling!
3224 // A8.6.139 ROR (immediate) -- Encoding T1
3225 ARMEncoding use_encoding = encoding;
3226 if (shift_type == SRType_ROR && use_encoding == eEncodingT1)
3228 // Morph the T1 encoding from the ARM Architecture Manual into T2 encoding to
3229 // have the same decoding of bit fields as the other Thumb2 shift operations.
3230 use_encoding = eEncodingT2;
3233 switch (use_encoding) {
3235 // Due to the above special case handling!
3236 if (shift_type == SRType_ROR)
3239 Rd = Bits32(opcode, 2, 0);
3240 Rm = Bits32(opcode, 5, 3);
3241 setflags = !InITBlock();
3242 imm5 = Bits32(opcode, 10, 6);
3246 // There's no imm form of RRX instructions.
3247 if (shift_type == SRType_RRX)
3250 Rd = Bits32(opcode, 11, 8);
3251 Rm = Bits32(opcode, 3, 0);
3252 setflags = BitIsSet(opcode, 20);
3253 imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6);
3254 if (BadReg(Rd) || BadReg(Rm))
3258 Rd = Bits32(opcode, 15, 12);
3259 Rm = Bits32(opcode, 3, 0);
3260 setflags = BitIsSet(opcode, 20);
3261 imm5 = Bits32(opcode, 11, 7);
3267 // A8.6.139 ROR (immediate)
3268 if (shift_type == SRType_ROR && imm5 == 0)
3269 shift_type = SRType_RRX;
3271 // Get the first operand.
3272 uint32_t value = ReadCoreReg (Rm, &success);
3276 // Decode the shift amount if not RRX.
3277 uint32_t amt = (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5));
3279 uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success);
3283 // The context specifies that an immediate is to be moved into Rd.
3284 EmulateInstruction::Context context;
3285 context.type = EmulateInstruction::eContextImmediate;
3286 context.SetNoArgs ();
3288 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
3295 EmulateInstructionARM::EmulateShiftReg (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type)
3297 // assert(shift_type == SRType_ASR
3298 // || shift_type == SRType_LSL
3299 // || shift_type == SRType_LSR
3300 // || shift_type == SRType_ROR);
3302 bool success = false;
3304 if (ConditionPassed(opcode))
3306 uint32_t Rd; // the destination register
3307 uint32_t Rn; // the first operand register
3308 uint32_t Rm; // the register whose bottom byte contains the amount to shift by
3309 uint32_t carry; // the carry bit after the shift operation
3313 Rd = Bits32(opcode, 2, 0);
3315 Rm = Bits32(opcode, 5, 3);
3316 setflags = !InITBlock();
3319 Rd = Bits32(opcode, 11, 8);
3320 Rn = Bits32(opcode, 19, 16);
3321 Rm = Bits32(opcode, 3, 0);
3322 setflags = BitIsSet(opcode, 20);
3323 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
3327 Rd = Bits32(opcode, 15, 12);
3328 Rn = Bits32(opcode, 3, 0);
3329 Rm = Bits32(opcode, 11, 8);
3330 setflags = BitIsSet(opcode, 20);
3331 if (Rd == 15 || Rn == 15 || Rm == 15)
3338 // Get the first operand.
3339 uint32_t value = ReadCoreReg (Rn, &success);
3342 // Get the Rm register content.
3343 uint32_t val = ReadCoreReg (Rm, &success);
3347 // Get the shift amount.
3348 uint32_t amt = Bits32(val, 7, 0);
3350 uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success);
3354 // The context specifies that an immediate is to be moved into Rd.
3355 EmulateInstruction::Context context;
3356 context.type = EmulateInstruction::eContextImmediate;
3357 context.SetNoArgs ();
3359 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
3365 // LDM loads multiple registers from consecutive memory locations, using an
3366 // address from a base register. Optionally the address just above the highest of those locations
3367 // can be written back to the base register.
3369 EmulateInstructionARM::EmulateLDM (const uint32_t opcode, const ARMEncoding encoding)
3372 // ARM pseudo code...
3373 if ConditionPassed()
3374 EncodingSpecificOperations(); NullCheckIfThumbEE (n);
3378 if registers<i> == '1' then
3379 R[i] = MemA[address, 4]; address = address + 4;
3380 if registers<15> == '1' then
3381 LoadWritePC (MemA[address, 4]);
3383 if wback && registers<n> == '0' then R[n] = R[n] + 4 * BitCount (registers);
3384 if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
3388 bool success = false;
3389 bool conditional = false;
3390 if (ConditionPassed(opcode, &conditional))
3393 uint32_t registers = 0;
3395 const uint32_t addr_byte_size = GetAddressByteSize();
3399 // n = UInt(Rn); registers = '00000000':register_list; wback = (registers<n> == '0');
3400 n = Bits32 (opcode, 10, 8);
3401 registers = Bits32 (opcode, 7, 0);
3402 registers = registers & 0x00ff; // Make sure the top 8 bits are zeros.
3403 wback = BitIsClear (registers, n);
3404 // if BitCount(registers) < 1 then UNPREDICTABLE;
3405 if (BitCount(registers) < 1)
3409 // if W == '1' && Rn == '1101' then SEE POP;
3410 // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1');
3411 n = Bits32 (opcode, 19, 16);
3412 registers = Bits32 (opcode, 15, 0);
3413 registers = registers & 0xdfff; // Make sure bit 13 is zero.
3414 wback = BitIsSet (opcode, 21);
3416 // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
3418 || (BitCount (registers) < 2)
3419 || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15)))
3422 // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
3423 if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock())
3426 // if wback && registers<n> == '1' then UNPREDICTABLE;
3428 && BitIsSet (registers, n))
3433 n = Bits32 (opcode, 19, 16);
3434 registers = Bits32 (opcode, 15, 0);
3435 wback = BitIsSet (opcode, 21);
3437 || (BitCount (registers) < 1))
3445 const addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
3449 EmulateInstruction::Context context;
3450 context.type = EmulateInstruction::eContextRegisterPlusOffset;
3451 RegisterInfo dwarf_reg;
3452 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
3453 context.SetRegisterPlusOffset (dwarf_reg, offset);
3455 for (int i = 0; i < 14; ++i)
3457 if (BitIsSet (registers, i))
3459 context.type = EmulateInstruction::eContextRegisterPlusOffset;
3460 context.SetRegisterPlusOffset (dwarf_reg, offset);
3461 if (wback && (n == 13)) // Pop Instruction
3464 context.type = EmulateInstruction::eContextRegisterLoad;
3466 context.type = EmulateInstruction::eContextPopRegisterOffStack;
3469 // R[i] = MemA [address, 4]; address = address + 4;
3470 uint32_t data = MemARead (context, base_address + offset, addr_byte_size, 0, &success);
3474 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data))
3477 offset += addr_byte_size;
3481 if (BitIsSet (registers, 15))
3483 //LoadWritePC (MemA [address, 4]);
3484 context.type = EmulateInstruction::eContextRegisterPlusOffset;
3485 context.SetRegisterPlusOffset (dwarf_reg, offset);
3486 uint32_t data = MemARead (context, base_address + offset, addr_byte_size, 0, &success);
3489 // In ARMv5T and above, this is an interworking branch.
3490 if (!LoadWritePC(context, data))
3494 if (wback && BitIsClear (registers, n))
3496 // R[n] = R[n] + 4 * BitCount (registers)
3497 int32_t offset = addr_byte_size * BitCount (registers);
3498 context.type = EmulateInstruction::eContextAdjustBaseRegister;
3499 context.SetRegisterPlusOffset (dwarf_reg, offset);
3501 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, base_address + offset))
3504 if (wback && BitIsSet (registers, n))
3505 // R[n] bits(32) UNKNOWN;
3506 return WriteBits32Unknown (n);
3511 // LDMDA loads multiple registers from consecutive memory locations using an address from a base register.
3512 // The consecutive memory locations end at this address and the address just below the lowest of those locations
3513 // can optionally be written back to the base register.
3515 EmulateInstructionARM::EmulateLDMDA (const uint32_t opcode, const ARMEncoding encoding)
3518 // ARM pseudo code...
3519 if ConditionPassed() then
3520 EncodingSpecificOperations();
3521 address = R[n] - 4*BitCount(registers) + 4;
3524 if registers<i> == '1' then
3525 R[i] = MemA[address,4]; address = address + 4;
3527 if registers<15> == '1' then
3528 LoadWritePC(MemA[address,4]);
3530 if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
3531 if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
3534 bool success = false;
3536 if (ConditionPassed(opcode))
3539 uint32_t registers = 0;
3541 const uint32_t addr_byte_size = GetAddressByteSize();
3543 // EncodingSpecificOperations();
3547 // n = UInt(Rn); registers = register_list; wback = (W == '1');
3548 n = Bits32 (opcode, 19, 16);
3549 registers = Bits32 (opcode, 15, 0);
3550 wback = BitIsSet (opcode, 21);
3552 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
3553 if ((n == 15) || (BitCount (registers) < 1))
3561 // address = R[n] - 4*BitCount(registers) + 4;
3564 addr_t Rn = ReadCoreReg (n, &success);
3569 addr_t address = Rn - (addr_byte_size * BitCount (registers)) + addr_byte_size;
3571 EmulateInstruction::Context context;
3572 context.type = EmulateInstruction::eContextRegisterPlusOffset;
3573 RegisterInfo dwarf_reg;
3574 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
3575 context.SetRegisterPlusOffset (dwarf_reg, offset);
3578 for (int i = 0; i < 14; ++i)
3580 // if registers<i> == '1' then
3581 if (BitIsSet (registers, i))
3583 // R[i] = MemA[address,4]; address = address + 4;
3584 context.SetRegisterPlusOffset (dwarf_reg, Rn - (address + offset));
3585 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3588 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data))
3590 offset += addr_byte_size;
3594 // if registers<15> == '1' then
3595 // LoadWritePC(MemA[address,4]);
3596 if (BitIsSet (registers, 15))
3598 context.SetRegisterPlusOffset (dwarf_reg, offset);
3599 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3602 // In ARMv5T and above, this is an interworking branch.
3603 if (!LoadWritePC(context, data))
3607 // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
3608 if (wback && BitIsClear (registers, n))
3613 offset = (addr_byte_size * BitCount (registers)) * -1;
3614 context.type = EmulateInstruction::eContextAdjustBaseRegister;
3615 context.SetImmediateSigned (offset);
3616 addr_t addr = Rn + offset;
3617 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr))
3621 // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
3622 if (wback && BitIsSet (registers, n))
3623 return WriteBits32Unknown (n);
3628 // LDMDB loads multiple registers from consecutive memory locations using an address from a base register. The
3629 // consecutive memory lcoations end just below this address, and the address of the lowest of those locations can
3630 // be optionally written back to the base register.
3632 EmulateInstructionARM::EmulateLDMDB (const uint32_t opcode, const ARMEncoding encoding)
3635 // ARM pseudo code...
3636 if ConditionPassed() then
3637 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
3638 address = R[n] - 4*BitCount(registers);
3641 if registers<i> == '1' then
3642 R[i] = MemA[address,4]; address = address + 4;
3643 if registers<15> == '1' then
3644 LoadWritePC(MemA[address,4]);
3646 if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
3647 if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
3650 bool success = false;
3652 if (ConditionPassed(opcode))
3655 uint32_t registers = 0;
3657 const uint32_t addr_byte_size = GetAddressByteSize();
3661 // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1');
3662 n = Bits32 (opcode, 19, 16);
3663 registers = Bits32 (opcode, 15, 0);
3664 registers = registers & 0xdfff; // Make sure bit 13 is a zero.
3665 wback = BitIsSet (opcode, 21);
3667 // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
3669 || (BitCount (registers) < 2)
3670 || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15)))
3673 // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
3674 if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock())
3677 // if wback && registers<n> == '1' then UNPREDICTABLE;
3678 if (wback && BitIsSet (registers, n))
3684 // n = UInt(Rn); registers = register_list; wback = (W == '1');
3685 n = Bits32 (opcode, 19, 16);
3686 registers = Bits32 (opcode, 15, 0);
3687 wback = BitIsSet (opcode, 21);
3689 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
3690 if ((n == 15) || (BitCount (registers) < 1))
3699 // address = R[n] - 4*BitCount(registers);
3702 addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
3707 addr_t address = Rn - (addr_byte_size * BitCount (registers));
3708 EmulateInstruction::Context context;
3709 context.type = EmulateInstruction::eContextRegisterPlusOffset;
3710 RegisterInfo dwarf_reg;
3711 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
3712 context.SetRegisterPlusOffset (dwarf_reg, Rn - address);
3714 for (int i = 0; i < 14; ++i)
3716 if (BitIsSet (registers, i))
3718 // R[i] = MemA[address,4]; address = address + 4;
3719 context.SetRegisterPlusOffset (dwarf_reg, Rn - (address + offset));
3720 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3724 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data))
3727 offset += addr_byte_size;
3731 // if registers<15> == '1' then
3732 // LoadWritePC(MemA[address,4]);
3733 if (BitIsSet (registers, 15))
3735 context.SetRegisterPlusOffset (dwarf_reg, offset);
3736 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3739 // In ARMv5T and above, this is an interworking branch.
3740 if (!LoadWritePC(context, data))
3744 // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
3745 if (wback && BitIsClear (registers, n))
3750 offset = (addr_byte_size * BitCount (registers)) * -1;
3751 context.type = EmulateInstruction::eContextAdjustBaseRegister;
3752 context.SetImmediateSigned (offset);
3753 addr_t addr = Rn + offset;
3754 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr))
3758 // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
3759 if (wback && BitIsSet (registers, n))
3760 return WriteBits32Unknown (n);
3765 // LDMIB loads multiple registers from consecutive memory locations using an address from a base register. The
3766 // consecutive memory locations start just above this address, and thea ddress of the last of those locations can
3767 // optinoally be written back to the base register.
3769 EmulateInstructionARM::EmulateLDMIB (const uint32_t opcode, const ARMEncoding encoding)
3772 if ConditionPassed() then
3773 EncodingSpecificOperations();
3777 if registers<i> == '1' then
3778 R[i] = MemA[address,4]; address = address + 4;
3779 if registers<15> == '1' then
3780 LoadWritePC(MemA[address,4]);
3782 if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
3783 if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
3786 bool success = false;
3788 if (ConditionPassed(opcode))
3791 uint32_t registers = 0;
3793 const uint32_t addr_byte_size = GetAddressByteSize();
3797 // n = UInt(Rn); registers = register_list; wback = (W == '1');
3798 n = Bits32 (opcode, 19, 16);
3799 registers = Bits32 (opcode, 15, 0);
3800 wback = BitIsSet (opcode, 21);
3802 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
3803 if ((n == 15) || (BitCount (registers) < 1))
3810 // address = R[n] + 4;
3813 addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
3818 addr_t address = Rn + addr_byte_size;
3820 EmulateInstruction::Context context;
3821 context.type = EmulateInstruction::eContextRegisterPlusOffset;
3822 RegisterInfo dwarf_reg;
3823 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
3824 context.SetRegisterPlusOffset (dwarf_reg, offset);
3826 for (int i = 0; i < 14; ++i)
3828 if (BitIsSet (registers, i))
3830 // R[i] = MemA[address,4]; address = address + 4;
3832 context.SetRegisterPlusOffset (dwarf_reg, offset + addr_byte_size);
3833 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3837 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data))
3840 offset += addr_byte_size;
3844 // if registers<15> == '1' then
3845 // LoadWritePC(MemA[address,4]);
3846 if (BitIsSet (registers, 15))
3848 context.SetRegisterPlusOffset (dwarf_reg, offset);
3849 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3852 // In ARMv5T and above, this is an interworking branch.
3853 if (!LoadWritePC(context, data))
3857 // if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
3858 if (wback && BitIsClear (registers, n))
3863 offset = addr_byte_size * BitCount (registers);
3864 context.type = EmulateInstruction::eContextAdjustBaseRegister;
3865 context.SetImmediateSigned (offset);
3866 addr_t addr = Rn + offset;
3867 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr))
3871 // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
3872 if (wback && BitIsSet (registers, n))
3873 return WriteBits32Unknown (n);
3878 // Load Register (immediate) calculates an address from a base register value and
3879 // an immediate offset, loads a word from memory, and writes to a register.
3880 // LDR (immediate, Thumb)
3882 EmulateInstructionARM::EmulateLDRRtRnImm (const uint32_t opcode, const ARMEncoding encoding)
3885 // ARM pseudo code...
3886 if (ConditionPassed())
3888 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
3889 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
3890 address = if index then offset_addr else R[n];
3891 data = MemU[address,4];
3892 if wback then R[n] = offset_addr;
3894 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
3895 elsif UnalignedSupport() || address<1:0> = '00' then
3897 else R[t] = bits(32) UNKNOWN; // Can only apply before ARMv7
3901 bool success = false;
3903 if (ConditionPassed(opcode))
3905 uint32_t Rt; // the destination register
3906 uint32_t Rn; // the base register
3907 uint32_t imm32; // the immediate offset used to form the address
3908 addr_t offset_addr; // the offset address
3909 addr_t address; // the calculated address
3910 uint32_t data; // the literal data value from memory load
3911 bool add, index, wback;
3914 Rt = Bits32(opcode, 2, 0);
3915 Rn = Bits32(opcode, 5, 3);
3916 imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32);
3917 // index = TRUE; add = TRUE; wback = FALSE
3925 // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
3926 Rt = Bits32 (opcode, 10, 8);
3928 imm32 = Bits32 (opcode, 7, 0) << 2;
3930 // index = TRUE; add = TRUE; wback = FALSE;
3938 // if Rn == '1111' then SEE LDR (literal);
3939 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
3940 Rt = Bits32 (opcode, 15, 12);
3941 Rn = Bits32 (opcode, 19, 16);
3942 imm32 = Bits32 (opcode, 11, 0);
3944 // index = TRUE; add = TRUE; wback = FALSE;
3949 // if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
3950 if ((Rt == 15) && InITBlock() && !LastInITBlock())
3956 // if Rn == '1111' then SEE LDR (literal);
3957 // if P == '1' && U == '1' && W == '0' then SEE LDRT;
3958 // if Rn == '1101' && P == '0' && U == '1' && W == '1' && imm8 == '00000100' then SEE POP;
3959 // if P == '0' && W == '0' then UNDEFINED;
3960 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
3963 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
3964 Rt = Bits32 (opcode, 15, 12);
3965 Rn = Bits32 (opcode, 19, 16);
3966 imm32 = Bits32 (opcode, 7, 0);
3968 // index = (P == '1'); add = (U == '1'); wback = (W == '1');
3969 index = BitIsSet (opcode, 10);
3970 add = BitIsSet (opcode, 9);
3971 wback = BitIsSet (opcode, 8);
3973 // if (wback && n == t) || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE;
3974 if ((wback && (Rn == Rt)) || ((Rt == 15) && InITBlock() && !LastInITBlock()))
3982 uint32_t base = ReadCoreReg (Rn, &success);
3986 offset_addr = base + imm32;
3988 offset_addr = base - imm32;
3990 address = (index ? offset_addr : base);
3992 RegisterInfo base_reg;
3993 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rn, base_reg);
3996 EmulateInstruction::Context ctx;
3997 ctx.type = EmulateInstruction::eContextAdjustBaseRegister;
3998 ctx.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base));
4000 if (!WriteRegisterUnsigned (ctx, eRegisterKindDWARF, dwarf_r0 + Rn, offset_addr))
4004 // Prepare to write to the Rt register.
4005 EmulateInstruction::Context context;
4006 context.type = EmulateInstruction::eContextRegisterLoad;
4007 context.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base));
4009 // Read memory from the address.
4010 data = MemURead(context, address, 4, 0, &success);
4016 if (Bits32(address, 1, 0) == 0)
4018 if (!LoadWritePC(context, data))
4024 else if (UnalignedSupport() || Bits32(address, 1, 0) == 0)
4026 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data))
4030 WriteBits32Unknown (Rt);
4035 // STM (Store Multiple Increment After) stores multiple registers to consecutive memory locations using an address
4036 // from a base register. The consecutive memory locations start at this address, and teh address just above the last
4037 // of those locations can optionally be written back to the base register.
4039 EmulateInstructionARM::EmulateSTM (const uint32_t opcode, const ARMEncoding encoding)
4042 if ConditionPassed() then
4043 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4047 if registers<i> == '1' then
4048 if i == n && wback && i != LowestSetBit(registers) then
4049 MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1
4051 MemA[address,4] = R[i];
4052 address = address + 4;
4054 if registers<15> == '1' then // Only possible for encoding A1
4055 MemA[address,4] = PCStoreValue();
4056 if wback then R[n] = R[n] + 4*BitCount(registers);
4059 bool success = false;
4061 if (ConditionPassed(opcode))
4064 uint32_t registers = 0;
4066 const uint32_t addr_byte_size = GetAddressByteSize();
4068 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4072 // n = UInt(Rn); registers = '00000000':register_list; wback = TRUE;
4073 n = Bits32 (opcode, 10, 8);
4074 registers = Bits32 (opcode, 7, 0);
4075 registers = registers & 0x00ff; // Make sure the top 8 bits are zeros.
4078 // if BitCount(registers) < 1 then UNPREDICTABLE;
4079 if (BitCount (registers) < 1)
4085 // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1');
4086 n = Bits32 (opcode, 19, 16);
4087 registers = Bits32 (opcode, 15, 0);
4088 registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros.
4089 wback = BitIsSet (opcode, 21);
4091 // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
4092 if ((n == 15) || (BitCount (registers) < 2))
4095 // if wback && registers<n> == '1' then UNPREDICTABLE;
4096 if (wback && BitIsSet (registers, n))
4102 // n = UInt(Rn); registers = register_list; wback = (W == '1');
4103 n = Bits32 (opcode, 19, 16);
4104 registers = Bits32 (opcode, 15, 0);
4105 wback = BitIsSet (opcode, 21);
4107 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4108 if ((n == 15) || (BitCount (registers) < 1))
4119 const addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4123 EmulateInstruction::Context context;
4124 context.type = EmulateInstruction::eContextRegisterStore;
4125 RegisterInfo base_reg;
4126 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4129 uint32_t lowest_set_bit = 14;
4130 for (uint32_t i = 0; i < 14; ++i)
4132 // if registers<i> == '1' then
4133 if (BitIsSet (registers, i))
4135 if (i < lowest_set_bit)
4137 // if i == n && wback && i != LowestSetBit(registers) then
4138 if ((i == n) && wback && (i != lowest_set_bit))
4139 // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1
4140 WriteBits32UnknownToMemory (address + offset);
4143 // MemA[address,4] = R[i];
4144 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success);
4148 RegisterInfo data_reg;
4149 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
4150 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset);
4151 if (!MemAWrite (context, address + offset, data, addr_byte_size))
4155 // address = address + 4;
4156 offset += addr_byte_size;
4160 // if registers<15> == '1' then // Only possible for encoding A1
4161 // MemA[address,4] = PCStoreValue();
4162 if (BitIsSet (registers, 15))
4164 RegisterInfo pc_reg;
4165 GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
4166 context.SetRegisterPlusOffset (pc_reg, 8);
4167 const uint32_t pc = ReadCoreReg (PC_REG, &success);
4171 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4175 // if wback then R[n] = R[n] + 4*BitCount(registers);
4178 offset = addr_byte_size * BitCount (registers);
4179 context.type = EmulateInstruction::eContextAdjustBaseRegister;
4180 context.SetImmediateSigned (offset);
4181 addr_t data = address + offset;
4182 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
4189 // STMDA (Store Multiple Decrement After) stores multiple registers to consecutive memory locations using an address
4190 // from a base register. The consecutive memory locations end at this address, and the address just below the lowest
4191 // of those locations can optionally be written back to the base register.
4193 EmulateInstructionARM::EmulateSTMDA (const uint32_t opcode, const ARMEncoding encoding)
4196 if ConditionPassed() then
4197 EncodingSpecificOperations();
4198 address = R[n] - 4*BitCount(registers) + 4;
4201 if registers<i> == '1' then
4202 if i == n && wback && i != LowestSetBit(registers) then
4203 MemA[address,4] = bits(32) UNKNOWN;
4205 MemA[address,4] = R[i];
4206 address = address + 4;
4208 if registers<15> == '1' then
4209 MemA[address,4] = PCStoreValue();
4211 if wback then R[n] = R[n] - 4*BitCount(registers);
4214 bool success = false;
4216 if (ConditionPassed(opcode))
4219 uint32_t registers = 0;
4221 const uint32_t addr_byte_size = GetAddressByteSize();
4223 // EncodingSpecificOperations();
4227 // n = UInt(Rn); registers = register_list; wback = (W == '1');
4228 n = Bits32 (opcode, 19, 16);
4229 registers = Bits32 (opcode, 15, 0);
4230 wback = BitIsSet (opcode, 21);
4232 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4233 if ((n == 15) || (BitCount (registers) < 1))
4240 // address = R[n] - 4*BitCount(registers) + 4;
4242 addr_t Rn = ReadCoreReg (n, &success);
4246 addr_t address = Rn - (addr_byte_size * BitCount (registers)) + 4;
4248 EmulateInstruction::Context context;
4249 context.type = EmulateInstruction::eContextRegisterStore;
4250 RegisterInfo base_reg;
4251 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4254 uint32_t lowest_bit_set = 14;
4255 for (uint32_t i = 0; i < 14; ++i)
4257 // if registers<i> == '1' then
4258 if (BitIsSet (registers, i))
4260 if (i < lowest_bit_set)
4262 //if i == n && wback && i != LowestSetBit(registers) then
4263 if ((i == n) && wback && (i != lowest_bit_set))
4264 // MemA[address,4] = bits(32) UNKNOWN;
4265 WriteBits32UnknownToMemory (address + offset);
4268 // MemA[address,4] = R[i];
4269 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success);
4273 RegisterInfo data_reg;
4274 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
4275 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset));
4276 if (!MemAWrite (context, address + offset, data, addr_byte_size))
4280 // address = address + 4;
4281 offset += addr_byte_size;
4285 // if registers<15> == '1' then
4286 // MemA[address,4] = PCStoreValue();
4287 if (BitIsSet (registers, 15))
4289 RegisterInfo pc_reg;
4290 GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
4291 context.SetRegisterPlusOffset (pc_reg, 8);
4292 const uint32_t pc = ReadCoreReg (PC_REG, &success);
4296 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4300 // if wback then R[n] = R[n] - 4*BitCount(registers);
4303 offset = (addr_byte_size * BitCount (registers)) * -1;
4304 context.type = EmulateInstruction::eContextAdjustBaseRegister;
4305 context.SetImmediateSigned (offset);
4306 addr_t data = Rn + offset;
4307 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
4314 // STMDB (Store Multiple Decrement Before) stores multiple registers to consecutive memory locations using an address
4315 // from a base register. The consecutive memory locations end just below this address, and the address of the first of
4316 // those locations can optionally be written back to the base register.
4318 EmulateInstructionARM::EmulateSTMDB (const uint32_t opcode, const ARMEncoding encoding)
4321 if ConditionPassed() then
4322 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4323 address = R[n] - 4*BitCount(registers);
4326 if registers<i> == '1' then
4327 if i == n && wback && i != LowestSetBit(registers) then
4328 MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1
4330 MemA[address,4] = R[i];
4331 address = address + 4;
4333 if registers<15> == '1' then // Only possible for encoding A1
4334 MemA[address,4] = PCStoreValue();
4336 if wback then R[n] = R[n] - 4*BitCount(registers);
4340 bool success = false;
4342 if (ConditionPassed(opcode))
4345 uint32_t registers = 0;
4347 const uint32_t addr_byte_size = GetAddressByteSize();
4349 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4353 // if W == '1' && Rn == '1101' then SEE PUSH;
4354 if ((BitIsSet (opcode, 21)) && (Bits32 (opcode, 19, 16) == 13))
4358 // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1');
4359 n = Bits32 (opcode, 19, 16);
4360 registers = Bits32 (opcode, 15, 0);
4361 registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros.
4362 wback = BitIsSet (opcode, 21);
4363 // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
4364 if ((n == 15) || BitCount (registers) < 2)
4366 // if wback && registers<n> == '1' then UNPREDICTABLE;
4367 if (wback && BitIsSet (registers, n))
4372 // if W == '1' && Rn == '1101Õ && BitCount(register_list) >= 2 then SEE PUSH;
4373 if (BitIsSet (opcode, 21) && (Bits32 (opcode, 19, 16) == 13) && BitCount (Bits32 (opcode, 15, 0)) >= 2)
4377 // n = UInt(Rn); registers = register_list; wback = (W == '1');
4378 n = Bits32 (opcode, 19, 16);
4379 registers = Bits32 (opcode, 15, 0);
4380 wback = BitIsSet (opcode, 21);
4381 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4382 if ((n == 15) || BitCount (registers) < 1)
4390 // address = R[n] - 4*BitCount(registers);
4393 addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4397 addr_t address = Rn - (addr_byte_size * BitCount (registers));
4399 EmulateInstruction::Context context;
4400 context.type = EmulateInstruction::eContextRegisterStore;
4401 RegisterInfo base_reg;
4402 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4405 uint32_t lowest_set_bit = 14;
4406 for (uint32_t i = 0; i < 14; ++i)
4408 // if registers<i> == '1' then
4409 if (BitIsSet (registers, i))
4411 if (i < lowest_set_bit)
4413 // if i == n && wback && i != LowestSetBit(registers) then
4414 if ((i == n) && wback && (i != lowest_set_bit))
4415 // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1
4416 WriteBits32UnknownToMemory (address + offset);
4419 // MemA[address,4] = R[i];
4420 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success);
4424 RegisterInfo data_reg;
4425 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
4426 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset));
4427 if (!MemAWrite (context, address + offset, data, addr_byte_size))
4431 // address = address + 4;
4432 offset += addr_byte_size;
4436 // if registers<15> == '1' then // Only possible for encoding A1
4437 // MemA[address,4] = PCStoreValue();
4438 if (BitIsSet (registers, 15))
4440 RegisterInfo pc_reg;
4441 GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
4442 context.SetRegisterPlusOffset (pc_reg, 8);
4443 const uint32_t pc = ReadCoreReg (PC_REG, &success);
4447 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4451 // if wback then R[n] = R[n] - 4*BitCount(registers);
4454 offset = (addr_byte_size * BitCount (registers)) * -1;
4455 context.type = EmulateInstruction::eContextAdjustBaseRegister;
4456 context.SetImmediateSigned (offset);
4457 addr_t data = Rn + offset;
4458 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
4465 // STMIB (Store Multiple Increment Before) stores multiple registers to consecutive memory locations using an address
4466 // from a base register. The consecutive memory locations start just above this address, and the address of the last
4467 // of those locations can optionally be written back to the base register.
4469 EmulateInstructionARM::EmulateSTMIB (const uint32_t opcode, const ARMEncoding encoding)
4472 if ConditionPassed() then
4473 EncodingSpecificOperations();
4477 if registers<i> == '1' then
4478 if i == n && wback && i != LowestSetBit(registers) then
4479 MemA[address,4] = bits(32) UNKNOWN;
4481 MemA[address,4] = R[i];
4482 address = address + 4;
4484 if registers<15> == '1' then
4485 MemA[address,4] = PCStoreValue();
4487 if wback then R[n] = R[n] + 4*BitCount(registers);
4490 bool success = false;
4492 if (ConditionPassed(opcode))
4495 uint32_t registers = 0;
4497 const uint32_t addr_byte_size = GetAddressByteSize();
4499 // EncodingSpecificOperations();
4503 // n = UInt(Rn); registers = register_list; wback = (W == '1');
4504 n = Bits32 (opcode, 19, 16);
4505 registers = Bits32 (opcode, 15, 0);
4506 wback = BitIsSet (opcode, 21);
4508 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4509 if ((n == 15) && (BitCount (registers) < 1))
4515 // address = R[n] + 4;
4518 addr_t Rn = ReadCoreReg (n, &success);
4522 addr_t address = Rn + addr_byte_size;
4524 EmulateInstruction::Context context;
4525 context.type = EmulateInstruction::eContextRegisterStore;
4526 RegisterInfo base_reg;
4527 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4529 uint32_t lowest_set_bit = 14;
4531 for (uint32_t i = 0; i < 14; ++i)
4533 // if registers<i> == '1' then
4534 if (BitIsSet (registers, i))
4536 if (i < lowest_set_bit)
4538 // if i == n && wback && i != LowestSetBit(registers) then
4539 if ((i == n) && wback && (i != lowest_set_bit))
4540 // MemA[address,4] = bits(32) UNKNOWN;
4541 WriteBits32UnknownToMemory (address + offset);
4545 // MemA[address,4] = R[i];
4546 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success);
4550 RegisterInfo data_reg;
4551 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
4552 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset + addr_byte_size);
4553 if (!MemAWrite (context, address + offset, data, addr_byte_size))
4557 // address = address + 4;
4558 offset += addr_byte_size;
4562 // if registers<15> == '1' then
4563 // MemA[address,4] = PCStoreValue();
4564 if (BitIsSet (registers, 15))
4566 RegisterInfo pc_reg;
4567 GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
4568 context.SetRegisterPlusOffset (pc_reg, 8);
4569 const uint32_t pc = ReadCoreReg (PC_REG, &success);
4573 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4577 // if wback then R[n] = R[n] + 4*BitCount(registers);
4580 offset = addr_byte_size * BitCount (registers);
4581 context.type = EmulateInstruction::eContextAdjustBaseRegister;
4582 context.SetImmediateSigned (offset);
4583 addr_t data = Rn + offset;
4584 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
4591 // STR (store immediate) calcualtes an address from a base register value and an immediate offset, and stores a word
4592 // from a register to memory. It can use offset, post-indexed, or pre-indexed addressing.
4594 EmulateInstructionARM::EmulateSTRThumb (const uint32_t opcode, const ARMEncoding encoding)
4597 if ConditionPassed() then
4598 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4599 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
4600 address = if index then offset_addr else R[n];
4601 if UnalignedSupport() || address<1:0> == '00' then
4602 MemU[address,4] = R[t];
4603 else // Can only occur before ARMv7
4604 MemU[address,4] = bits(32) UNKNOWN;
4605 if wback then R[n] = offset_addr;
4608 bool success = false;
4610 if (ConditionPassed(opcode))
4612 const uint32_t addr_byte_size = GetAddressByteSize();
4620 // EncodingSpecificOperations (); NullCheckIfThumbEE(n);
4624 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'00', 32);
4625 t = Bits32 (opcode, 2, 0);
4626 n = Bits32 (opcode, 5, 3);
4627 imm32 = Bits32 (opcode, 10, 6) << 2;
4629 // index = TRUE; add = TRUE; wback = FALSE;
4636 // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
4637 t = Bits32 (opcode, 10, 8);
4639 imm32 = Bits32 (opcode, 7, 0) << 2;
4641 // index = TRUE; add = TRUE; wback = FALSE;
4648 // if Rn == '1111' then UNDEFINED;
4649 if (Bits32 (opcode, 19, 16) == 15)
4652 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
4653 t = Bits32 (opcode, 15, 12);
4654 n = Bits32 (opcode, 19, 16);
4655 imm32 = Bits32 (opcode, 11, 0);
4657 // index = TRUE; add = TRUE; wback = FALSE;
4662 // if t == 15 then UNPREDICTABLE;
4668 // if P == '1' && U == '1' && W == '0' then SEE STRT;
4669 // if Rn == '1101' && P == '1' && U == '0' && W == '1' && imm8 == '00000100' then SEE PUSH;
4670 // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
4671 if ((Bits32 (opcode, 19, 16) == 15)
4672 || (BitIsClear (opcode, 10) && BitIsClear (opcode, 8)))
4675 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
4676 t = Bits32 (opcode, 15, 12);
4677 n = Bits32 (opcode, 19, 16);
4678 imm32 = Bits32 (opcode, 7, 0);
4680 // index = (P == '1'); add = (U == '1'); wback = (W == '1');
4681 index = BitIsSet (opcode, 10);
4682 add = BitIsSet (opcode, 9);
4683 wback = BitIsSet (opcode, 8);
4685 // if t == 15 || (wback && n == t) then UNPREDICTABLE;
4686 if ((t == 15) || (wback && (n == t)))
4697 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
4698 uint32_t base_address = ReadCoreReg (n, &success);
4703 offset_addr = base_address + imm32;
4705 offset_addr = base_address - imm32;
4707 // address = if index then offset_addr else R[n];
4709 address = offset_addr;
4711 address = base_address;
4713 EmulateInstruction::Context context;
4714 context.type = eContextRegisterStore;
4715 RegisterInfo base_reg;
4716 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4718 // if UnalignedSupport() || address<1:0> == '00' then
4719 if (UnalignedSupport () || (BitIsClear (address, 1) && BitIsClear (address, 0)))
4721 // MemU[address,4] = R[t];
4722 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
4726 RegisterInfo data_reg;
4727 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
4728 int32_t offset = address - base_address;
4729 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset);
4730 if (!MemUWrite (context, address, data, addr_byte_size))
4735 // MemU[address,4] = bits(32) UNKNOWN;
4736 WriteBits32UnknownToMemory (address);
4739 // if wback then R[n] = offset_addr;
4742 context.type = eContextRegisterLoad;
4743 context.SetAddress (offset_addr);
4744 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
4751 // STR (Store Register) calculates an address from a base register value and an offset register value, stores a
4752 // word from a register to memory. The offset register value can optionally be shifted.
4754 EmulateInstructionARM::EmulateSTRRegister (const uint32_t opcode, const ARMEncoding encoding)
4757 if ConditionPassed() then
4758 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4759 offset = Shift(R[m], shift_t, shift_n, APSR.C);
4760 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
4761 address = if index then offset_addr else R[n];
4762 if t == 15 then // Only possible for encoding A1
4763 data = PCStoreValue();
4766 if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then
4767 MemU[address,4] = data;
4768 else // Can only occur before ARMv7
4769 MemU[address,4] = bits(32) UNKNOWN;
4770 if wback then R[n] = offset_addr;
4773 bool success = false;
4775 if (ConditionPassed(opcode))
4777 const uint32_t addr_byte_size = GetAddressByteSize();
4782 ARM_ShifterType shift_t;
4788 // EncodingSpecificOperations (); NullCheckIfThumbEE(n);
4792 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
4793 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
4794 t = Bits32 (opcode, 2, 0);
4795 n = Bits32 (opcode, 5, 3);
4796 m = Bits32 (opcode, 8, 6);
4798 // index = TRUE; add = TRUE; wback = FALSE;
4803 // (shift_t, shift_n) = (SRType_LSL, 0);
4804 shift_t = SRType_LSL;
4809 // if Rn == '1111' then UNDEFINED;
4810 if (Bits32 (opcode, 19, 16) == 15)
4813 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
4814 t = Bits32 (opcode, 15, 12);
4815 n = Bits32 (opcode, 19, 16);
4816 m = Bits32 (opcode, 3, 0);
4818 // index = TRUE; add = TRUE; wback = FALSE;
4823 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
4824 shift_t = SRType_LSL;
4825 shift_n = Bits32 (opcode, 5, 4);
4827 // if t == 15 || BadReg(m) then UNPREDICTABLE;
4828 if ((t == 15) || (BadReg (m)))
4834 // if P == '0' && W == '1' then SEE STRT;
4835 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
4836 t = Bits32 (opcode, 15, 12);
4837 n = Bits32 (opcode, 19, 16);
4838 m = Bits32 (opcode, 3, 0);
4840 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
4841 index = BitIsSet (opcode, 24);
4842 add = BitIsSet (opcode, 23);
4843 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
4845 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
4846 uint32_t typ = Bits32 (opcode, 6, 5);
4847 uint32_t imm5 = Bits32 (opcode, 11, 7);
4848 shift_n = DecodeImmShift(typ, imm5, shift_t);
4850 // if m == 15 then UNPREDICTABLE;
4854 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
4855 if (wback && ((n == 15) || (n == t)))
4868 addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4872 uint32_t Rm_data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
4876 // offset = Shift(R[m], shift_t, shift_n, APSR.C);
4877 offset = Shift (Rm_data, shift_t, shift_n, APSR_C, &success);
4881 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
4883 offset_addr = base_address + offset;
4885 offset_addr = base_address - offset;
4887 // address = if index then offset_addr else R[n];
4889 address = offset_addr;
4891 address = base_address;
4894 // if t == 15 then // Only possible for encoding A1
4896 // data = PCStoreValue();
4897 data = ReadCoreReg (PC_REG, &success);
4900 data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
4905 EmulateInstruction::Context context;
4906 context.type = eContextRegisterStore;
4908 // if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then
4909 if (UnalignedSupport ()
4910 || (BitIsClear (address, 1) && BitIsClear (address, 0))
4911 || CurrentInstrSet() == eModeARM)
4913 // MemU[address,4] = data;
4915 RegisterInfo base_reg;
4916 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4918 RegisterInfo data_reg;
4919 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
4921 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - base_address);
4922 if (!MemUWrite (context, address, data, addr_byte_size))
4927 // MemU[address,4] = bits(32) UNKNOWN;
4928 WriteBits32UnknownToMemory (address);
4930 // if wback then R[n] = offset_addr;
4933 context.type = eContextRegisterLoad;
4934 context.SetAddress (offset_addr);
4935 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
4944 EmulateInstructionARM::EmulateSTRBThumb (const uint32_t opcode, const ARMEncoding encoding)
4947 if ConditionPassed() then
4948 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4949 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
4950 address = if index then offset_addr else R[n];
4951 MemU[address,1] = R[t]<7:0>;
4952 if wback then R[n] = offset_addr;
4956 bool success = false;
4958 if (ConditionPassed(opcode))
4966 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4970 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
4971 t = Bits32 (opcode, 2, 0);
4972 n = Bits32 (opcode, 5, 3);
4973 imm32 = Bits32 (opcode, 10, 6);
4975 // index = TRUE; add = TRUE; wback = FALSE;
4982 // if Rn == '1111' then UNDEFINED;
4983 if (Bits32 (opcode, 19, 16) == 15)
4986 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
4987 t = Bits32 (opcode, 15, 12);
4988 n = Bits32 (opcode, 19, 16);
4989 imm32 = Bits32 (opcode, 11, 0);
4991 // index = TRUE; add = TRUE; wback = FALSE;
4996 // if BadReg(t) then UNPREDICTABLE;
5002 // if P == '1' && U == '1' && W == '0' then SEE STRBT;
5003 // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
5004 if (Bits32 (opcode, 19, 16) == 15)
5007 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
5008 t = Bits32 (opcode, 15, 12);
5009 n = Bits32 (opcode, 19, 16);
5010 imm32 = Bits32 (opcode, 7, 0);
5012 // index = (P == '1'); add = (U == '1'); wback = (W == '1');
5013 index = BitIsSet (opcode, 10);
5014 add = BitIsSet (opcode, 9);
5015 wback = BitIsSet (opcode, 8);
5017 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE
5018 if ((BadReg (t)) || (wback && (n == t)))
5028 addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
5032 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5034 offset_addr = base_address + imm32;
5036 offset_addr = base_address - imm32;
5038 // address = if index then offset_addr else R[n];
5040 address = offset_addr;
5042 address = base_address;
5044 // MemU[address,1] = R[t]<7:0>
5045 RegisterInfo base_reg;
5046 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5048 RegisterInfo data_reg;
5049 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
5051 EmulateInstruction::Context context;
5052 context.type = eContextRegisterStore;
5053 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - base_address);
5055 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
5059 data = Bits32 (data, 7, 0);
5061 if (!MemUWrite (context, address, data, 1))
5064 // if wback then R[n] = offset_addr;
5067 context.type = eContextRegisterLoad;
5068 context.SetAddress (offset_addr);
5069 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
5078 // STRH (register) calculates an address from a base register value and an offset register value, and stores a
5079 // halfword from a register to memory. The offset register alue can be shifted left by 0, 1, 2, or 3 bits.
5081 EmulateInstructionARM::EmulateSTRHRegister (const uint32_t opcode, const ARMEncoding encoding)
5084 if ConditionPassed() then
5085 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5086 offset = Shift(R[m], shift_t, shift_n, APSR.C);
5087 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5088 address = if index then offset_addr else R[n];
5089 if UnalignedSupport() || address<0> == '0' then
5090 MemU[address,2] = R[t]<15:0>;
5091 else // Can only occur before ARMv7
5092 MemU[address,2] = bits(16) UNKNOWN;
5093 if wback then R[n] = offset_addr;
5096 bool success = false;
5098 if (ConditionPassed(opcode))
5106 ARM_ShifterType shift_t;
5109 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5113 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
5114 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5115 t = Bits32 (opcode, 2, 0);
5116 n = Bits32 (opcode, 5, 3);
5117 m = Bits32 (opcode, 8, 6);
5119 // index = TRUE; add = TRUE; wback = FALSE;
5124 // (shift_t, shift_n) = (SRType_LSL, 0);
5125 shift_t = SRType_LSL;
5131 // if Rn == '1111' then UNDEFINED;
5132 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5133 t = Bits32 (opcode, 15, 12);
5134 n = Bits32 (opcode, 19, 16);
5135 m = Bits32 (opcode, 3, 0);
5139 // index = TRUE; add = TRUE; wback = FALSE;
5144 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
5145 shift_t = SRType_LSL;
5146 shift_n = Bits32 (opcode, 5, 4);
5148 // if BadReg(t) || BadReg(m) then UNPREDICTABLE;
5149 if (BadReg (t) || BadReg (m))
5155 // if P == '0' && W == '1' then SEE STRHT;
5156 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5157 t = Bits32 (opcode, 15, 12);
5158 n = Bits32 (opcode, 19, 16);
5159 m = Bits32 (opcode, 3, 0);
5161 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
5162 index = BitIsSet (opcode, 24);
5163 add = BitIsSet (opcode, 23);
5164 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
5166 // (shift_t, shift_n) = (SRType_LSL, 0);
5167 shift_t = SRType_LSL;
5170 // if t == 15 || m == 15 then UNPREDICTABLE;
5171 if ((t == 15) || (m == 15))
5174 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
5175 if (wback && ((n == 15) || (n == t)))
5184 uint32_t Rm = ReadCoreReg (m, &success);
5188 uint32_t Rn = ReadCoreReg (n, &success);
5192 // offset = Shift(R[m], shift_t, shift_n, APSR.C);
5193 uint32_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
5197 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5200 offset_addr = Rn + offset;
5202 offset_addr = Rn - offset;
5204 // address = if index then offset_addr else R[n];
5207 address = offset_addr;
5211 EmulateInstruction::Context context;
5212 context.type = eContextRegisterStore;
5213 RegisterInfo base_reg;
5214 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5215 RegisterInfo offset_reg;
5216 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
5218 // if UnalignedSupport() || address<0> == '0' then
5219 if (UnalignedSupport() || BitIsClear (address, 0))
5221 // MemU[address,2] = R[t]<15:0>;
5222 uint32_t Rt = ReadCoreReg (t, &success);
5226 EmulateInstruction::Context context;
5227 context.type = eContextRegisterStore;
5228 RegisterInfo base_reg;
5229 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5230 RegisterInfo offset_reg;
5231 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
5232 RegisterInfo data_reg;
5233 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
5234 context.SetRegisterToRegisterPlusIndirectOffset (base_reg, offset_reg, data_reg);
5236 if (!MemUWrite (context, address, Bits32 (Rt, 15, 0), 2))
5239 else // Can only occur before ARMv7
5241 // MemU[address,2] = bits(16) UNKNOWN;
5244 // if wback then R[n] = offset_addr;
5247 context.type = eContextAdjustBaseRegister;
5248 context.SetAddress (offset_addr);
5249 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
5257 // Add with Carry (immediate) adds an immediate value and the carry flag value to a register value,
5258 // and writes the result to the destination register. It can optionally update the condition flags
5259 // based on the result.
5261 EmulateInstructionARM::EmulateADCImm (const uint32_t opcode, const ARMEncoding encoding)
5264 // ARM pseudo code...
5265 if ConditionPassed() then
5266 EncodingSpecificOperations();
5267 (result, carry, overflow) = AddWithCarry(R[n], imm32, APSR.C);
5268 if d == 15 then // Can only occur for ARM encoding
5269 ALUWritePC(result); // setflags is always FALSE here
5273 APSR.N = result<31>;
5274 APSR.Z = IsZeroBit(result);
5279 bool success = false;
5281 if (ConditionPassed(opcode))
5284 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
5289 Rd = Bits32(opcode, 11, 8);
5290 Rn = Bits32(opcode, 19, 16);
5291 setflags = BitIsSet(opcode, 20);
5292 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
5293 if (BadReg(Rd) || BadReg(Rn))
5297 Rd = Bits32(opcode, 15, 12);
5298 Rn = Bits32(opcode, 19, 16);
5299 setflags = BitIsSet(opcode, 20);
5300 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
5302 if (Rd == 15 && setflags)
5303 return EmulateSUBSPcLrEtc (opcode, encoding);
5309 // Read the first operand.
5310 int32_t val1 = ReadCoreReg(Rn, &success);
5314 AddWithCarryResult res = AddWithCarry(val1, imm32, APSR_C);
5316 EmulateInstruction::Context context;
5317 context.type = EmulateInstruction::eContextImmediate;
5318 context.SetNoArgs ();
5320 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
5326 // Add with Carry (register) adds a register value, the carry flag value, and an optionally-shifted
5327 // register value, and writes the result to the destination register. It can optionally update the
5328 // condition flags based on the result.
5330 EmulateInstructionARM::EmulateADCReg (const uint32_t opcode, const ARMEncoding encoding)
5333 // ARM pseudo code...
5334 if ConditionPassed() then
5335 EncodingSpecificOperations();
5336 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
5337 (result, carry, overflow) = AddWithCarry(R[n], shifted, APSR.C);
5338 if d == 15 then // Can only occur for ARM encoding
5339 ALUWritePC(result); // setflags is always FALSE here
5343 APSR.N = result<31>;
5344 APSR.Z = IsZeroBit(result);
5349 bool success = false;
5351 if (ConditionPassed(opcode))
5353 uint32_t Rd, Rn, Rm;
5354 ARM_ShifterType shift_t;
5355 uint32_t shift_n; // the shift applied to the value read from Rm
5360 Rd = Rn = Bits32(opcode, 2, 0);
5361 Rm = Bits32(opcode, 5, 3);
5362 setflags = !InITBlock();
5363 shift_t = SRType_LSL;
5367 Rd = Bits32(opcode, 11, 8);
5368 Rn = Bits32(opcode, 19, 16);
5369 Rm = Bits32(opcode, 3, 0);
5370 setflags = BitIsSet(opcode, 20);
5371 shift_n = DecodeImmShiftThumb(opcode, shift_t);
5372 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5376 Rd = Bits32(opcode, 15, 12);
5377 Rn = Bits32(opcode, 19, 16);
5378 Rm = Bits32(opcode, 3, 0);
5379 setflags = BitIsSet(opcode, 20);
5380 shift_n = DecodeImmShiftARM(opcode, shift_t);
5382 if (Rd == 15 && setflags)
5383 return EmulateSUBSPcLrEtc (opcode, encoding);
5389 // Read the first operand.
5390 int32_t val1 = ReadCoreReg(Rn, &success);
5394 // Read the second operand.
5395 int32_t val2 = ReadCoreReg(Rm, &success);
5399 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
5402 AddWithCarryResult res = AddWithCarry(val1, shifted, APSR_C);
5404 EmulateInstruction::Context context;
5405 context.type = EmulateInstruction::eContextImmediate;
5406 context.SetNoArgs ();
5408 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
5414 // This instruction adds an immediate value to the PC value to form a PC-relative address,
5415 // and writes the result to the destination register.
5417 EmulateInstructionARM::EmulateADR (const uint32_t opcode, const ARMEncoding encoding)
5420 // ARM pseudo code...
5421 if ConditionPassed() then
5422 EncodingSpecificOperations();
5423 result = if add then (Align(PC,4) + imm32) else (Align(PC,4) - imm32);
5424 if d == 15 then // Can only occur for ARM encodings
5430 bool success = false;
5432 if (ConditionPassed(opcode))
5435 uint32_t imm32; // the immediate value to be added/subtracted to/from the PC
5440 Rd = Bits32(opcode, 10, 8);
5441 imm32 = ThumbImm8Scaled(opcode); // imm32 = ZeroExtend(imm8:'00', 32)
5446 Rd = Bits32(opcode, 11, 8);
5447 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
5448 add = (Bits32(opcode, 24, 21) == 0); // 0b0000 => ADD; 0b0101 => SUB
5454 Rd = Bits32(opcode, 15, 12);
5455 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
5456 add = (Bits32(opcode, 24, 21) == 0x4); // 0b0100 => ADD; 0b0010 => SUB
5462 // Read the PC value.
5463 uint32_t pc = ReadCoreReg(PC_REG, &success);
5467 uint32_t result = (add ? Align(pc, 4) + imm32 : Align(pc, 4) - imm32);
5469 EmulateInstruction::Context context;
5470 context.type = EmulateInstruction::eContextImmediate;
5471 context.SetNoArgs ();
5473 if (!WriteCoreReg(context, result, Rd))
5479 // This instruction performs a bitwise AND of a register value and an immediate value, and writes the result
5480 // to the destination register. It can optionally update the condition flags based on the result.
5482 EmulateInstructionARM::EmulateANDImm (const uint32_t opcode, const ARMEncoding encoding)
5485 // ARM pseudo code...
5486 if ConditionPassed() then
5487 EncodingSpecificOperations();
5488 result = R[n] AND imm32;
5489 if d == 15 then // Can only occur for ARM encoding
5490 ALUWritePC(result); // setflags is always FALSE here
5494 APSR.N = result<31>;
5495 APSR.Z = IsZeroBit(result);
5500 bool success = false;
5502 if (ConditionPassed(opcode))
5505 uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn
5507 uint32_t carry; // the carry bit after ARM/Thumb Expand operation
5511 Rd = Bits32(opcode, 11, 8);
5512 Rn = Bits32(opcode, 19, 16);
5513 setflags = BitIsSet(opcode, 20);
5514 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
5515 // if Rd == '1111' && S == '1' then SEE TST (immediate);
5516 if (Rd == 15 && setflags)
5517 return EmulateTSTImm(opcode, eEncodingT1);
5518 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
5522 Rd = Bits32(opcode, 15, 12);
5523 Rn = Bits32(opcode, 19, 16);
5524 setflags = BitIsSet(opcode, 20);
5525 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
5527 if (Rd == 15 && setflags)
5528 return EmulateSUBSPcLrEtc (opcode, encoding);
5534 // Read the first operand.
5535 uint32_t val1 = ReadCoreReg(Rn, &success);
5539 uint32_t result = val1 & imm32;
5541 EmulateInstruction::Context context;
5542 context.type = EmulateInstruction::eContextImmediate;
5543 context.SetNoArgs ();
5545 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
5551 // This instruction performs a bitwise AND of a register value and an optionally-shifted register value,
5552 // and writes the result to the destination register. It can optionally update the condition flags
5553 // based on the result.
5555 EmulateInstructionARM::EmulateANDReg (const uint32_t opcode, const ARMEncoding encoding)
5558 // ARM pseudo code...
5559 if ConditionPassed() then
5560 EncodingSpecificOperations();
5561 (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
5562 result = R[n] AND shifted;
5563 if d == 15 then // Can only occur for ARM encoding
5564 ALUWritePC(result); // setflags is always FALSE here
5568 APSR.N = result<31>;
5569 APSR.Z = IsZeroBit(result);
5574 bool success = false;
5576 if (ConditionPassed(opcode))
5578 uint32_t Rd, Rn, Rm;
5579 ARM_ShifterType shift_t;
5580 uint32_t shift_n; // the shift applied to the value read from Rm
5586 Rd = Rn = Bits32(opcode, 2, 0);
5587 Rm = Bits32(opcode, 5, 3);
5588 setflags = !InITBlock();
5589 shift_t = SRType_LSL;
5593 Rd = Bits32(opcode, 11, 8);
5594 Rn = Bits32(opcode, 19, 16);
5595 Rm = Bits32(opcode, 3, 0);
5596 setflags = BitIsSet(opcode, 20);
5597 shift_n = DecodeImmShiftThumb(opcode, shift_t);
5598 // if Rd == '1111' && S == '1' then SEE TST (register);
5599 if (Rd == 15 && setflags)
5600 return EmulateTSTReg(opcode, eEncodingT2);
5601 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
5605 Rd = Bits32(opcode, 15, 12);
5606 Rn = Bits32(opcode, 19, 16);
5607 Rm = Bits32(opcode, 3, 0);
5608 setflags = BitIsSet(opcode, 20);
5609 shift_n = DecodeImmShiftARM(opcode, shift_t);
5611 if (Rd == 15 && setflags)
5612 return EmulateSUBSPcLrEtc (opcode, encoding);
5618 // Read the first operand.
5619 uint32_t val1 = ReadCoreReg(Rn, &success);
5623 // Read the second operand.
5624 uint32_t val2 = ReadCoreReg(Rm, &success);
5628 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
5631 uint32_t result = val1 & shifted;
5633 EmulateInstruction::Context context;
5634 context.type = EmulateInstruction::eContextImmediate;
5635 context.SetNoArgs ();
5637 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
5643 // Bitwise Bit Clear (immediate) performs a bitwise AND of a register value and the complement of an
5644 // immediate value, and writes the result to the destination register. It can optionally update the
5645 // condition flags based on the result.
5647 EmulateInstructionARM::EmulateBICImm (const uint32_t opcode, const ARMEncoding encoding)
5650 // ARM pseudo code...
5651 if ConditionPassed() then
5652 EncodingSpecificOperations();
5653 result = R[n] AND NOT(imm32);
5654 if d == 15 then // Can only occur for ARM encoding
5655 ALUWritePC(result); // setflags is always FALSE here
5659 APSR.N = result<31>;
5660 APSR.Z = IsZeroBit(result);
5665 bool success = false;
5667 if (ConditionPassed(opcode))
5670 uint32_t imm32; // the immediate value to be bitwise inverted and ANDed to the value obtained from Rn
5672 uint32_t carry; // the carry bit after ARM/Thumb Expand operation
5676 Rd = Bits32(opcode, 11, 8);
5677 Rn = Bits32(opcode, 19, 16);
5678 setflags = BitIsSet(opcode, 20);
5679 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
5680 if (BadReg(Rd) || BadReg(Rn))
5684 Rd = Bits32(opcode, 15, 12);
5685 Rn = Bits32(opcode, 19, 16);
5686 setflags = BitIsSet(opcode, 20);
5687 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
5689 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
5690 if (Rd == 15 && setflags)
5691 return EmulateSUBSPcLrEtc (opcode, encoding);
5697 // Read the first operand.
5698 uint32_t val1 = ReadCoreReg(Rn, &success);
5702 uint32_t result = val1 & ~imm32;
5704 EmulateInstruction::Context context;
5705 context.type = EmulateInstruction::eContextImmediate;
5706 context.SetNoArgs ();
5708 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
5714 // Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an
5715 // optionally-shifted register value, and writes the result to the destination register.
5716 // It can optionally update the condition flags based on the result.
5718 EmulateInstructionARM::EmulateBICReg (const uint32_t opcode, const ARMEncoding encoding)
5721 // ARM pseudo code...
5722 if ConditionPassed() then
5723 EncodingSpecificOperations();
5724 (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
5725 result = R[n] AND NOT(shifted);
5726 if d == 15 then // Can only occur for ARM encoding
5727 ALUWritePC(result); // setflags is always FALSE here
5731 APSR.N = result<31>;
5732 APSR.Z = IsZeroBit(result);
5737 bool success = false;
5739 if (ConditionPassed(opcode))
5741 uint32_t Rd, Rn, Rm;
5742 ARM_ShifterType shift_t;
5743 uint32_t shift_n; // the shift applied to the value read from Rm
5749 Rd = Rn = Bits32(opcode, 2, 0);
5750 Rm = Bits32(opcode, 5, 3);
5751 setflags = !InITBlock();
5752 shift_t = SRType_LSL;
5756 Rd = Bits32(opcode, 11, 8);
5757 Rn = Bits32(opcode, 19, 16);
5758 Rm = Bits32(opcode, 3, 0);
5759 setflags = BitIsSet(opcode, 20);
5760 shift_n = DecodeImmShiftThumb(opcode, shift_t);
5761 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5765 Rd = Bits32(opcode, 15, 12);
5766 Rn = Bits32(opcode, 19, 16);
5767 Rm = Bits32(opcode, 3, 0);
5768 setflags = BitIsSet(opcode, 20);
5769 shift_n = DecodeImmShiftARM(opcode, shift_t);
5771 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
5772 if (Rd == 15 && setflags)
5773 return EmulateSUBSPcLrEtc (opcode, encoding);
5779 // Read the first operand.
5780 uint32_t val1 = ReadCoreReg(Rn, &success);
5784 // Read the second operand.
5785 uint32_t val2 = ReadCoreReg(Rm, &success);
5789 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
5792 uint32_t result = val1 & ~shifted;
5794 EmulateInstruction::Context context;
5795 context.type = EmulateInstruction::eContextImmediate;
5796 context.SetNoArgs ();
5798 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
5804 // LDR (immediate, ARM) calculates an address from a base register value and an immediate offset, loads a word
5805 // from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing.
5807 EmulateInstructionARM::EmulateLDRImmediateARM (const uint32_t opcode, const ARMEncoding encoding)
5810 if ConditionPassed() then
5811 EncodingSpecificOperations();
5812 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5813 address = if index then offset_addr else R[n];
5814 data = MemU[address,4];
5815 if wback then R[n] = offset_addr;
5817 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
5818 elsif UnalignedSupport() || address<1:0> = '00' then
5820 else // Can only apply before ARMv7
5821 R[t] = ROR(data, 8*UInt(address<1:0>));
5824 bool success = false;
5826 if (ConditionPassed(opcode))
5828 const uint32_t addr_byte_size = GetAddressByteSize();
5840 // if Rn == '1111' then SEE LDR (literal);
5841 // if P == '0' && W == '1' then SEE LDRT;
5842 // if Rn == '1101' && P == '0' && U == '1' && W == '0' && imm12 == '000000000100' then SEE POP;
5843 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
5844 t = Bits32 (opcode, 15, 12);
5845 n = Bits32 (opcode, 19, 16);
5846 imm32 = Bits32 (opcode, 11, 0);
5848 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
5849 index = BitIsSet (opcode, 24);
5850 add = BitIsSet (opcode, 23);
5851 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
5853 // if wback && n == t then UNPREDICTABLE;
5854 if (wback && (n == t))
5865 addr_t base_address = ReadCoreReg (n, &success);
5869 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5871 offset_addr = base_address + imm32;
5873 offset_addr = base_address - imm32;
5875 // address = if index then offset_addr else R[n];
5877 address = offset_addr;
5879 address = base_address;
5881 // data = MemU[address,4];
5883 RegisterInfo base_reg;
5884 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5886 EmulateInstruction::Context context;
5887 context.type = eContextRegisterLoad;
5888 context.SetRegisterPlusOffset (base_reg, address - base_address);
5890 uint64_t data = MemURead (context, address, addr_byte_size, 0, &success);
5894 // if wback then R[n] = offset_addr;
5897 context.type = eContextAdjustBaseRegister;
5898 context.SetAddress (offset_addr);
5899 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
5906 // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
5907 if (BitIsClear (address, 1) && BitIsClear (address, 0))
5909 // LoadWritePC (data);
5910 context.type = eContextRegisterLoad;
5911 context.SetRegisterPlusOffset (base_reg, address - base_address);
5912 LoadWritePC (context, data);
5917 // elsif UnalignedSupport() || address<1:0> = '00' then
5918 else if (UnalignedSupport() || (BitIsClear (address, 1) && BitIsClear (address, 0)))
5921 context.type = eContextRegisterLoad;
5922 context.SetRegisterPlusOffset (base_reg, address - base_address);
5923 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
5926 // else // Can only apply before ARMv7
5929 // R[t] = ROR(data, 8*UInt(address<1:0>));
5930 data = ROR (data, Bits32 (address, 1, 0), &success);
5933 context.type = eContextRegisterLoad;
5934 context.SetImmediate (data);
5935 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
5943 // LDR (register) calculates an address from a base register value and an offset register value, loads a word
5944 // from memory, and writes it to a resgister. The offset register value can optionally be shifted.
5946 EmulateInstructionARM::EmulateLDRRegister (const uint32_t opcode, const ARMEncoding encoding)
5949 if ConditionPassed() then
5950 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5951 offset = Shift(R[m], shift_t, shift_n, APSR.C);
5952 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5953 address = if index then offset_addr else R[n];
5954 data = MemU[address,4];
5955 if wback then R[n] = offset_addr;
5957 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
5958 elsif UnalignedSupport() || address<1:0> = '00' then
5960 else // Can only apply before ARMv7
5961 if CurrentInstrSet() == InstrSet_ARM then
5962 R[t] = ROR(data, 8*UInt(address<1:0>));
5964 R[t] = bits(32) UNKNOWN;
5967 bool success = false;
5969 if (ConditionPassed(opcode))
5971 const uint32_t addr_byte_size = GetAddressByteSize();
5979 ARM_ShifterType shift_t;
5985 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
5986 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5987 t = Bits32 (opcode, 2, 0);
5988 n = Bits32 (opcode, 5, 3);
5989 m = Bits32 (opcode, 8, 6);
5991 // index = TRUE; add = TRUE; wback = FALSE;
5996 // (shift_t, shift_n) = (SRType_LSL, 0);
5997 shift_t = SRType_LSL;
6003 // if Rn == '1111' then SEE LDR (literal);
6004 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6005 t = Bits32 (opcode, 15, 12);
6006 n = Bits32 (opcode, 19, 16);
6007 m = Bits32 (opcode, 3, 0);
6009 // index = TRUE; add = TRUE; wback = FALSE;
6014 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
6015 shift_t = SRType_LSL;
6016 shift_n = Bits32 (opcode, 5, 4);
6018 // if BadReg(m) then UNPREDICTABLE;
6022 // if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
6023 if ((t == 15) && InITBlock() && !LastInITBlock())
6030 // if P == '0' && W == '1' then SEE LDRT;
6031 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6032 t = Bits32 (opcode, 15, 12);
6033 n = Bits32 (opcode, 19, 16);
6034 m = Bits32 (opcode, 3, 0);
6036 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
6037 index = BitIsSet (opcode, 24);
6038 add = BitIsSet (opcode, 23);
6039 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
6041 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
6042 uint32_t type = Bits32 (opcode, 6, 5);
6043 uint32_t imm5 = Bits32 (opcode, 11, 7);
6044 shift_n = DecodeImmShift (type, imm5, shift_t);
6046 // if m == 15 then UNPREDICTABLE;
6050 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
6051 if (wback && ((n == 15) || (n == t)))
6061 uint32_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
6065 uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6072 // offset = Shift(R[m], shift_t, shift_n, APSR.C); -- Note "The APSR is an application level alias for the CPSR".
6073 addr_t offset = Shift (Rm, shift_t, shift_n, Bit32 (m_opcode_cpsr, APSR_C), &success);
6077 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6079 offset_addr = Rn + offset;
6081 offset_addr = Rn - offset;
6083 // address = if index then offset_addr else R[n];
6085 address = offset_addr;
6089 // data = MemU[address,4];
6090 RegisterInfo base_reg;
6091 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
6093 EmulateInstruction::Context context;
6094 context.type = eContextRegisterLoad;
6095 context.SetRegisterPlusOffset (base_reg, address - Rn);
6097 uint64_t data = MemURead (context, address, addr_byte_size, 0, &success);
6101 // if wback then R[n] = offset_addr;
6104 context.type = eContextAdjustBaseRegister;
6105 context.SetAddress (offset_addr);
6106 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
6113 // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
6114 if (BitIsClear (address, 1) && BitIsClear (address, 0))
6116 context.type = eContextRegisterLoad;
6117 context.SetRegisterPlusOffset (base_reg, address - Rn);
6118 LoadWritePC (context, data);
6123 // elsif UnalignedSupport() || address<1:0> = '00' then
6124 else if (UnalignedSupport () || (BitIsClear (address, 1) && BitIsClear (address, 0)))
6127 context.type = eContextRegisterLoad;
6128 context.SetRegisterPlusOffset (base_reg, address - Rn);
6129 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6132 else // Can only apply before ARMv7
6134 // if CurrentInstrSet() == InstrSet_ARM then
6135 if (CurrentInstrSet () == eModeARM)
6137 // R[t] = ROR(data, 8*UInt(address<1:0>));
6138 data = ROR (data, Bits32 (address, 1, 0), &success);
6141 context.type = eContextRegisterLoad;
6142 context.SetImmediate (data);
6143 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6148 // R[t] = bits(32) UNKNOWN;
6149 WriteBits32Unknown (t);
6156 // LDRB (immediate, Thumb)
6158 EmulateInstructionARM::EmulateLDRBImmediate (const uint32_t opcode, const ARMEncoding encoding)
6161 if ConditionPassed() then
6162 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6163 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6164 address = if index then offset_addr else R[n];
6165 R[t] = ZeroExtend(MemU[address,1], 32);
6166 if wback then R[n] = offset_addr;
6169 bool success = false;
6171 if (ConditionPassed(opcode))
6180 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6184 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
6185 t = Bits32 (opcode, 2, 0);
6186 n = Bits32 (opcode, 5, 3);
6187 imm32 = Bits32 (opcode, 10, 6);
6189 // index = TRUE; add = TRUE; wback = FALSE;
6197 // if Rt == '1111' then SEE PLD;
6198 // if Rn == '1111' then SEE LDRB (literal);
6199 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6200 t = Bits32 (opcode, 15, 12);
6201 n = Bits32 (opcode, 19, 16);
6202 imm32 = Bits32 (opcode, 11, 0);
6204 // index = TRUE; add = TRUE; wback = FALSE;
6209 // if t == 13 then UNPREDICTABLE;
6216 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD;
6217 // if Rn == '1111' then SEE LDRB (literal);
6218 // if P == '1' && U == '1' && W == '0' then SEE LDRBT;
6219 // if P == '0' && W == '0' then UNDEFINED;
6220 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
6223 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
6224 t = Bits32 (opcode, 15, 12);
6225 n = Bits32 (opcode, 19, 16);
6226 imm32 = Bits32 (opcode, 7, 0);
6228 // index = (P == '1'); add = (U == '1'); wback = (W == '1');
6229 index = BitIsSet (opcode, 10);
6230 add = BitIsSet (opcode, 9);
6231 wback = BitIsSet (opcode, 8);
6233 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE;
6234 if (BadReg (t) || (wback && (n == t)))
6243 uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6250 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6252 offset_addr = Rn + imm32;
6254 offset_addr = Rn - imm32;
6256 // address = if index then offset_addr else R[n];
6258 address = offset_addr;
6262 // R[t] = ZeroExtend(MemU[address,1], 32);
6263 RegisterInfo base_reg;
6264 RegisterInfo data_reg;
6265 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
6266 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
6268 EmulateInstruction::Context context;
6269 context.type = eContextRegisterLoad;
6270 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
6272 uint64_t data = MemURead (context, address, 1, 0, &success);
6276 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6279 // if wback then R[n] = offset_addr;
6282 context.type = eContextAdjustBaseRegister;
6283 context.SetAddress (offset_addr);
6284 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
6291 // LDRB (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory,
6292 // zero-extends it to form a 32-bit word and writes it to a register.
6294 EmulateInstructionARM::EmulateLDRBLiteral (const uint32_t opcode, const ARMEncoding encoding)
6297 if ConditionPassed() then
6298 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
6300 address = if add then (base + imm32) else (base - imm32);
6301 R[t] = ZeroExtend(MemU[address,1], 32);
6304 bool success = false;
6306 if (ConditionPassed(opcode))
6314 // if Rt == '1111' then SEE PLD;
6315 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
6316 t = Bits32 (opcode, 15, 12);
6317 imm32 = Bits32 (opcode, 11, 0);
6318 add = BitIsSet (opcode, 23);
6320 // if t == 13 then UNPREDICTABLE;
6327 // t == UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
6328 t = Bits32 (opcode, 15, 12);
6329 imm32 = Bits32 (opcode, 11, 0);
6330 add = BitIsSet (opcode, 23);
6332 // if t == 15 then UNPREDICTABLE;
6341 // base = Align(PC,4);
6342 uint32_t pc_val = ReadCoreReg (PC_REG, &success);
6346 uint32_t base = AlignPC (pc_val);
6349 // address = if add then (base + imm32) else (base - imm32);
6351 address = base + imm32;
6353 address = base - imm32;
6355 // R[t] = ZeroExtend(MemU[address,1], 32);
6356 EmulateInstruction::Context context;
6357 context.type = eContextRelativeBranchImmediate;
6358 context.SetImmediate (address - base);
6360 uint64_t data = MemURead (context, address, 1, 0, &success);
6364 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6370 // LDRB (register) calculates an address from a base register value and an offset rigister value, loads a byte from
6371 // memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can
6372 // optionally be shifted.
6374 EmulateInstructionARM::EmulateLDRBRegister (const uint32_t opcode, const ARMEncoding encoding)
6377 if ConditionPassed() then
6378 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6379 offset = Shift(R[m], shift_t, shift_n, APSR.C);
6380 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6381 address = if index then offset_addr else R[n];
6382 R[t] = ZeroExtend(MemU[address,1],32);
6383 if wback then R[n] = offset_addr;
6386 bool success = false;
6388 if (ConditionPassed(opcode))
6396 ARM_ShifterType shift_t;
6399 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6403 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6404 t = Bits32 (opcode, 2, 0);
6405 n = Bits32 (opcode, 5, 3);
6406 m = Bits32 (opcode, 8, 6);
6408 // index = TRUE; add = TRUE; wback = FALSE;
6413 // (shift_t, shift_n) = (SRType_LSL, 0);
6414 shift_t = SRType_LSL;
6419 // if Rt == '1111' then SEE PLD;
6420 // if Rn == '1111' then SEE LDRB (literal);
6421 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6422 t = Bits32 (opcode, 15, 12);
6423 n = Bits32 (opcode, 19, 16);
6424 m = Bits32 (opcode, 3, 0);
6426 // index = TRUE; add = TRUE; wback = FALSE;
6431 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
6432 shift_t = SRType_LSL;
6433 shift_n = Bits32 (opcode, 5, 4);
6435 // if t == 13 || BadReg(m) then UNPREDICTABLE;
6436 if ((t == 13) || BadReg (m))
6442 // if P == '0' && W == '1' then SEE LDRBT;
6443 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6444 t = Bits32 (opcode, 15, 12);
6445 n = Bits32 (opcode, 19, 16);
6446 m = Bits32 (opcode, 3, 0);
6448 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
6449 index = BitIsSet (opcode, 24);
6450 add = BitIsSet (opcode, 23);
6451 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
6453 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
6454 uint32_t type = Bits32 (opcode, 6, 5);
6455 uint32_t imm5 = Bits32 (opcode, 11, 7);
6456 shift_n = DecodeImmShift (type, imm5, shift_t);
6458 // if t == 15 || m == 15 then UNPREDICTABLE;
6459 if ((t == 15) || (m == 15))
6462 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
6463 if (wback && ((n == 15) || (n == t)))
6475 // offset = Shift(R[m], shift_t, shift_n, APSR.C);
6476 uint32_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
6480 addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
6484 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6485 uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6490 offset_addr = Rn + offset;
6492 offset_addr = Rn - offset;
6494 // address = if index then offset_addr else R[n];
6496 address = offset_addr;
6500 // R[t] = ZeroExtend(MemU[address,1],32);
6501 RegisterInfo base_reg;
6502 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
6504 EmulateInstruction::Context context;
6505 context.type = eContextRegisterLoad;
6506 context.SetRegisterPlusOffset (base_reg, address - Rn);
6508 uint64_t data = MemURead (context, address, 1, 0, &success);
6512 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6515 // if wback then R[n] = offset_addr;
6518 context.type = eContextAdjustBaseRegister;
6519 context.SetAddress (offset_addr);
6520 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
6527 // LDRH (immediate, Thumb) calculates an address from a base register value and an immediate offset, loads a
6528 // halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset,
6529 // post-indexed, or pre-indexed addressing.
6531 EmulateInstructionARM::EmulateLDRHImmediate (const uint32_t opcode, const ARMEncoding encoding)
6534 if ConditionPassed() then
6535 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6536 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6537 address = if index then offset_addr else R[n];
6538 data = MemU[address,2];
6539 if wback then R[n] = offset_addr;
6540 if UnalignedSupport() || address<0> = '0' then
6541 R[t] = ZeroExtend(data, 32);
6542 else // Can only apply before ARMv7
6543 R[t] = bits(32) UNKNOWN;
6547 bool success = false;
6549 if (ConditionPassed(opcode))
6558 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6562 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'0', 32);
6563 t = Bits32 (opcode, 2, 0);
6564 n = Bits32 (opcode, 5, 3);
6565 imm32 = Bits32 (opcode, 10, 6) << 1;
6567 // index = TRUE; add = TRUE; wback = FALSE;
6575 // if Rt == '1111' then SEE "Unallocated memory hints";
6576 // if Rn == '1111' then SEE LDRH (literal);
6577 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6578 t = Bits32 (opcode, 15, 12);
6579 n = Bits32 (opcode, 19, 16);
6580 imm32 = Bits32 (opcode, 11, 0);
6582 // index = TRUE; add = TRUE; wback = FALSE;
6587 // if t == 13 then UNPREDICTABLE;
6593 // if Rn == '1111' then SEE LDRH (literal);
6594 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "Unallocated memory hints";
6595 // if P == '1' && U == '1' && W == '0' then SEE LDRHT;
6596 // if P == '0' && W == '0' then UNDEFINED;
6597 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
6600 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
6601 t = Bits32 (opcode, 15, 12);
6602 n = Bits32 (opcode, 19, 16);
6603 imm32 = Bits32 (opcode, 7, 0);
6605 // index = (P == '1'); add = (U == '1'); wback = (W == '1');
6606 index = BitIsSet (opcode, 10);
6607 add = BitIsSet (opcode, 9);
6608 wback = BitIsSet (opcode, 8);
6610 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE;
6611 if (BadReg (t) || (wback && (n == t)))
6619 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6620 uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6628 offset_addr = Rn + imm32;
6630 offset_addr = Rn - imm32;
6632 // address = if index then offset_addr else R[n];
6634 address = offset_addr;
6638 // data = MemU[address,2];
6639 RegisterInfo base_reg;
6640 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
6642 EmulateInstruction::Context context;
6643 context.type = eContextRegisterLoad;
6644 context.SetRegisterPlusOffset (base_reg, address - Rn);
6646 uint64_t data = MemURead (context, address, 2, 0, &success);
6650 // if wback then R[n] = offset_addr;
6653 context.type = eContextAdjustBaseRegister;
6654 context.SetAddress (offset_addr);
6655 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
6659 // if UnalignedSupport() || address<0> = '0' then
6660 if (UnalignedSupport () || BitIsClear (address, 0))
6662 // R[t] = ZeroExtend(data, 32);
6663 context.type = eContextRegisterLoad;
6664 context.SetRegisterPlusOffset (base_reg, address - Rn);
6665 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6668 else // Can only apply before ARMv7
6670 // R[t] = bits(32) UNKNOWN;
6671 WriteBits32Unknown (t);
6677 // LDRH (literal) caculates an address from the PC value and an immediate offset, loads a halfword from memory,
6678 // zero-extends it to form a 32-bit word, and writes it to a register.
6680 EmulateInstructionARM::EmulateLDRHLiteral (const uint32_t opcode, const ARMEncoding encoding)
6683 if ConditionPassed() then
6684 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
6686 address = if add then (base + imm32) else (base - imm32);
6687 data = MemU[address,2];
6688 if UnalignedSupport() || address<0> = '0' then
6689 R[t] = ZeroExtend(data, 32);
6690 else // Can only apply before ARMv7
6691 R[t] = bits(32) UNKNOWN;
6694 bool success = false;
6696 if (ConditionPassed(opcode))
6702 // EncodingSpecificOperations(); NullCheckIfThumbEE(15);
6706 // if Rt == '1111' then SEE "Unallocated memory hints";
6707 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
6708 t = Bits32 (opcode, 15, 12);
6709 imm32 = Bits32 (opcode, 11, 0);
6710 add = BitIsSet (opcode, 23);
6712 // if t == 13 then UNPREDICTABLE;
6720 uint32_t imm4H = Bits32 (opcode, 11, 8);
6721 uint32_t imm4L = Bits32 (opcode, 3, 0);
6723 // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1');
6724 t = Bits32 (opcode, 15, 12);
6725 imm32 = (imm4H << 4) | imm4L;
6726 add = BitIsSet (opcode, 23);
6728 // if t == 15 then UNPREDICTABLE;
6738 // base = Align(PC,4);
6739 uint64_t pc_value = ReadCoreReg (PC_REG, &success);
6743 addr_t base = AlignPC (pc_value);
6746 // address = if add then (base + imm32) else (base - imm32);
6748 address = base + imm32;
6750 address = base - imm32;
6752 // data = MemU[address,2];
6753 RegisterInfo base_reg;
6754 GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, base_reg);
6756 EmulateInstruction::Context context;
6757 context.type = eContextRegisterLoad;
6758 context.SetRegisterPlusOffset (base_reg, address - base);
6760 uint64_t data = MemURead (context, address, 2, 0, &success);
6765 // if UnalignedSupport() || address<0> = '0' then
6766 if (UnalignedSupport () || BitIsClear (address, 0))
6768 // R[t] = ZeroExtend(data, 32);
6769 context.type = eContextRegisterLoad;
6770 context.SetRegisterPlusOffset (base_reg, address - base);
6771 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6775 else // Can only apply before ARMv7
6777 // R[t] = bits(32) UNKNOWN;
6778 WriteBits32Unknown (t);
6784 // LDRH (literal) calculates an address from a base register value and an offset register value, loads a halfword
6785 // from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can
6786 // be shifted left by 0, 1, 2, or 3 bits.
6788 EmulateInstructionARM::EmulateLDRHRegister (const uint32_t opcode, const ARMEncoding encoding)
6791 if ConditionPassed() then
6792 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6793 offset = Shift(R[m], shift_t, shift_n, APSR.C);
6794 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6795 address = if index then offset_addr else R[n];
6796 data = MemU[address,2];
6797 if wback then R[n] = offset_addr;
6798 if UnalignedSupport() || address<0> = '0' then
6799 R[t] = ZeroExtend(data, 32);
6800 else // Can only apply before ARMv7
6801 R[t] = bits(32) UNKNOWN;
6804 bool success = false;
6806 if (ConditionPassed(opcode))
6814 ARM_ShifterType shift_t;
6817 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6821 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
6822 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6823 t = Bits32 (opcode, 2, 0);
6824 n = Bits32 (opcode, 5, 3);
6825 m = Bits32 (opcode, 8, 6);
6827 // index = TRUE; add = TRUE; wback = FALSE;
6832 // (shift_t, shift_n) = (SRType_LSL, 0);
6833 shift_t = SRType_LSL;
6839 // if Rn == '1111' then SEE LDRH (literal);
6840 // if Rt == '1111' then SEE "Unallocated memory hints";
6841 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6842 t = Bits32 (opcode, 15, 12);
6843 n = Bits32 (opcode, 19, 16);
6844 m = Bits32 (opcode, 3, 0);
6846 // index = TRUE; add = TRUE; wback = FALSE;
6851 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
6852 shift_t = SRType_LSL;
6853 shift_n = Bits32 (opcode, 5, 4);
6855 // if t == 13 || BadReg(m) then UNPREDICTABLE;
6856 if ((t == 13) || BadReg (m))
6861 // if P == '0' && W == '1' then SEE LDRHT;
6862 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6863 t = Bits32 (opcode, 15, 12);
6864 n = Bits32 (opcode, 19, 16);
6865 m = Bits32 (opcode, 3, 0);
6867 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
6868 index = BitIsSet (opcode, 24);
6869 add = BitIsSet (opcode, 23);
6870 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
6872 // (shift_t, shift_n) = (SRType_LSL, 0);
6873 shift_t = SRType_LSL;
6876 // if t == 15 || m == 15 then UNPREDICTABLE;
6877 if ((t == 15) || (m == 15))
6880 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
6881 if (wback && ((n == 15) || (n == t)))
6890 // offset = Shift(R[m], shift_t, shift_n, APSR.C);
6892 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
6896 addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
6903 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6904 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6909 offset_addr = Rn + offset;
6911 offset_addr = Rn - offset;
6913 // address = if index then offset_addr else R[n];
6915 address = offset_addr;
6919 // data = MemU[address,2];
6920 RegisterInfo base_reg;
6921 RegisterInfo offset_reg;
6922 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
6923 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
6925 EmulateInstruction::Context context;
6926 context.type = eContextRegisterLoad;
6927 context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
6928 uint64_t data = MemURead (context, address, 2, 0, &success);
6932 // if wback then R[n] = offset_addr;
6935 context.type = eContextAdjustBaseRegister;
6936 context.SetAddress (offset_addr);
6937 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
6941 // if UnalignedSupport() || address<0> = '0' then
6942 if (UnalignedSupport() || BitIsClear (address, 0))
6944 // R[t] = ZeroExtend(data, 32);
6945 context.type = eContextRegisterLoad;
6946 context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
6947 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6950 else // Can only apply before ARMv7
6952 // R[t] = bits(32) UNKNOWN;
6953 WriteBits32Unknown (t);
6959 // LDRSB (immediate) calculates an address from a base register value and an immediate offset, loads a byte from
6960 // memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed,
6961 // or pre-indexed addressing.
6963 EmulateInstructionARM::EmulateLDRSBImmediate (const uint32_t opcode, const ARMEncoding encoding)
6966 if ConditionPassed() then
6967 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6968 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6969 address = if index then offset_addr else R[n];
6970 R[t] = SignExtend(MemU[address,1], 32);
6971 if wback then R[n] = offset_addr;
6974 bool success = false;
6976 if (ConditionPassed(opcode))
6985 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6989 // if Rt == '1111' then SEE PLI;
6990 // if Rn == '1111' then SEE LDRSB (literal);
6991 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6992 t = Bits32 (opcode, 15, 12);
6993 n = Bits32 (opcode, 19, 16);
6994 imm32 = Bits32 (opcode, 11, 0);
6996 // index = TRUE; add = TRUE; wback = FALSE;
7001 // if t == 13 then UNPREDICTABLE;
7008 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLI;
7009 // if Rn == '1111' then SEE LDRSB (literal);
7010 // if P == '1' && U == '1' && W == '0' then SEE LDRSBT;
7011 // if P == '0' && W == '0' then UNDEFINED;
7012 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
7015 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
7016 t = Bits32 (opcode, 15, 12);
7017 n = Bits32 (opcode, 19, 16);
7018 imm32 = Bits32 (opcode, 7, 0);
7020 // index = (P == '1'); add = (U == '1'); wback = (W == '1');
7021 index = BitIsSet (opcode, 10);
7022 add = BitIsSet (opcode, 9);
7023 wback = BitIsSet (opcode, 8);
7025 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE;
7026 if (((t == 13) || ((t == 15)
7027 && (BitIsClear (opcode, 10) || BitIsSet (opcode, 9) || BitIsSet (opcode, 8))))
7028 || (wback && (n == t)))
7035 // if Rn == '1111' then SEE LDRSB (literal);
7036 // if P == '0' && W == '1' then SEE LDRSBT;
7037 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
7038 t = Bits32 (opcode, 15, 12);
7039 n = Bits32 (opcode, 19, 16);
7041 uint32_t imm4H = Bits32 (opcode, 11, 8);
7042 uint32_t imm4L = Bits32 (opcode, 3, 0);
7043 imm32 = (imm4H << 4) | imm4L;
7045 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
7046 index = BitIsSet (opcode, 24);
7047 add = BitIsSet (opcode, 23);
7048 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
7050 // if t == 15 || (wback && n == t) then UNPREDICTABLE;
7051 if ((t == 15) || (wback && (n == t)))
7061 uint64_t Rn = ReadCoreReg (n, &success);
7068 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
7070 offset_addr = Rn + imm32;
7072 offset_addr = Rn - imm32;
7074 // address = if index then offset_addr else R[n];
7076 address = offset_addr;
7080 // R[t] = SignExtend(MemU[address,1], 32);
7081 RegisterInfo base_reg;
7082 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
7084 EmulateInstruction::Context context;
7085 context.type = eContextRegisterLoad;
7086 context.SetRegisterPlusOffset (base_reg, address - Rn);
7088 uint64_t unsigned_data = MemURead (context, address, 1, 0, &success);
7092 int64_t signed_data = llvm::SignExtend64<8>(unsigned_data);
7093 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data))
7096 // if wback then R[n] = offset_addr;
7099 context.type = eContextAdjustBaseRegister;
7100 context.SetAddress (offset_addr);
7101 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
7109 // LDRSB (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory,
7110 // sign-extends it to form a 32-bit word, and writes tit to a register.
7112 EmulateInstructionARM::EmulateLDRSBLiteral (const uint32_t opcode, const ARMEncoding encoding)
7115 if ConditionPassed() then
7116 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
7118 address = if add then (base + imm32) else (base - imm32);
7119 R[t] = SignExtend(MemU[address,1], 32);
7122 bool success = false;
7124 if (ConditionPassed(opcode))
7130 // EncodingSpecificOperations(); NullCheckIfThumbEE(15);
7134 // if Rt == '1111' then SEE PLI;
7135 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
7136 t = Bits32 (opcode, 15, 12);
7137 imm32 = Bits32 (opcode, 11, 0);
7138 add = BitIsSet (opcode, 23);
7140 // if t == 13 then UNPREDICTABLE;
7148 // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1');
7149 t = Bits32 (opcode, 15, 12);
7150 uint32_t imm4H = Bits32 (opcode, 11, 8);
7151 uint32_t imm4L = Bits32 (opcode, 3, 0);
7152 imm32 = (imm4H << 4) | imm4L;
7153 add = BitIsSet (opcode, 23);
7155 // if t == 15 then UNPREDICTABLE;
7166 // base = Align(PC,4);
7167 uint64_t pc_value = ReadCoreReg (PC_REG, &success);
7170 uint64_t base = AlignPC (pc_value);
7172 // address = if add then (base + imm32) else (base - imm32);
7175 address = base + imm32;
7177 address = base - imm32;
7179 // R[t] = SignExtend(MemU[address,1], 32);
7180 RegisterInfo base_reg;
7181 GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, base_reg);
7183 EmulateInstruction::Context context;
7184 context.type = eContextRegisterLoad;
7185 context.SetRegisterPlusOffset (base_reg, address - base);
7187 uint64_t unsigned_data = MemURead (context, address, 1, 0, &success);
7191 int64_t signed_data = llvm::SignExtend64<8>(unsigned_data);
7192 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data))
7198 // LDRSB (register) calculates an address from a base register value and an offset register value, loadsa byte from
7199 // memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be
7200 // shifted left by 0, 1, 2, or 3 bits.
7202 EmulateInstructionARM::EmulateLDRSBRegister (const uint32_t opcode, const ARMEncoding encoding)
7205 if ConditionPassed() then
7206 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
7207 offset = Shift(R[m], shift_t, shift_n, APSR.C);
7208 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
7209 address = if index then offset_addr else R[n];
7210 R[t] = SignExtend(MemU[address,1], 32);
7211 if wback then R[n] = offset_addr;
7214 bool success = false;
7216 if (ConditionPassed(opcode))
7224 ARM_ShifterType shift_t;
7227 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
7231 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7232 t = Bits32 (opcode, 2, 0);
7233 n = Bits32 (opcode, 5, 3);
7234 m = Bits32 (opcode, 8, 6);
7236 // index = TRUE; add = TRUE; wback = FALSE;
7241 // (shift_t, shift_n) = (SRType_LSL, 0);
7242 shift_t = SRType_LSL;
7248 // if Rt == '1111' then SEE PLI;
7249 // if Rn == '1111' then SEE LDRSB (literal);
7250 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7251 t = Bits32 (opcode, 15, 12);
7252 n = Bits32 (opcode, 19, 16);
7253 m = Bits32 (opcode, 3, 0);
7255 // index = TRUE; add = TRUE; wback = FALSE;
7260 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
7261 shift_t = SRType_LSL;
7262 shift_n = Bits32 (opcode, 5, 4);
7264 // if t == 13 || BadReg(m) then UNPREDICTABLE;
7265 if ((t == 13) || BadReg (m))
7270 // if P == '0' && W == '1' then SEE LDRSBT;
7271 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7272 t = Bits32 (opcode, 15, 12);
7273 n = Bits32 (opcode, 19, 16);
7274 m = Bits32 (opcode, 3, 0);
7276 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
7277 index = BitIsSet (opcode, 24);
7278 add = BitIsSet (opcode, 23);
7279 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
7281 // (shift_t, shift_n) = (SRType_LSL, 0);
7282 shift_t = SRType_LSL;
7285 // if t == 15 || m == 15 then UNPREDICTABLE;
7286 if ((t == 15) || (m == 15))
7289 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
7290 if (wback && ((n == 15) || (n == t)))
7298 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7302 // offset = Shift(R[m], shift_t, shift_n, APSR.C);
7303 addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
7310 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
7311 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
7316 offset_addr = Rn + offset;
7318 offset_addr = Rn - offset;
7320 // address = if index then offset_addr else R[n];
7322 address = offset_addr;
7326 // R[t] = SignExtend(MemU[address,1], 32);
7327 RegisterInfo base_reg;
7328 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
7329 RegisterInfo offset_reg;
7330 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
7332 EmulateInstruction::Context context;
7333 context.type = eContextRegisterLoad;
7334 context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
7336 uint64_t unsigned_data = MemURead (context, address, 1, 0, &success);
7340 int64_t signed_data = llvm::SignExtend64<8>(unsigned_data);
7341 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data))
7344 // if wback then R[n] = offset_addr;
7347 context.type = eContextAdjustBaseRegister;
7348 context.SetAddress (offset_addr);
7349 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
7356 // LDRSH (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from
7357 // memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or
7358 // pre-indexed addressing.
7360 EmulateInstructionARM::EmulateLDRSHImmediate (const uint32_t opcode, const ARMEncoding encoding)
7363 if ConditionPassed() then
7364 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
7365 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
7366 address = if index then offset_addr else R[n];
7367 data = MemU[address,2];
7368 if wback then R[n] = offset_addr;
7369 if UnalignedSupport() || address<0> = '0' then
7370 R[t] = SignExtend(data, 32);
7371 else // Can only apply before ARMv7
7372 R[t] = bits(32) UNKNOWN;
7375 bool success = false;
7377 if (ConditionPassed(opcode))
7386 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
7390 // if Rn == '1111' then SEE LDRSH (literal);
7391 // if Rt == '1111' then SEE "Unallocated memory hints";
7392 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
7393 t = Bits32 (opcode, 15, 12);
7394 n = Bits32 (opcode, 19, 16);
7395 imm32 = Bits32 (opcode, 11, 0);
7397 // index = TRUE; add = TRUE; wback = FALSE;
7402 // if t == 13 then UNPREDICTABLE;
7409 // if Rn == '1111' then SEE LDRSH (literal);
7410 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "Unallocated memory hints";
7411 // if P == '1' && U == '1' && W == '0' then SEE LDRSHT;
7412 // if P == '0' && W == '0' then UNDEFINED;
7413 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
7416 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
7417 t = Bits32 (opcode, 15, 12);
7418 n = Bits32 (opcode, 19, 16);
7419 imm32 = Bits32 (opcode, 7, 0);
7421 // index = (P == '1'); add = (U == '1'); wback = (W == '1');
7422 index = BitIsSet (opcode, 10);
7423 add = BitIsSet (opcode, 9);
7424 wback = BitIsSet (opcode, 8);
7426 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE;
7427 if (BadReg (t) || (wback && (n == t)))
7434 // if Rn == '1111' then SEE LDRSH (literal);
7435 // if P == '0' && W == '1' then SEE LDRSHT;
7436 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
7437 t = Bits32 (opcode, 15, 12);
7438 n = Bits32 (opcode, 19, 16);
7439 uint32_t imm4H = Bits32 (opcode, 11,8);
7440 uint32_t imm4L = Bits32 (opcode, 3, 0);
7441 imm32 = (imm4H << 4) | imm4L;
7443 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
7444 index = BitIsSet (opcode, 24);
7445 add = BitIsSet (opcode, 23);
7446 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
7448 // if t == 15 || (wback && n == t) then UNPREDICTABLE;
7449 if ((t == 15) || (wback && (n == t)))
7459 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
7460 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
7466 offset_addr = Rn + imm32;
7468 offset_addr = Rn - imm32;
7470 // address = if index then offset_addr else R[n];
7473 address = offset_addr;
7477 // data = MemU[address,2];
7478 RegisterInfo base_reg;
7479 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
7481 EmulateInstruction::Context context;
7482 context.type = eContextRegisterLoad;
7483 context.SetRegisterPlusOffset (base_reg, address - Rn);
7485 uint64_t data = MemURead (context, address, 2, 0, &success);
7489 // if wback then R[n] = offset_addr;
7492 context.type = eContextAdjustBaseRegister;
7493 context.SetAddress (offset_addr);
7494 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
7498 // if UnalignedSupport() || address<0> = '0' then
7499 if (UnalignedSupport() || BitIsClear (address, 0))
7501 // R[t] = SignExtend(data, 32);
7502 int64_t signed_data = llvm::SignExtend64<16>(data);
7503 context.type = eContextRegisterLoad;
7504 context.SetRegisterPlusOffset (base_reg, address - Rn);
7505 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data))
7508 else // Can only apply before ARMv7
7510 // R[t] = bits(32) UNKNOWN;
7511 WriteBits32Unknown (t);
7517 // LDRSH (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory,
7518 // sign-extends it to from a 32-bit word, and writes it to a register.
7520 EmulateInstructionARM::EmulateLDRSHLiteral (const uint32_t opcode, const ARMEncoding encoding)
7523 if ConditionPassed() then
7524 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
7526 address = if add then (base + imm32) else (base - imm32);
7527 data = MemU[address,2];
7528 if UnalignedSupport() || address<0> = '0' then
7529 R[t] = SignExtend(data, 32);
7530 else // Can only apply before ARMv7
7531 R[t] = bits(32) UNKNOWN;
7534 bool success = false;
7536 if (ConditionPassed(opcode))
7542 // EncodingSpecificOperations(); NullCheckIfThumbEE(15);
7546 // if Rt == '1111' then SEE "Unallocated memory hints";
7547 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
7548 t = Bits32 (opcode, 15, 12);
7549 imm32 = Bits32 (opcode, 11, 0);
7550 add = BitIsSet (opcode, 23);
7552 // if t == 13 then UNPREDICTABLE;
7560 // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1');
7561 t = Bits32 (opcode, 15, 12);
7562 uint32_t imm4H = Bits32 (opcode, 11, 8);
7563 uint32_t imm4L = Bits32 (opcode, 3, 0);
7564 imm32 = (imm4H << 4) | imm4L;
7565 add = BitIsSet (opcode, 23);
7567 // if t == 15 then UNPREDICTABLE;
7577 // base = Align(PC,4);
7578 uint64_t pc_value = ReadCoreReg (PC_REG, &success);
7582 uint64_t base = AlignPC (pc_value);
7585 // address = if add then (base + imm32) else (base - imm32);
7587 address = base + imm32;
7589 address = base - imm32;
7591 // data = MemU[address,2];
7592 RegisterInfo base_reg;
7593 GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, base_reg);
7595 EmulateInstruction::Context context;
7596 context.type = eContextRegisterLoad;
7597 context.SetRegisterPlusOffset (base_reg, imm32);
7599 uint64_t data = MemURead (context, address, 2, 0, &success);
7603 // if UnalignedSupport() || address<0> = '0' then
7604 if (UnalignedSupport() || BitIsClear (address, 0))
7606 // R[t] = SignExtend(data, 32);
7607 int64_t signed_data = llvm::SignExtend64<16>(data);
7608 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data))
7611 else // Can only apply before ARMv7
7613 // R[t] = bits(32) UNKNOWN;
7614 WriteBits32Unknown (t);
7620 // LDRSH (register) calculates an address from a base register value and an offset register value, loads a halfword
7621 // from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be
7622 // shifted left by 0, 1, 2, or 3 bits.
7624 EmulateInstructionARM::EmulateLDRSHRegister (const uint32_t opcode, const ARMEncoding encoding)
7627 if ConditionPassed() then
7628 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
7629 offset = Shift(R[m], shift_t, shift_n, APSR.C);
7630 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
7631 address = if index then offset_addr else R[n];
7632 data = MemU[address,2];
7633 if wback then R[n] = offset_addr;
7634 if UnalignedSupport() || address<0> = '0' then
7635 R[t] = SignExtend(data, 32);
7636 else // Can only apply before ARMv7
7637 R[t] = bits(32) UNKNOWN;
7640 bool success = false;
7642 if (ConditionPassed(opcode))
7650 ARM_ShifterType shift_t;
7653 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
7657 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
7658 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7659 t = Bits32 (opcode, 2, 0);
7660 n = Bits32 (opcode, 5, 3);
7661 m = Bits32 (opcode, 8, 6);
7663 // index = TRUE; add = TRUE; wback = FALSE;
7668 // (shift_t, shift_n) = (SRType_LSL, 0);
7669 shift_t = SRType_LSL;
7675 // if Rn == '1111' then SEE LDRSH (literal);
7676 // if Rt == '1111' then SEE "Unallocated memory hints";
7677 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7678 t = Bits32 (opcode, 15, 12);
7679 n = Bits32 (opcode, 19, 16);
7680 m = Bits32 (opcode, 3, 0);
7682 // index = TRUE; add = TRUE; wback = FALSE;
7687 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
7688 shift_t = SRType_LSL;
7689 shift_n = Bits32 (opcode, 5, 4);
7691 // if t == 13 || BadReg(m) then UNPREDICTABLE;
7692 if ((t == 13) || BadReg (m))
7698 // if P == '0' && W == '1' then SEE LDRSHT;
7699 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7700 t = Bits32 (opcode, 15, 12);
7701 n = Bits32 (opcode, 19, 16);
7702 m = Bits32 (opcode, 3, 0);
7704 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
7705 index = BitIsSet (opcode, 24);
7706 add = BitIsSet (opcode, 23);
7707 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
7709 // (shift_t, shift_n) = (SRType_LSL, 0);
7710 shift_t = SRType_LSL;
7713 // if t == 15 || m == 15 then UNPREDICTABLE;
7714 if ((t == 15) || (m == 15))
7717 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
7718 if (wback && ((n == 15) || (n == t)))
7727 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7731 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
7735 // offset = Shift(R[m], shift_t, shift_n, APSR.C);
7736 addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
7743 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
7745 offset_addr = Rn + offset;
7747 offset_addr = Rn - offset;
7749 // address = if index then offset_addr else R[n];
7751 address = offset_addr;
7755 // data = MemU[address,2];
7756 RegisterInfo base_reg;
7757 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
7759 RegisterInfo offset_reg;
7760 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
7762 EmulateInstruction::Context context;
7763 context.type = eContextRegisterLoad;
7764 context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
7766 uint64_t data = MemURead (context, address, 2, 0, &success);
7770 // if wback then R[n] = offset_addr;
7773 context.type = eContextAdjustBaseRegister;
7774 context.SetAddress (offset_addr);
7775 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
7779 // if UnalignedSupport() || address<0> = '0' then
7780 if (UnalignedSupport() || BitIsClear (address, 0))
7782 // R[t] = SignExtend(data, 32);
7783 context.type = eContextRegisterLoad;
7784 context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
7786 int64_t signed_data = llvm::SignExtend64<16>(data);
7787 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data))
7790 else // Can only apply before ARMv7
7792 // R[t] = bits(32) UNKNOWN;
7793 WriteBits32Unknown (t);
7799 // SXTB extracts an 8-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination
7800 // register. You can specifiy a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.
7802 EmulateInstructionARM::EmulateSXTB (const uint32_t opcode, const ARMEncoding encoding)
7805 if ConditionPassed() then
7806 EncodingSpecificOperations();
7807 rotated = ROR(R[m], rotation);
7808 R[d] = SignExtend(rotated<7:0>, 32);
7811 bool success = false;
7813 if (ConditionPassed(opcode))
7819 // EncodingSpecificOperations();
7823 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
7824 d = Bits32 (opcode, 2, 0);
7825 m = Bits32 (opcode, 5, 3);
7831 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7832 d = Bits32 (opcode, 11, 8);
7833 m = Bits32 (opcode, 3, 0);
7834 rotation = Bits32 (opcode, 5, 4) << 3;
7836 // if BadReg(d) || BadReg(m) then UNPREDICTABLE;
7837 if (BadReg (d) || BadReg (m))
7843 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7844 d = Bits32 (opcode, 15, 12);
7845 m = Bits32 (opcode, 3, 0);
7846 rotation = Bits32 (opcode, 11, 10) << 3;
7848 // if d == 15 || m == 15 then UNPREDICTABLE;
7849 if ((d == 15) || (m == 15))
7858 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7862 // rotated = ROR(R[m], rotation);
7863 uint64_t rotated = ROR (Rm, rotation, &success);
7867 // R[d] = SignExtend(rotated<7:0>, 32);
7868 int64_t data = llvm::SignExtend64<8>(rotated);
7870 RegisterInfo source_reg;
7871 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, source_reg);
7873 EmulateInstruction::Context context;
7874 context.type = eContextRegisterLoad;
7875 context.SetRegister (source_reg);
7877 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, (uint64_t) data))
7883 // SXTH extracts a 16-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination
7884 // register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.
7886 EmulateInstructionARM::EmulateSXTH (const uint32_t opcode, const ARMEncoding encoding)
7889 if ConditionPassed() then
7890 EncodingSpecificOperations();
7891 rotated = ROR(R[m], rotation);
7892 R[d] = SignExtend(rotated<15:0>, 32);
7895 bool success = false;
7897 if (ConditionPassed(opcode))
7903 // EncodingSpecificOperations();
7907 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
7908 d = Bits32 (opcode, 2, 0);
7909 m = Bits32 (opcode, 5, 3);
7915 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7916 d = Bits32 (opcode, 11, 8);
7917 m = Bits32 (opcode, 3, 0);
7918 rotation = Bits32 (opcode, 5, 4) << 3;
7920 // if BadReg(d) || BadReg(m) then UNPREDICTABLE;
7921 if (BadReg (d) || BadReg (m))
7927 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7928 d = Bits32 (opcode, 15, 12);
7929 m = Bits32 (opcode, 3, 0);
7930 rotation = Bits32 (opcode, 11, 10) << 3;
7932 // if d == 15 || m == 15 then UNPREDICTABLE;
7933 if ((d == 15) || (m == 15))
7942 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7946 // rotated = ROR(R[m], rotation);
7947 uint64_t rotated = ROR (Rm, rotation, &success);
7951 // R[d] = SignExtend(rotated<15:0>, 32);
7952 RegisterInfo source_reg;
7953 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, source_reg);
7955 EmulateInstruction::Context context;
7956 context.type = eContextRegisterLoad;
7957 context.SetRegister (source_reg);
7959 int64_t data = llvm::SignExtend64<16> (rotated);
7960 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, (uint64_t) data))
7967 // UXTB extracts an 8-bit value from a register, zero-extneds it to 32 bits, and writes the result to the destination
7968 // register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.
7970 EmulateInstructionARM::EmulateUXTB (const uint32_t opcode, const ARMEncoding encoding)
7973 if ConditionPassed() then
7974 EncodingSpecificOperations();
7975 rotated = ROR(R[m], rotation);
7976 R[d] = ZeroExtend(rotated<7:0>, 32);
7979 bool success = false;
7981 if (ConditionPassed(opcode))
7987 // EncodingSpecificOperations();
7991 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
7992 d = Bits32 (opcode, 2, 0);
7993 m = Bits32 (opcode, 5, 3);
7999 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8000 d = Bits32 (opcode, 11, 8);
8001 m = Bits32 (opcode, 3, 0);
8002 rotation = Bits32 (opcode, 5, 4) << 3;
8004 // if BadReg(d) || BadReg(m) then UNPREDICTABLE;
8005 if (BadReg (d) || BadReg (m))
8011 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8012 d = Bits32 (opcode, 15, 12);
8013 m = Bits32 (opcode, 3, 0);
8014 rotation = Bits32 (opcode, 11, 10) << 3;
8016 // if d == 15 || m == 15 then UNPREDICTABLE;
8017 if ((d == 15) || (m == 15))
8026 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
8030 // rotated = ROR(R[m], rotation);
8031 uint64_t rotated = ROR (Rm, rotation, &success);
8035 // R[d] = ZeroExtend(rotated<7:0>, 32);
8036 RegisterInfo source_reg;
8037 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, source_reg);
8039 EmulateInstruction::Context context;
8040 context.type = eContextRegisterLoad;
8041 context.SetRegister (source_reg);
8043 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, Bits32 (rotated, 7, 0)))
8049 // UXTH extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination
8050 // register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.
8052 EmulateInstructionARM::EmulateUXTH (const uint32_t opcode, const ARMEncoding encoding)
8055 if ConditionPassed() then
8056 EncodingSpecificOperations();
8057 rotated = ROR(R[m], rotation);
8058 R[d] = ZeroExtend(rotated<15:0>, 32);
8061 bool success = false;
8063 if (ConditionPassed(opcode))
8072 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8073 d = Bits32 (opcode, 2, 0);
8074 m = Bits32 (opcode, 5, 3);
8080 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8081 d = Bits32 (opcode, 11, 8);
8082 m = Bits32 (opcode, 3, 0);
8083 rotation = Bits32 (opcode, 5, 4) << 3;
8085 // if BadReg(d) || BadReg(m) then UNPREDICTABLE;
8086 if (BadReg (d) || BadReg (m))
8092 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8093 d = Bits32 (opcode, 15, 12);
8094 m = Bits32 (opcode, 3, 0);
8095 rotation = Bits32 (opcode, 11, 10) << 3;
8097 // if d == 15 || m == 15 then UNPREDICTABLE;
8098 if ((d == 15) || (m == 15))
8107 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
8111 // rotated = ROR(R[m], rotation);
8112 uint64_t rotated = ROR (Rm, rotation, &success);
8116 // R[d] = ZeroExtend(rotated<15:0>, 32);
8117 RegisterInfo source_reg;
8118 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, source_reg);
8120 EmulateInstruction::Context context;
8121 context.type = eContextRegisterLoad;
8122 context.SetRegister (source_reg);
8124 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, Bits32 (rotated, 15, 0)))
8130 // RFE (Return From Exception) loads the PC and the CPSR from the word at the specified address and the following
8131 // word respectively.
8133 EmulateInstructionARM::EmulateRFE (const uint32_t opcode, const ARMEncoding encoding)
8136 if ConditionPassed() then
8137 EncodingSpecificOperations();
8138 if !CurrentModeIsPrivileged() || CurrentInstrSet() == InstrSet_ThumbEE then
8141 address = if increment then R[n] else R[n]-8;
8142 if wordhigher then address = address+4;
8143 CPSRWriteByInstr(MemA[address+4,4], '1111', TRUE);
8144 BranchWritePC(MemA[address,4]);
8145 if wback then R[n] = if increment then R[n]+8 else R[n]-8;
8148 bool success = false;
8150 if (ConditionPassed(opcode))
8157 // EncodingSpecificOperations();
8161 // n = UInt(Rn); wback = (W == '1'); increment = FALSE; wordhigher = FALSE;
8162 n = Bits32 (opcode, 19, 16);
8163 wback = BitIsSet (opcode, 21);
8167 // if n == 15 then UNPREDICTABLE;
8171 // if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
8172 if (InITBlock() && !LastInITBlock())
8178 // n = UInt(Rn); wback = (W == '1'); increment = TRUE; wordhigher = FALSE;
8179 n = Bits32 (opcode, 19, 16);
8180 wback = BitIsSet (opcode, 21);
8184 // if n == 15 then UNPREDICTABLE;
8188 // if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
8189 if (InITBlock() && !LastInITBlock())
8196 n = Bits32 (opcode, 19, 16);
8198 // wback = (W == '1'); inc = (U == '1'); wordhigher = (P == U);
8199 wback = BitIsSet (opcode, 21);
8200 increment = BitIsSet (opcode, 23);
8201 wordhigher = (Bit32 (opcode, 24) == Bit32 (opcode, 23));
8203 // if n == 15 then UNPREDICTABLE;
8213 // if !CurrentModeIsPrivileged() || CurrentInstrSet() == InstrSet_ThumbEE then
8214 if (!CurrentModeIsPrivileged ())
8219 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
8224 // address = if increment then R[n] else R[n]-8;
8230 // if wordhigher then address = address+4;
8232 address = address + 4;
8234 // CPSRWriteByInstr(MemA[address+4,4], '1111', TRUE);
8235 RegisterInfo base_reg;
8236 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
8238 EmulateInstruction::Context context;
8239 context.type = eContextReturnFromException;
8240 context.SetRegisterPlusOffset (base_reg, address - Rn);
8242 uint64_t data = MemARead (context, address + 4, 4, 0, &success);
8246 CPSRWriteByInstr (data, 15, true);
8248 // BranchWritePC(MemA[address,4]);
8249 uint64_t data2 = MemARead (context, address, 4, 0, &success);
8253 BranchWritePC (context, data2);
8255 // if wback then R[n] = if increment then R[n]+8 else R[n]-8;
8258 context.type = eContextAdjustBaseRegister;
8261 context.SetOffset (8);
8262 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn + 8))
8267 context.SetOffset (-8);
8268 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn - 8))
8273 } // if ConditionPassed()
8277 // Bitwise Exclusive OR (immediate) performs a bitwise exclusive OR of a register value and an immediate value,
8278 // and writes the result to the destination register. It can optionally update the condition flags based on
8281 EmulateInstructionARM::EmulateEORImm (const uint32_t opcode, const ARMEncoding encoding)
8284 // ARM pseudo code...
8285 if ConditionPassed() then
8286 EncodingSpecificOperations();
8287 result = R[n] EOR imm32;
8288 if d == 15 then // Can only occur for ARM encoding
8289 ALUWritePC(result); // setflags is always FALSE here
8293 APSR.N = result<31>;
8294 APSR.Z = IsZeroBit(result);
8299 bool success = false;
8301 if (ConditionPassed(opcode))
8304 uint32_t imm32; // the immediate value to be ORed to the value obtained from Rn
8306 uint32_t carry; // the carry bit after ARM/Thumb Expand operation
8310 Rd = Bits32(opcode, 11, 8);
8311 Rn = Bits32(opcode, 19, 16);
8312 setflags = BitIsSet(opcode, 20);
8313 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
8314 // if Rd == '1111' && S == '1' then SEE TEQ (immediate);
8315 if (Rd == 15 && setflags)
8316 return EmulateTEQImm (opcode, eEncodingT1);
8317 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
8321 Rd = Bits32(opcode, 15, 12);
8322 Rn = Bits32(opcode, 19, 16);
8323 setflags = BitIsSet(opcode, 20);
8324 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
8326 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8327 if (Rd == 15 && setflags)
8328 return EmulateSUBSPcLrEtc (opcode, encoding);
8334 // Read the first operand.
8335 uint32_t val1 = ReadCoreReg(Rn, &success);
8339 uint32_t result = val1 ^ imm32;
8341 EmulateInstruction::Context context;
8342 context.type = EmulateInstruction::eContextImmediate;
8343 context.SetNoArgs ();
8345 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8351 // Bitwise Exclusive OR (register) performs a bitwise exclusive OR of a register value and an
8352 // optionally-shifted register value, and writes the result to the destination register.
8353 // It can optionally update the condition flags based on the result.
8355 EmulateInstructionARM::EmulateEORReg (const uint32_t opcode, const ARMEncoding encoding)
8358 // ARM pseudo code...
8359 if ConditionPassed() then
8360 EncodingSpecificOperations();
8361 (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
8362 result = R[n] EOR shifted;
8363 if d == 15 then // Can only occur for ARM encoding
8364 ALUWritePC(result); // setflags is always FALSE here
8368 APSR.N = result<31>;
8369 APSR.Z = IsZeroBit(result);
8374 bool success = false;
8376 if (ConditionPassed(opcode))
8378 uint32_t Rd, Rn, Rm;
8379 ARM_ShifterType shift_t;
8380 uint32_t shift_n; // the shift applied to the value read from Rm
8386 Rd = Rn = Bits32(opcode, 2, 0);
8387 Rm = Bits32(opcode, 5, 3);
8388 setflags = !InITBlock();
8389 shift_t = SRType_LSL;
8393 Rd = Bits32(opcode, 11, 8);
8394 Rn = Bits32(opcode, 19, 16);
8395 Rm = Bits32(opcode, 3, 0);
8396 setflags = BitIsSet(opcode, 20);
8397 shift_n = DecodeImmShiftThumb(opcode, shift_t);
8398 // if Rd == '1111' && S == '1' then SEE TEQ (register);
8399 if (Rd == 15 && setflags)
8400 return EmulateTEQReg (opcode, eEncodingT1);
8401 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
8405 Rd = Bits32(opcode, 15, 12);
8406 Rn = Bits32(opcode, 19, 16);
8407 Rm = Bits32(opcode, 3, 0);
8408 setflags = BitIsSet(opcode, 20);
8409 shift_n = DecodeImmShiftARM(opcode, shift_t);
8411 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8412 if (Rd == 15 && setflags)
8413 return EmulateSUBSPcLrEtc (opcode, encoding);
8419 // Read the first operand.
8420 uint32_t val1 = ReadCoreReg(Rn, &success);
8424 // Read the second operand.
8425 uint32_t val2 = ReadCoreReg(Rm, &success);
8429 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
8432 uint32_t result = val1 ^ shifted;
8434 EmulateInstruction::Context context;
8435 context.type = EmulateInstruction::eContextImmediate;
8436 context.SetNoArgs ();
8438 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8444 // Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and
8445 // writes the result to the destination register. It can optionally update the condition flags based
8448 EmulateInstructionARM::EmulateORRImm (const uint32_t opcode, const ARMEncoding encoding)
8451 // ARM pseudo code...
8452 if ConditionPassed() then
8453 EncodingSpecificOperations();
8454 result = R[n] OR imm32;
8455 if d == 15 then // Can only occur for ARM encoding
8456 ALUWritePC(result); // setflags is always FALSE here
8460 APSR.N = result<31>;
8461 APSR.Z = IsZeroBit(result);
8466 bool success = false;
8468 if (ConditionPassed(opcode))
8471 uint32_t imm32; // the immediate value to be ORed to the value obtained from Rn
8473 uint32_t carry; // the carry bit after ARM/Thumb Expand operation
8477 Rd = Bits32(opcode, 11, 8);
8478 Rn = Bits32(opcode, 19, 16);
8479 setflags = BitIsSet(opcode, 20);
8480 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
8481 // if Rn == '1111' then SEE MOV (immediate);
8483 return EmulateMOVRdImm (opcode, eEncodingT2);
8484 if (BadReg(Rd) || Rn == 13)
8488 Rd = Bits32(opcode, 15, 12);
8489 Rn = Bits32(opcode, 19, 16);
8490 setflags = BitIsSet(opcode, 20);
8491 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
8493 if (Rd == 15 && setflags)
8494 return EmulateSUBSPcLrEtc (opcode, encoding);
8500 // Read the first operand.
8501 uint32_t val1 = ReadCoreReg(Rn, &success);
8505 uint32_t result = val1 | imm32;
8507 EmulateInstruction::Context context;
8508 context.type = EmulateInstruction::eContextImmediate;
8509 context.SetNoArgs ();
8511 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8517 // Bitwise OR (register) performs a bitwise (inclusive) OR of a register value and an optionally-shifted register
8518 // value, and writes the result to the destination register. It can optionally update the condition flags based
8521 EmulateInstructionARM::EmulateORRReg (const uint32_t opcode, const ARMEncoding encoding)
8524 // ARM pseudo code...
8525 if ConditionPassed() then
8526 EncodingSpecificOperations();
8527 (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
8528 result = R[n] OR shifted;
8529 if d == 15 then // Can only occur for ARM encoding
8530 ALUWritePC(result); // setflags is always FALSE here
8534 APSR.N = result<31>;
8535 APSR.Z = IsZeroBit(result);
8540 bool success = false;
8542 if (ConditionPassed(opcode))
8544 uint32_t Rd, Rn, Rm;
8545 ARM_ShifterType shift_t;
8546 uint32_t shift_n; // the shift applied to the value read from Rm
8552 Rd = Rn = Bits32(opcode, 2, 0);
8553 Rm = Bits32(opcode, 5, 3);
8554 setflags = !InITBlock();
8555 shift_t = SRType_LSL;
8559 Rd = Bits32(opcode, 11, 8);
8560 Rn = Bits32(opcode, 19, 16);
8561 Rm = Bits32(opcode, 3, 0);
8562 setflags = BitIsSet(opcode, 20);
8563 shift_n = DecodeImmShiftThumb(opcode, shift_t);
8564 // if Rn == '1111' then SEE MOV (register);
8566 return EmulateMOVRdRm (opcode, eEncodingT3);
8567 if (BadReg(Rd) || Rn == 13 || BadReg(Rm))
8571 Rd = Bits32(opcode, 15, 12);
8572 Rn = Bits32(opcode, 19, 16);
8573 Rm = Bits32(opcode, 3, 0);
8574 setflags = BitIsSet(opcode, 20);
8575 shift_n = DecodeImmShiftARM(opcode, shift_t);
8577 if (Rd == 15 && setflags)
8578 return EmulateSUBSPcLrEtc (opcode, encoding);
8584 // Read the first operand.
8585 uint32_t val1 = ReadCoreReg(Rn, &success);
8589 // Read the second operand.
8590 uint32_t val2 = ReadCoreReg(Rm, &success);
8594 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
8597 uint32_t result = val1 | shifted;
8599 EmulateInstruction::Context context;
8600 context.type = EmulateInstruction::eContextImmediate;
8601 context.SetNoArgs ();
8603 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8609 // Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to
8610 // the destination register. It can optionally update the condition flags based on the result.
8612 EmulateInstructionARM::EmulateRSBImm (const uint32_t opcode, const ARMEncoding encoding)
8615 // ARM pseudo code...
8616 if ConditionPassed() then
8617 EncodingSpecificOperations();
8618 (result, carry, overflow) = AddWithCarry(NOT(R[n]), imm32, '1');
8619 if d == 15 then // Can only occur for ARM encoding
8620 ALUWritePC(result); // setflags is always FALSE here
8624 APSR.N = result<31>;
8625 APSR.Z = IsZeroBit(result);
8630 bool success = false;
8632 uint32_t Rd; // the destination register
8633 uint32_t Rn; // the first operand
8635 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
8638 Rd = Bits32(opcode, 2, 0);
8639 Rn = Bits32(opcode, 5, 3);
8640 setflags = !InITBlock();
8644 Rd = Bits32(opcode, 11, 8);
8645 Rn = Bits32(opcode, 19, 16);
8646 setflags = BitIsSet(opcode, 20);
8647 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
8648 if (BadReg(Rd) || BadReg(Rn))
8652 Rd = Bits32(opcode, 15, 12);
8653 Rn = Bits32(opcode, 19, 16);
8654 setflags = BitIsSet(opcode, 20);
8655 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
8657 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8658 if (Rd == 15 && setflags)
8659 return EmulateSUBSPcLrEtc (opcode, encoding);
8664 // Read the register value from the operand register Rn.
8665 uint32_t reg_val = ReadCoreReg(Rn, &success);
8669 AddWithCarryResult res = AddWithCarry(~reg_val, imm32, 1);
8671 EmulateInstruction::Context context;
8672 context.type = EmulateInstruction::eContextImmediate;
8673 context.SetNoArgs ();
8675 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8681 // Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the
8682 // result to the destination register. It can optionally update the condition flags based on the result.
8684 EmulateInstructionARM::EmulateRSBReg (const uint32_t opcode, const ARMEncoding encoding)
8687 // ARM pseudo code...
8688 if ConditionPassed() then
8689 EncodingSpecificOperations();
8690 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
8691 (result, carry, overflow) = AddWithCarry(NOT(R[n]), shifted, '1');
8692 if d == 15 then // Can only occur for ARM encoding
8693 ALUWritePC(result); // setflags is always FALSE here
8697 APSR.N = result<31>;
8698 APSR.Z = IsZeroBit(result);
8703 bool success = false;
8705 uint32_t Rd; // the destination register
8706 uint32_t Rn; // the first operand
8707 uint32_t Rm; // the second operand
8709 ARM_ShifterType shift_t;
8710 uint32_t shift_n; // the shift applied to the value read from Rm
8713 Rd = Bits32(opcode, 11, 8);
8714 Rn = Bits32(opcode, 19, 16);
8715 Rm = Bits32(opcode, 3, 0);
8716 setflags = BitIsSet(opcode, 20);
8717 shift_n = DecodeImmShiftThumb(opcode, shift_t);
8718 // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
8719 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
8723 Rd = Bits32(opcode, 15, 12);
8724 Rn = Bits32(opcode, 19, 16);
8725 Rm = Bits32(opcode, 3, 0);
8726 setflags = BitIsSet(opcode, 20);
8727 shift_n = DecodeImmShiftARM(opcode, shift_t);
8729 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8730 if (Rd == 15 && setflags)
8731 return EmulateSUBSPcLrEtc (opcode, encoding);
8736 // Read the register value from register Rn.
8737 uint32_t val1 = ReadCoreReg(Rn, &success);
8741 // Read the register value from register Rm.
8742 uint32_t val2 = ReadCoreReg(Rm, &success);
8746 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
8749 AddWithCarryResult res = AddWithCarry(~val1, shifted, 1);
8751 EmulateInstruction::Context context;
8752 context.type = EmulateInstruction::eContextImmediate;
8753 context.SetNoArgs();
8754 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8760 // Reverse Subtract with Carry (immediate) subtracts a register value and the value of NOT (Carry flag) from
8761 // an immediate value, and writes the result to the destination register. It can optionally update the condition
8762 // flags based on the result.
8764 EmulateInstructionARM::EmulateRSCImm (const uint32_t opcode, const ARMEncoding encoding)
8767 // ARM pseudo code...
8768 if ConditionPassed() then
8769 EncodingSpecificOperations();
8770 (result, carry, overflow) = AddWithCarry(NOT(R[n]), imm32, APSR.C);
8772 ALUWritePC(result); // setflags is always FALSE here
8776 APSR.N = result<31>;
8777 APSR.Z = IsZeroBit(result);
8782 bool success = false;
8784 uint32_t Rd; // the destination register
8785 uint32_t Rn; // the first operand
8787 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
8790 Rd = Bits32(opcode, 15, 12);
8791 Rn = Bits32(opcode, 19, 16);
8792 setflags = BitIsSet(opcode, 20);
8793 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
8795 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8796 if (Rd == 15 && setflags)
8797 return EmulateSUBSPcLrEtc (opcode, encoding);
8802 // Read the register value from the operand register Rn.
8803 uint32_t reg_val = ReadCoreReg(Rn, &success);
8807 AddWithCarryResult res = AddWithCarry(~reg_val, imm32, APSR_C);
8809 EmulateInstruction::Context context;
8810 context.type = EmulateInstruction::eContextImmediate;
8811 context.SetNoArgs ();
8813 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8819 // Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an
8820 // optionally-shifted register value, and writes the result to the destination register. It can optionally update the
8821 // condition flags based on the result.
8823 EmulateInstructionARM::EmulateRSCReg (const uint32_t opcode, const ARMEncoding encoding)
8826 // ARM pseudo code...
8827 if ConditionPassed() then
8828 EncodingSpecificOperations();
8829 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
8830 (result, carry, overflow) = AddWithCarry(NOT(R[n]), shifted, APSR.C);
8832 ALUWritePC(result); // setflags is always FALSE here
8836 APSR.N = result<31>;
8837 APSR.Z = IsZeroBit(result);
8842 bool success = false;
8844 uint32_t Rd; // the destination register
8845 uint32_t Rn; // the first operand
8846 uint32_t Rm; // the second operand
8848 ARM_ShifterType shift_t;
8849 uint32_t shift_n; // the shift applied to the value read from Rm
8852 Rd = Bits32(opcode, 15, 12);
8853 Rn = Bits32(opcode, 19, 16);
8854 Rm = Bits32(opcode, 3, 0);
8855 setflags = BitIsSet(opcode, 20);
8856 shift_n = DecodeImmShiftARM(opcode, shift_t);
8858 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8859 if (Rd == 15 && setflags)
8860 return EmulateSUBSPcLrEtc (opcode, encoding);
8865 // Read the register value from register Rn.
8866 uint32_t val1 = ReadCoreReg(Rn, &success);
8870 // Read the register value from register Rm.
8871 uint32_t val2 = ReadCoreReg(Rm, &success);
8875 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
8878 AddWithCarryResult res = AddWithCarry(~val1, shifted, APSR_C);
8880 EmulateInstruction::Context context;
8881 context.type = EmulateInstruction::eContextImmediate;
8882 context.SetNoArgs();
8883 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8889 // Subtract with Carry (immediate) subtracts an immediate value and the value of
8890 // NOT (Carry flag) from a register value, and writes the result to the destination register.
8891 // It can optionally update the condition flags based on the result.
8893 EmulateInstructionARM::EmulateSBCImm (const uint32_t opcode, const ARMEncoding encoding)
8896 // ARM pseudo code...
8897 if ConditionPassed() then
8898 EncodingSpecificOperations();
8899 (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), APSR.C);
8900 if d == 15 then // Can only occur for ARM encoding
8901 ALUWritePC(result); // setflags is always FALSE here
8905 APSR.N = result<31>;
8906 APSR.Z = IsZeroBit(result);
8911 bool success = false;
8913 uint32_t Rd; // the destination register
8914 uint32_t Rn; // the first operand
8916 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
8919 Rd = Bits32(opcode, 11, 8);
8920 Rn = Bits32(opcode, 19, 16);
8921 setflags = BitIsSet(opcode, 20);
8922 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
8923 if (BadReg(Rd) || BadReg(Rn))
8927 Rd = Bits32(opcode, 15, 12);
8928 Rn = Bits32(opcode, 19, 16);
8929 setflags = BitIsSet(opcode, 20);
8930 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
8932 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8933 if (Rd == 15 && setflags)
8934 return EmulateSUBSPcLrEtc (opcode, encoding);
8939 // Read the register value from the operand register Rn.
8940 uint32_t reg_val = ReadCoreReg(Rn, &success);
8944 AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, APSR_C);
8946 EmulateInstruction::Context context;
8947 context.type = EmulateInstruction::eContextImmediate;
8948 context.SetNoArgs ();
8950 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8956 // Subtract with Carry (register) subtracts an optionally-shifted register value and the value of
8957 // NOT (Carry flag) from a register value, and writes the result to the destination register.
8958 // It can optionally update the condition flags based on the result.
8960 EmulateInstructionARM::EmulateSBCReg (const uint32_t opcode, const ARMEncoding encoding)
8963 // ARM pseudo code...
8964 if ConditionPassed() then
8965 EncodingSpecificOperations();
8966 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
8967 (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), APSR.C);
8968 if d == 15 then // Can only occur for ARM encoding
8969 ALUWritePC(result); // setflags is always FALSE here
8973 APSR.N = result<31>;
8974 APSR.Z = IsZeroBit(result);
8979 bool success = false;
8981 uint32_t Rd; // the destination register
8982 uint32_t Rn; // the first operand
8983 uint32_t Rm; // the second operand
8985 ARM_ShifterType shift_t;
8986 uint32_t shift_n; // the shift applied to the value read from Rm
8989 Rd = Rn = Bits32(opcode, 2, 0);
8990 Rm = Bits32(opcode, 5, 3);
8991 setflags = !InITBlock();
8992 shift_t = SRType_LSL;
8996 Rd = Bits32(opcode, 11, 8);
8997 Rn = Bits32(opcode, 19, 16);
8998 Rm = Bits32(opcode, 3, 0);
8999 setflags = BitIsSet(opcode, 20);
9000 shift_n = DecodeImmShiftThumb(opcode, shift_t);
9001 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
9005 Rd = Bits32(opcode, 15, 12);
9006 Rn = Bits32(opcode, 19, 16);
9007 Rm = Bits32(opcode, 3, 0);
9008 setflags = BitIsSet(opcode, 20);
9009 shift_n = DecodeImmShiftARM(opcode, shift_t);
9011 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
9012 if (Rd == 15 && setflags)
9013 return EmulateSUBSPcLrEtc (opcode, encoding);
9018 // Read the register value from register Rn.
9019 uint32_t val1 = ReadCoreReg(Rn, &success);
9023 // Read the register value from register Rm.
9024 uint32_t val2 = ReadCoreReg(Rm, &success);
9028 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
9031 AddWithCarryResult res = AddWithCarry(val1, ~shifted, APSR_C);
9033 EmulateInstruction::Context context;
9034 context.type = EmulateInstruction::eContextImmediate;
9035 context.SetNoArgs();
9036 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
9042 // This instruction subtracts an immediate value from a register value, and writes the result
9043 // to the destination register. It can optionally update the condition flags based on the result.
9045 EmulateInstructionARM::EmulateSUBImmThumb (const uint32_t opcode, const ARMEncoding encoding)
9048 // ARM pseudo code...
9049 if ConditionPassed() then
9050 EncodingSpecificOperations();
9051 (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1');
9054 APSR.N = result<31>;
9055 APSR.Z = IsZeroBit(result);
9060 bool success = false;
9062 uint32_t Rd; // the destination register
9063 uint32_t Rn; // the first operand
9065 uint32_t imm32; // the immediate value to be subtracted from the value obtained from Rn
9068 Rd = Bits32(opcode, 2, 0);
9069 Rn = Bits32(opcode, 5, 3);
9070 setflags = !InITBlock();
9071 imm32 = Bits32(opcode, 8, 6); // imm32 = ZeroExtend(imm3, 32)
9074 Rd = Rn = Bits32(opcode, 10, 8);
9075 setflags = !InITBlock();
9076 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
9079 Rd = Bits32(opcode, 11, 8);
9080 Rn = Bits32(opcode, 19, 16);
9081 setflags = BitIsSet(opcode, 20);
9082 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
9084 // if Rd == '1111' && S == '1' then SEE CMP (immediate);
9085 if (Rd == 15 && setflags)
9086 return EmulateCMPImm (opcode, eEncodingT2);
9088 // if Rn == '1101' then SEE SUB (SP minus immediate);
9090 return EmulateSUBSPImm (opcode, eEncodingT2);
9092 // if d == 13 || (d == 15 && S == '0') || n == 15 then UNPREDICTABLE;
9093 if (Rd == 13 || (Rd == 15 && !setflags) || Rn == 15)
9097 Rd = Bits32(opcode, 11, 8);
9098 Rn = Bits32(opcode, 19, 16);
9099 setflags = BitIsSet(opcode, 20);
9100 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
9102 // if Rn == '1111' then SEE ADR;
9104 return EmulateADR (opcode, eEncodingT2);
9106 // if Rn == '1101' then SEE SUB (SP minus immediate);
9108 return EmulateSUBSPImm (opcode, eEncodingT3);
9116 // Read the register value from the operand register Rn.
9117 uint32_t reg_val = ReadCoreReg(Rn, &success);
9121 AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1);
9123 EmulateInstruction::Context context;
9124 context.type = EmulateInstruction::eContextImmediate;
9125 context.SetNoArgs ();
9127 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
9133 // This instruction subtracts an immediate value from a register value, and writes the result
9134 // to the destination register. It can optionally update the condition flags based on the result.
9136 EmulateInstructionARM::EmulateSUBImmARM (const uint32_t opcode, const ARMEncoding encoding)
9139 // ARM pseudo code...
9140 if ConditionPassed() then
9141 EncodingSpecificOperations();
9142 (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1');
9144 ALUWritePC(result); // setflags is always FALSE here
9148 APSR.N = result<31>;
9149 APSR.Z = IsZeroBit(result);
9154 bool success = false;
9156 uint32_t Rd; // the destination register
9157 uint32_t Rn; // the first operand
9159 uint32_t imm32; // the immediate value to be subtracted from the value obtained from Rn
9162 Rd = Bits32(opcode, 15, 12);
9163 Rn = Bits32(opcode, 19, 16);
9164 setflags = BitIsSet(opcode, 20);
9165 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
9167 // if Rn == '1111' && S == '0' then SEE ADR;
9168 if (Rn == 15 && !setflags)
9169 return EmulateADR (opcode, eEncodingA2);
9171 // if Rn == '1101' then SEE SUB (SP minus immediate);
9173 return EmulateSUBSPImm (opcode, eEncodingA1);
9175 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
9176 if (Rd == 15 && setflags)
9177 return EmulateSUBSPcLrEtc (opcode, encoding);
9182 // Read the register value from the operand register Rn.
9183 uint32_t reg_val = ReadCoreReg(Rn, &success);
9187 AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1);
9189 EmulateInstruction::Context context;
9190 context.type = EmulateInstruction::eContextImmediate;
9191 context.SetNoArgs ();
9193 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
9199 // Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an
9200 // immediate value. It updates the condition flags based on the result, and discards the result.
9202 EmulateInstructionARM::EmulateTEQImm (const uint32_t opcode, const ARMEncoding encoding)
9205 // ARM pseudo code...
9206 if ConditionPassed() then
9207 EncodingSpecificOperations();
9208 result = R[n] EOR imm32;
9209 APSR.N = result<31>;
9210 APSR.Z = IsZeroBit(result);
9215 bool success = false;
9217 if (ConditionPassed(opcode))
9220 uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn
9221 uint32_t carry; // the carry bit after ARM/Thumb Expand operation
9225 Rn = Bits32(opcode, 19, 16);
9226 imm32 = ThumbExpandImm_C (opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
9231 Rn = Bits32(opcode, 19, 16);
9232 imm32 = ARMExpandImm_C (opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
9238 // Read the first operand.
9239 uint32_t val1 = ReadCoreReg(Rn, &success);
9243 uint32_t result = val1 ^ imm32;
9245 EmulateInstruction::Context context;
9246 context.type = EmulateInstruction::eContextImmediate;
9247 context.SetNoArgs ();
9249 if (!WriteFlags(context, result, carry))
9255 // Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an
9256 // optionally-shifted register value. It updates the condition flags based on the result, and discards
9259 EmulateInstructionARM::EmulateTEQReg (const uint32_t opcode, const ARMEncoding encoding)
9262 // ARM pseudo code...
9263 if ConditionPassed() then
9264 EncodingSpecificOperations();
9265 (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
9266 result = R[n] EOR shifted;
9267 APSR.N = result<31>;
9268 APSR.Z = IsZeroBit(result);
9273 bool success = false;
9275 if (ConditionPassed(opcode))
9278 ARM_ShifterType shift_t;
9279 uint32_t shift_n; // the shift applied to the value read from Rm
9284 Rn = Bits32(opcode, 19, 16);
9285 Rm = Bits32(opcode, 3, 0);
9286 shift_n = DecodeImmShiftThumb(opcode, shift_t);
9287 if (BadReg(Rn) || BadReg(Rm))
9291 Rn = Bits32(opcode, 19, 16);
9292 Rm = Bits32(opcode, 3, 0);
9293 shift_n = DecodeImmShiftARM(opcode, shift_t);
9299 // Read the first operand.
9300 uint32_t val1 = ReadCoreReg(Rn, &success);
9304 // Read the second operand.
9305 uint32_t val2 = ReadCoreReg(Rm, &success);
9309 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
9312 uint32_t result = val1 ^ shifted;
9314 EmulateInstruction::Context context;
9315 context.type = EmulateInstruction::eContextImmediate;
9316 context.SetNoArgs ();
9318 if (!WriteFlags(context, result, carry))
9324 // Test (immediate) performs a bitwise AND operation on a register value and an immediate value.
9325 // It updates the condition flags based on the result, and discards the result.
9327 EmulateInstructionARM::EmulateTSTImm (const uint32_t opcode, const ARMEncoding encoding)
9330 // ARM pseudo code...
9331 if ConditionPassed() then
9332 EncodingSpecificOperations();
9333 result = R[n] AND imm32;
9334 APSR.N = result<31>;
9335 APSR.Z = IsZeroBit(result);
9340 bool success = false;
9342 if (ConditionPassed(opcode))
9345 uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn
9346 uint32_t carry; // the carry bit after ARM/Thumb Expand operation
9350 Rn = Bits32(opcode, 19, 16);
9351 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
9356 Rn = Bits32(opcode, 19, 16);
9357 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
9363 // Read the first operand.
9364 uint32_t val1 = ReadCoreReg(Rn, &success);
9368 uint32_t result = val1 & imm32;
9370 EmulateInstruction::Context context;
9371 context.type = EmulateInstruction::eContextImmediate;
9372 context.SetNoArgs ();
9374 if (!WriteFlags(context, result, carry))
9380 // Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value.
9381 // It updates the condition flags based on the result, and discards the result.
9383 EmulateInstructionARM::EmulateTSTReg (const uint32_t opcode, const ARMEncoding encoding)
9386 // ARM pseudo code...
9387 if ConditionPassed() then
9388 EncodingSpecificOperations();
9389 (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
9390 result = R[n] AND shifted;
9391 APSR.N = result<31>;
9392 APSR.Z = IsZeroBit(result);
9397 bool success = false;
9399 if (ConditionPassed(opcode))
9402 ARM_ShifterType shift_t;
9403 uint32_t shift_n; // the shift applied to the value read from Rm
9408 Rn = Bits32(opcode, 2, 0);
9409 Rm = Bits32(opcode, 5, 3);
9410 shift_t = SRType_LSL;
9414 Rn = Bits32(opcode, 19, 16);
9415 Rm = Bits32(opcode, 3, 0);
9416 shift_n = DecodeImmShiftThumb(opcode, shift_t);
9417 if (BadReg(Rn) || BadReg(Rm))
9421 Rn = Bits32(opcode, 19, 16);
9422 Rm = Bits32(opcode, 3, 0);
9423 shift_n = DecodeImmShiftARM(opcode, shift_t);
9429 // Read the first operand.
9430 uint32_t val1 = ReadCoreReg(Rn, &success);
9434 // Read the second operand.
9435 uint32_t val2 = ReadCoreReg(Rm, &success);
9439 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
9442 uint32_t result = val1 & shifted;
9444 EmulateInstruction::Context context;
9445 context.type = EmulateInstruction::eContextImmediate;
9446 context.SetNoArgs ();
9448 if (!WriteFlags(context, result, carry))
9454 // A8.6.216 SUB (SP minus register)
9456 EmulateInstructionARM::EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding encoding)
9459 if ConditionPassed() then
9460 EncodingSpecificOperations();
9461 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
9462 (result, carry, overflow) = AddWithCarry(SP, NOT(shifted), Ô1Õ);
9463 if d == 15 then // Can only occur for ARM encoding
9464 ALUWritePC(result); // setflags is always FALSE here
9468 APSR.N = result<31>;
9469 APSR.Z = IsZeroBit(result);
9474 bool success = false;
9476 if (ConditionPassed(opcode))
9481 ARM_ShifterType shift_t;
9487 // d = UInt(Rd); m = UInt(Rm); setflags = (S == Ô1Õ);
9488 d = Bits32 (opcode, 11, 8);
9489 m = Bits32 (opcode, 3, 0);
9490 setflags = BitIsSet (opcode, 20);
9492 // (shift_t, shift_n) = DecodeImmShift(type, imm3:imm2);
9493 shift_n = DecodeImmShiftThumb (opcode, shift_t);
9495 // if d == 13 && (shift_t != SRType_LSL || shift_n > 3) then UNPREDICTABLE;
9496 if ((d == 13) && ((shift_t != SRType_LSL) || (shift_n > 3)))
9499 // if d == 15 || BadReg(m) then UNPREDICTABLE;
9500 if ((d == 15) || BadReg (m))
9505 // d = UInt(Rd); m = UInt(Rm); setflags = (S == Ô1Õ);
9506 d = Bits32 (opcode, 15, 12);
9507 m = Bits32 (opcode, 3, 0);
9508 setflags = BitIsSet (opcode, 20);
9510 // if Rd == Ô1111Õ && S == Ô1Õ then SEE SUBS PC, LR and related instructions;
9511 if (d == 15 && setflags)
9512 EmulateSUBSPcLrEtc (opcode, encoding);
9514 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
9515 shift_n = DecodeImmShiftARM (opcode, shift_t);
9522 // shifted = Shift(R[m], shift_t, shift_n, APSR.C);
9523 uint32_t Rm = ReadCoreReg (m, &success);
9527 uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C, &success);
9531 // (result, carry, overflow) = AddWithCarry(SP, NOT(shifted), Ô1Õ);
9532 uint32_t sp_val = ReadCoreReg (SP_REG, &success);
9536 AddWithCarryResult res = AddWithCarry (sp_val, ~shifted, 1);
9538 EmulateInstruction::Context context;
9539 context.type = eContextArithmetic;
9540 RegisterInfo sp_reg;
9541 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
9542 RegisterInfo dwarf_reg;
9543 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, dwarf_reg);
9544 context.SetRegisterRegisterOperands (sp_reg, dwarf_reg);
9546 if (!WriteCoreRegOptionalFlags(context, res.result, dwarf_r0 + d, setflags, res.carry_out, res.overflow))
9553 // A8.6.7 ADD (register-shifted register)
9555 EmulateInstructionARM::EmulateADDRegShift (const uint32_t opcode, const ARMEncoding encoding)
9558 if ConditionPassed() then
9559 EncodingSpecificOperations();
9560 shift_n = UInt(R[s]<7:0>);
9561 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
9562 (result, carry, overflow) = AddWithCarry(R[n], shifted, Ô0Õ);
9565 APSR.N = result<31>;
9566 APSR.Z = IsZeroBit(result);
9571 bool success = false;
9573 if (ConditionPassed(opcode))
9580 ARM_ShifterType shift_t;
9585 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); s = UInt(Rs);
9586 d = Bits32 (opcode, 15, 12);
9587 n = Bits32 (opcode, 19, 16);
9588 m = Bits32 (opcode, 3, 0);
9589 s = Bits32 (opcode, 11, 8);
9591 // setflags = (S == Ô1Õ); shift_t = DecodeRegShift(type);
9592 setflags = BitIsSet (opcode, 20);
9593 shift_t = DecodeRegShift (Bits32 (opcode, 6, 5));
9595 // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
9596 if ((d == 15) || (m == 15) || (m == 15) || (s == 15))
9604 // shift_n = UInt(R[s]<7:0>);
9605 uint32_t Rs = ReadCoreReg (s, &success);
9609 uint32_t shift_n = Bits32 (Rs, 7, 0);
9611 // shifted = Shift(R[m], shift_t, shift_n, APSR.C);
9612 uint32_t Rm = ReadCoreReg (m, &success);
9616 uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C, &success);
9620 // (result, carry, overflow) = AddWithCarry(R[n], shifted, Ô0Õ);
9621 uint32_t Rn = ReadCoreReg (n, &success);
9625 AddWithCarryResult res = AddWithCarry (Rn, shifted, 0);
9628 EmulateInstruction::Context context;
9629 context.type = eContextArithmetic;
9631 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, reg_n);
9633 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, reg_m);
9635 context.SetRegisterRegisterOperands (reg_n, reg_m);
9637 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, res.result))
9641 // APSR.N = result<31>;
9642 // APSR.Z = IsZeroBit(result);
9644 // APSR.V = overflow;
9646 return WriteFlags (context, res.result, res.carry_out, res.overflow);
9651 // A8.6.213 SUB (register)
9653 EmulateInstructionARM::EmulateSUBReg (const uint32_t opcode, const ARMEncoding encoding)
9656 if ConditionPassed() then
9657 EncodingSpecificOperations();
9658 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
9659 (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), Ô1Õ);
9660 if d == 15 then // Can only occur for ARM encoding
9661 ALUWritePC(result); // setflags is always FALSE here
9665 APSR.N = result<31>;
9666 APSR.Z = IsZeroBit(result);
9671 bool success = false;
9673 if (ConditionPassed(opcode))
9679 ARM_ShifterType shift_t;
9685 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = !InITBlock();
9686 d = Bits32 (opcode, 2, 0);
9687 n = Bits32 (opcode, 5, 3);
9688 m = Bits32 (opcode, 8, 6);
9689 setflags = !InITBlock();
9691 // (shift_t, shift_n) = (SRType_LSL, 0);
9692 shift_t = SRType_LSL;
9698 // if Rd == Ô1111Õ && S == Ô1Õ then SEE CMP (register);
9699 // if Rn == Ô1101Õ then SEE SUB (SP minus register);
9700 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == Ô1Õ);
9701 d = Bits32 (opcode, 11, 8);
9702 n = Bits32 (opcode, 19, 16);
9703 m = Bits32 (opcode, 3, 0);
9704 setflags = BitIsSet (opcode, 20);
9706 // (shift_t, shift_n) = DecodeImmShift(type, imm3:imm2);
9707 shift_n = DecodeImmShiftThumb (opcode, shift_t);
9709 // if d == 13 || (d == 15 && S == '0') || n == 15 || BadReg(m) then UNPREDICTABLE;
9710 if ((d == 13) || ((d == 15) && BitIsClear (opcode, 20)) || (n == 15) || BadReg (m))
9716 // if Rn == Ô1101Õ then SEE SUB (SP minus register);
9717 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == Ô1Õ);
9718 d = Bits32 (opcode, 15, 12);
9719 n = Bits32 (opcode, 19, 16);
9720 m = Bits32 (opcode, 3, 0);
9721 setflags = BitIsSet (opcode, 20);
9723 // if Rd == Ô1111Õ && S == Ô1Õ then SEE SUBS PC, LR and related instructions;
9724 if ((d == 15) && setflags)
9725 EmulateSUBSPcLrEtc (opcode, encoding);
9727 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
9728 shift_n = DecodeImmShiftARM (opcode, shift_t);
9736 // shifted = Shift(R[m], shift_t, shift_n, APSR.C);
9737 uint32_t Rm = ReadCoreReg (m, &success);
9741 uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C, &success);
9745 // (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), Ô1Õ);
9746 uint32_t Rn = ReadCoreReg (n, &success);
9750 AddWithCarryResult res = AddWithCarry (Rn, ~shifted, 1);
9752 // if d == 15 then // Can only occur for ARM encoding
9753 // ALUWritePC(result); // setflags is always FALSE here
9757 // APSR.N = result<31>;
9758 // APSR.Z = IsZeroBit(result);
9760 // APSR.V = overflow;
9762 EmulateInstruction::Context context;
9763 context.type = eContextArithmetic;
9765 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, reg_n);
9767 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, reg_m);
9768 context.SetRegisterRegisterOperands (reg_n, reg_m);
9770 if (!WriteCoreRegOptionalFlags (context, res.result, dwarf_r0 + d, setflags, res.carry_out, res.overflow))
9777 // Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a
9778 // word from a register to memory if the executing processor has exclusive access to the memory addressed.
9780 EmulateInstructionARM::EmulateSTREX (const uint32_t opcode, const ARMEncoding encoding)
9783 if ConditionPassed() then
9784 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
9785 address = R[n] + imm32;
9786 if ExclusiveMonitorsPass(address,4) then
9787 MemA[address,4] = R[t];
9793 bool success = false;
9795 if (ConditionPassed(opcode))
9801 const uint32_t addr_byte_size = GetAddressByteSize();
9806 // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
9807 d = Bits32 (opcode, 11, 8);
9808 t = Bits32 (opcode, 15, 12);
9809 n = Bits32 (opcode, 19, 16);
9810 imm32 = Bits32 (opcode, 7, 0) << 2;
9812 // if BadReg(d) || BadReg(t) || n == 15 then UNPREDICTABLE;
9813 if (BadReg (d) || BadReg (t) || (n == 15))
9816 // if d == n || d == t then UNPREDICTABLE;
9817 if ((d == n) || (d == t))
9823 // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = Zeros(32); // Zero offset
9824 d = Bits32 (opcode, 15, 12);
9825 t = Bits32 (opcode, 3, 0);
9826 n = Bits32 (opcode, 19, 16);
9829 // if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
9830 if ((d == 15) || (t == 15) || (n == 15))
9833 // if d == n || d == t then UNPREDICTABLE;
9834 if ((d == n) || (d == t))
9843 // address = R[n] + imm32;
9844 uint32_t Rn = ReadCoreReg (n, &success);
9848 addr_t address = Rn + imm32;
9850 RegisterInfo base_reg;
9851 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
9852 RegisterInfo data_reg;
9853 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
9854 EmulateInstruction::Context context;
9855 context.type = eContextRegisterStore;
9856 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, imm32);
9858 // if ExclusiveMonitorsPass(address,4) then
9859 // if (ExclusiveMonitorsPass (address, addr_byte_size)) -- For now, for the sake of emulation, we will say this
9860 // always return true.
9863 // MemA[address,4] = R[t];
9864 uint32_t Rt = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
9868 if (!MemAWrite (context, address, Rt, addr_byte_size))
9872 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, 0))
9878 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, 1))
9885 // A8.6.197 STRB (immediate, ARM)
9887 EmulateInstructionARM::EmulateSTRBImmARM (const uint32_t opcode, const ARMEncoding encoding)
9890 if ConditionPassed() then
9891 EncodingSpecificOperations();
9892 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
9893 address = if index then offset_addr else R[n];
9894 MemU[address,1] = R[t]<7:0>;
9895 if wback then R[n] = offset_addr;
9898 bool success = false;
9900 if (ConditionPassed(opcode))
9912 // if P == Ô0Õ && W == Ô1Õ then SEE STRBT;
9913 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
9914 t = Bits32 (opcode, 15, 12);
9915 n = Bits32 (opcode, 19, 16);
9916 imm32 = Bits32 (opcode, 11, 0);
9918 // index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (P == Ô0Õ) || (W == Ô1Õ);
9919 index = BitIsSet (opcode, 24);
9920 add = BitIsSet (opcode, 23);
9921 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
9923 // if t == 15 then UNPREDICTABLE;
9927 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
9928 if (wback && ((n == 15) || (n == t)))
9937 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
9938 uint32_t Rn = ReadCoreReg (n, &success);
9944 offset_addr = Rn + imm32;
9946 offset_addr = Rn - imm32;
9948 // address = if index then offset_addr else R[n];
9951 address = offset_addr;
9955 // MemU[address,1] = R[t]<7:0>;
9956 uint32_t Rt = ReadCoreReg (t, &success);
9960 RegisterInfo base_reg;
9961 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
9962 RegisterInfo data_reg;
9963 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
9964 EmulateInstruction::Context context;
9965 context.type = eContextRegisterStore;
9966 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
9968 if (!MemUWrite (context, address, Bits32 (Rt, 7, 0), 1))
9971 // if wback then R[n] = offset_addr;
9974 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
9981 // A8.6.194 STR (immediate, ARM)
9983 EmulateInstructionARM::EmulateSTRImmARM (const uint32_t opcode, const ARMEncoding encoding)
9986 if ConditionPassed() then
9987 EncodingSpecificOperations();
9988 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
9989 address = if index then offset_addr else R[n];
9990 MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
9991 if wback then R[n] = offset_addr;
9994 bool success = false;
9996 if (ConditionPassed(opcode))
10005 const uint32_t addr_byte_size = GetAddressByteSize();
10010 // if P == Ô0Õ && W == Ô1Õ then SEE STRT;
10011 // if Rn == Ô1101Õ && P == Ô1Õ && U == Ô0Õ && W == Ô1Õ && imm12 == Ô000000000100Õ then SEE PUSH;
10012 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
10013 t = Bits32 (opcode, 15, 12);
10014 n = Bits32 (opcode, 19, 16);
10015 imm32 = Bits32 (opcode, 11, 0);
10017 // index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (P == Ô0Õ) || (W == Ô1Õ);
10018 index = BitIsSet (opcode, 24);
10019 add = BitIsSet (opcode, 23);
10020 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
10022 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
10023 if (wback && ((n == 15) || (n == t)))
10032 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10033 uint32_t Rn = ReadCoreReg (n, &success);
10037 addr_t offset_addr;
10039 offset_addr = Rn + imm32;
10041 offset_addr = Rn - imm32;
10043 // address = if index then offset_addr else R[n];
10046 address = offset_addr;
10050 RegisterInfo base_reg;
10051 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
10052 RegisterInfo data_reg;
10053 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
10054 EmulateInstruction::Context context;
10055 context.type = eContextRegisterStore;
10056 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10058 // MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
10059 uint32_t Rt = ReadCoreReg (t, &success);
10065 uint32_t pc_value = ReadCoreReg (PC_REG, &success);
10069 if (!MemUWrite (context, address, pc_value, addr_byte_size))
10074 if (!MemUWrite (context, address, Rt, addr_byte_size))
10078 // if wback then R[n] = offset_addr;
10081 context.type = eContextAdjustBaseRegister;
10082 context.SetImmediate (offset_addr);
10084 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
10091 // A8.6.66 LDRD (immediate)
10092 // Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two
10093 // words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing.
10095 EmulateInstructionARM::EmulateLDRDImmediate (const uint32_t opcode, const ARMEncoding encoding)
10098 if ConditionPassed() then
10099 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
10100 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10101 address = if index then offset_addr else R[n];
10102 R[t] = MemA[address,4];
10103 R[t2] = MemA[address+4,4];
10104 if wback then R[n] = offset_addr;
10107 bool success = false;
10109 if (ConditionPassed(opcode))
10122 //if P == Ô0Õ && W == Ô0Õ then SEE ÒRelated encodingsÓ;
10123 //if Rn == Ô1111Õ then SEE LDRD (literal);
10124 //t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
10125 t = Bits32 (opcode, 15, 12);
10126 t2 = Bits32 (opcode, 11, 8);
10127 n = Bits32 (opcode, 19, 16);
10128 imm32 = Bits32 (opcode, 7, 0) << 2;
10130 //index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (W == Ô1Õ);
10131 index = BitIsSet (opcode, 24);
10132 add = BitIsSet (opcode, 23);
10133 wback = BitIsSet (opcode, 21);
10135 //if wback && (n == t || n == t2) then UNPREDICTABLE;
10136 if (wback && ((n == t) || (n == t2)))
10139 //if BadReg(t) || BadReg(t2) || t == t2 then UNPREDICTABLE;
10140 if (BadReg (t) || BadReg (t2) || (t == t2))
10146 //if Rn == Ô1111Õ then SEE LDRD (literal);
10147 //if Rt<0> == Ô1Õ then UNPREDICTABLE;
10148 //t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
10149 t = Bits32 (opcode, 15, 12);
10150 if (BitIsSet (t, 0))
10153 n = Bits32 (opcode, 19, 16);
10154 imm32 = (Bits32 (opcode, 11, 8) << 4) | Bits32 (opcode, 3, 0);
10156 //index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (P == Ô0Õ) || (W == Ô1Õ);
10157 index = BitIsSet (opcode, 24);
10158 add = BitIsSet (opcode, 23);
10159 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
10161 //if P == Ô0Õ && W == Ô1Õ then UNPREDICTABLE;
10162 if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21))
10165 //if wback && (n == t || n == t2) then UNPREDICTABLE;
10166 if (wback && ((n == t) || (n == t2)))
10169 //if t2 == 15 then UNPREDICTABLE;
10179 //offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10180 uint32_t Rn = ReadCoreReg (n, &success);
10184 addr_t offset_addr;
10186 offset_addr = Rn + imm32;
10188 offset_addr = Rn - imm32;
10190 //address = if index then offset_addr else R[n];
10193 address = offset_addr;
10197 //R[t] = MemA[address,4];
10198 RegisterInfo base_reg;
10199 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
10201 EmulateInstruction::Context context;
10202 context.type = eContextRegisterLoad;
10203 context.SetRegisterPlusOffset (base_reg, address - Rn);
10205 const uint32_t addr_byte_size = GetAddressByteSize();
10206 uint32_t data = MemARead (context, address, addr_byte_size, 0, &success);
10210 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
10213 //R[t2] = MemA[address+4,4];
10215 context.SetRegisterPlusOffset (base_reg, (address + 4) - Rn);
10216 data = MemARead (context, address + 4, addr_byte_size, 0, &success);
10220 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t2, data))
10223 //if wback then R[n] = offset_addr;
10226 context.type = eContextAdjustBaseRegister;
10227 context.SetAddress (offset_addr);
10229 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
10236 // A8.6.68 LDRD (register)
10237 // Load Register Dual (register) calculates an address from a base register value and a register offset, loads two
10238 // words from memory, and writes them to two registers. It can use offset, post-indexed or pre-indexed addressing.
10240 EmulateInstructionARM::EmulateLDRDRegister (const uint32_t opcode, const ARMEncoding encoding)
10243 if ConditionPassed() then
10244 EncodingSpecificOperations();
10245 offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
10246 address = if index then offset_addr else R[n];
10247 R[t] = MemA[address,4];
10248 R[t2] = MemA[address+4,4];
10249 if wback then R[n] = offset_addr;
10252 bool success = false;
10254 if (ConditionPassed(opcode))
10267 // if Rt<0> == Ô1Õ then UNPREDICTABLE;
10268 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
10269 t = Bits32 (opcode, 15, 12);
10270 if (BitIsSet (t, 0))
10273 n = Bits32 (opcode, 19, 16);
10274 m = Bits32 (opcode, 3, 0);
10276 // index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (P == Ô0Õ) || (W == Ô1Õ);
10277 index = BitIsSet (opcode, 24);
10278 add = BitIsSet (opcode, 23);
10279 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
10281 // if P == Ô0Õ && W == Ô1Õ then UNPREDICTABLE;
10282 if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21))
10285 // if t2 == 15 || m == 15 || m == t || m == t2 then UNPREDICTABLE;
10286 if ((t2 == 15) || (m == 15) || (m == t) || (m == t2))
10289 // if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;
10290 if (wback && ((n == 15) || (n == t) || (n == t2)))
10293 // if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;
10294 if ((ArchVersion() < 6) && wback && (m == n))
10302 uint32_t Rn = ReadCoreReg (n, &success);
10305 RegisterInfo base_reg;
10306 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
10308 uint32_t Rm = ReadCoreReg (m, &success);
10311 RegisterInfo offset_reg;
10312 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
10314 // offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
10315 addr_t offset_addr;
10317 offset_addr = Rn + Rm;
10319 offset_addr = Rn - Rm;
10321 // address = if index then offset_addr else R[n];
10324 address = offset_addr;
10328 EmulateInstruction::Context context;
10329 context.type = eContextRegisterLoad;
10330 context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
10332 // R[t] = MemA[address,4];
10333 const uint32_t addr_byte_size = GetAddressByteSize();
10334 uint32_t data = MemARead (context, address, addr_byte_size, 0, &success);
10338 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
10341 // R[t2] = MemA[address+4,4];
10343 data = MemARead (context, address + 4, addr_byte_size, 0, &success);
10347 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t2, data))
10350 // if wback then R[n] = offset_addr;
10353 context.type = eContextAdjustBaseRegister;
10354 context.SetAddress (offset_addr);
10356 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
10363 // A8.6.200 STRD (immediate)
10364 // Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and
10365 // stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing.
10367 EmulateInstructionARM::EmulateSTRDImm (const uint32_t opcode, const ARMEncoding encoding)
10370 if ConditionPassed() then
10371 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
10372 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10373 address = if index then offset_addr else R[n];
10374 MemA[address,4] = R[t];
10375 MemA[address+4,4] = R[t2];
10376 if wback then R[n] = offset_addr;
10379 bool success = false;
10381 if (ConditionPassed(opcode))
10394 // if P == Ô0Õ && W == Ô0Õ then SEE ÒRelated encodingsÓ;
10395 // t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
10396 t = Bits32 (opcode, 15, 12);
10397 t2 = Bits32 (opcode, 11, 8);
10398 n = Bits32 (opcode, 19, 16);
10399 imm32 = Bits32 (opcode, 7, 0) << 2;
10401 // index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (W == Ô1Õ);
10402 index = BitIsSet (opcode, 24);
10403 add = BitIsSet (opcode, 23);
10404 wback = BitIsSet (opcode, 21);
10406 // if wback && (n == t || n == t2) then UNPREDICTABLE;
10407 if (wback && ((n == t) || (n == t2)))
10410 // if n == 15 || BadReg(t) || BadReg(t2) then UNPREDICTABLE;
10411 if ((n == 15) || BadReg (t) || BadReg (t2))
10417 // if Rt<0> == Ô1Õ then UNPREDICTABLE;
10418 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
10419 t = Bits32 (opcode, 15, 12);
10420 if (BitIsSet (t, 0))
10424 n = Bits32 (opcode, 19, 16);
10425 imm32 = (Bits32 (opcode, 11, 8) << 4) | Bits32 (opcode, 3, 0);
10427 // index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (P == Ô0Õ) || (W == Ô1Õ);
10428 index = BitIsSet (opcode, 24);
10429 add = BitIsSet (opcode, 23);
10430 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
10432 // if P == Ô0Õ && W == Ô1Õ then UNPREDICTABLE;
10433 if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21))
10436 // if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;
10437 if (wback && ((n == 15) || (n == t) || (n == t2)))
10440 // if t2 == 15 then UNPREDICTABLE;
10450 RegisterInfo base_reg;
10451 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
10453 uint32_t Rn = ReadCoreReg (n, &success);
10457 //offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10458 addr_t offset_addr;
10460 offset_addr = Rn + imm32;
10462 offset_addr = Rn - imm32;
10464 //address = if index then offset_addr else R[n];
10467 address = offset_addr;
10471 //MemA[address,4] = R[t];
10472 RegisterInfo data_reg;
10473 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
10475 uint32_t data = ReadCoreReg (t, &success);
10479 EmulateInstruction::Context context;
10480 context.type = eContextRegisterStore;
10481 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10483 const uint32_t addr_byte_size = GetAddressByteSize();
10485 if (!MemAWrite (context, address, data, addr_byte_size))
10488 //MemA[address+4,4] = R[t2];
10489 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t2, data_reg);
10490 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
10492 data = ReadCoreReg (t2, &success);
10496 if (!MemAWrite (context, address + 4, data, addr_byte_size))
10499 //if wback then R[n] = offset_addr;
10502 context.type = eContextAdjustBaseRegister;
10503 context.SetAddress (offset_addr);
10505 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
10513 // A8.6.201 STRD (register)
10515 EmulateInstructionARM::EmulateSTRDReg (const uint32_t opcode, const ARMEncoding encoding)
10518 if ConditionPassed() then
10519 EncodingSpecificOperations();
10520 offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
10521 address = if index then offset_addr else R[n];
10522 MemA[address,4] = R[t];
10523 MemA[address+4,4] = R[t2];
10524 if wback then R[n] = offset_addr;
10527 bool success = false;
10529 if (ConditionPassed(opcode))
10542 // if Rt<0> == Ô1Õ then UNPREDICTABLE;
10543 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
10544 t = Bits32 (opcode, 15, 12);
10545 if (BitIsSet (t, 0))
10549 n = Bits32 (opcode, 19, 16);
10550 m = Bits32 (opcode, 3, 0);
10552 // index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (P == Ô0Õ) || (W == Ô1Õ);
10553 index = BitIsSet (opcode, 24);
10554 add = BitIsSet (opcode, 23);
10555 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
10557 // if P == Ô0Õ && W == Ô1Õ then UNPREDICTABLE;
10558 if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21))
10561 // if t2 == 15 || m == 15 then UNPREDICTABLE;
10562 if ((t2 == 15) || (m == 15))
10565 // if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;
10566 if (wback && ((n == 15) || (n == t) || (n == t2)))
10569 // if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;
10570 if ((ArchVersion() < 6) && wback && (m == n))
10579 RegisterInfo base_reg;
10580 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
10581 RegisterInfo offset_reg;
10582 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
10583 RegisterInfo data_reg;
10585 uint32_t Rn = ReadCoreReg (n, &success);
10589 uint32_t Rm = ReadCoreReg (m, &success);
10593 // offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
10594 addr_t offset_addr;
10596 offset_addr = Rn + Rm;
10598 offset_addr = Rn - Rm;
10600 // address = if index then offset_addr else R[n];
10603 address = offset_addr;
10606 // MemA[address,4] = R[t];
10607 uint32_t Rt = ReadCoreReg (t, &success);
10611 EmulateInstruction::Context context;
10612 context.type = eContextRegisterStore;
10613 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
10614 context.SetRegisterToRegisterPlusIndirectOffset (base_reg, offset_reg, data_reg);
10616 const uint32_t addr_byte_size = GetAddressByteSize();
10618 if (!MemAWrite (context, address, Rt, addr_byte_size))
10621 // MemA[address+4,4] = R[t2];
10622 uint32_t Rt2 = ReadCoreReg (t2, &success);
10626 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t2, data_reg);
10628 context.SetRegisterToRegisterPlusIndirectOffset (base_reg, offset_reg, data_reg);
10630 if (!MemAWrite (context, address + 4, Rt2, addr_byte_size))
10633 // if wback then R[n] = offset_addr;
10636 context.type = eContextAdjustBaseRegister;
10637 context.SetAddress (offset_addr);
10639 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
10648 // Vector Load Multiple loads multiple extension registers from consecutive memory locations using an address from
10649 // an ARM core register.
10651 EmulateInstructionARM::EmulateVLDM (const uint32_t opcode, const ARMEncoding encoding)
10654 if ConditionPassed() then
10655 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(n);
10656 address = if add then R[n] else R[n]-imm32;
10657 if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
10658 for r = 0 to regs-1
10659 if single_regs then
10660 S[d+r] = MemA[address,4]; address = address+4;
10662 word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;
10663 // Combine the word-aligned words in the correct order for current endianness.
10664 D[d+r] = if BigEndian() then word1:word2 else word2:word1;
10667 bool success = false;
10669 if (ConditionPassed(opcode))
10683 // if P == Ô0Õ && U == Ô0Õ && W == Ô0Õ then SEE ÒRelated encodingsÓ;
10684 // if P == Ô0Õ && U == Ô1Õ && W == Ô1Õ && Rn == Ô1101Õ then SEE VPOP;
10685 // if P == Ô1Õ && W == Ô0Õ then SEE VLDR;
10686 // if P == U && W == Ô1Õ then UNDEFINED;
10687 if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21))
10690 // // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
10691 // single_regs = FALSE; add = (U == Ô1Õ); wback = (W == Ô1Õ);
10692 single_regs = false;
10693 add = BitIsSet (opcode, 23);
10694 wback = BitIsSet (opcode, 21);
10696 // d = UInt(D:Vd); n = UInt(Rn); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
10697 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
10698 n = Bits32 (opcode, 19, 16);
10699 imm32 = Bits32 (opcode, 7, 0) << 2;
10701 // regs = UInt(imm8) DIV 2; // If UInt(imm8) is odd, see ÒFLDMXÓ.
10702 regs = Bits32 (opcode, 7, 0) / 2;
10704 // if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;
10705 if (n == 15 && (wback || CurrentInstrSet() != eModeARM))
10708 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
10709 if ((regs == 0) || (regs > 16) || ((d + regs) > 32))
10716 // if P == Ô0Õ && U == Ô0Õ && W == Ô0Õ then SEE ÒRelated encodingsÓ;
10717 // if P == Ô0Õ && U == Ô1Õ && W == Ô1Õ && Rn == Ô1101Õ then SEE VPOP;
10718 // if P == Ô1Õ && W == Ô0Õ then SEE VLDR;
10719 // if P == U && W == Ô1Õ then UNDEFINED;
10720 if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21))
10723 // // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
10724 // single_regs = TRUE; add = (U == Ô1Õ); wback = (W == Ô1Õ); d = UInt(Vd:D); n = UInt(Rn);
10725 single_regs = true;
10726 add = BitIsSet (opcode, 23);
10727 wback = BitIsSet (opcode, 21);
10728 d = (Bits32 (opcode, 15, 12) << 1) | Bit32 (opcode, 22);
10729 n = Bits32 (opcode, 19, 16);
10731 // imm32 = ZeroExtend(imm8:Õ00Õ, 32); regs = UInt(imm8);
10732 imm32 = Bits32 (opcode, 7, 0) << 2;
10733 regs = Bits32 (opcode, 7, 0);
10735 // if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;
10736 if ((n == 15) && (wback || (CurrentInstrSet() != eModeARM)))
10739 // if regs == 0 || (d+regs) > 32 then UNPREDICTABLE;
10740 if ((regs == 0) || ((d + regs) > 32))
10748 RegisterInfo base_reg;
10749 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
10751 uint32_t Rn = ReadCoreReg (n, &success);
10755 // address = if add then R[n] else R[n]-imm32;
10760 address = Rn - imm32;
10762 // if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
10763 EmulateInstruction::Context context;
10769 value = Rn + imm32;
10771 value = Rn - imm32;
10773 context.type = eContextAdjustBaseRegister;
10774 context.SetImmediateSigned (value - Rn);
10775 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, value))
10780 const uint32_t addr_byte_size = GetAddressByteSize();
10781 uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
10783 context.type = eContextRegisterLoad;
10785 // for r = 0 to regs-1
10786 for (uint32_t r = 0; r < regs; ++r)
10790 // S[d+r] = MemA[address,4]; address = address+4;
10791 context.SetRegisterPlusOffset (base_reg, address - Rn);
10793 uint32_t data = MemARead (context, address, addr_byte_size, 0, &success);
10797 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, start_reg + d + r, data))
10800 address = address + 4;
10804 // word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;
10805 context.SetRegisterPlusOffset (base_reg, address - Rn);
10806 uint32_t word1 = MemARead (context, address, addr_byte_size, 0, &success);
10810 context.SetRegisterPlusOffset (base_reg, (address + 4) - Rn);
10811 uint32_t word2 = MemARead (context, address + 4, addr_byte_size, 0, &success);
10815 address = address + 8;
10816 // // Combine the word-aligned words in the correct order for current endianness.
10817 // D[d+r] = if BigEndian() then word1:word2 else word2:word1;
10819 if (GetByteOrder() == eByteOrderBig)
10822 data = (data << 32) | word2;
10827 data = (data << 32) | word1;
10830 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, start_reg + d + r, data))
10839 // Vector Store Multiple stores multiple extension registers to consecutive memory locations using an address from an
10840 // ARM core register.
10842 EmulateInstructionARM::EmulateVSTM (const uint32_t opcode, const ARMEncoding encoding)
10845 if ConditionPassed() then
10846 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(n);
10847 address = if add then R[n] else R[n]-imm32;
10848 if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
10849 for r = 0 to regs-1
10850 if single_regs then
10851 MemA[address,4] = S[d+r]; address = address+4;
10853 // Store as two word-aligned words in the correct order for current endianness.
10854 MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
10855 MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
10856 address = address+8;
10859 bool success = false;
10861 if (ConditionPassed (opcode))
10875 // if P == Ô0Õ && U == Ô0Õ && W == Ô0Õ then SEE ÒRelated encodingsÓ;
10876 // if P == Ô1Õ && U == Ô0Õ && W == Ô1Õ && Rn == Ô1101Õ then SEE VPUSH;
10877 // if P == Ô1Õ && W == Ô0Õ then SEE VSTR;
10878 // if P == U && W == Ô1Õ then UNDEFINED;
10879 if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21))
10882 // // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
10883 // single_regs = FALSE; add = (U == Ô1Õ); wback = (W == Ô1Õ);
10884 single_regs = false;
10885 add = BitIsSet (opcode, 23);
10886 wback = BitIsSet (opcode, 21);
10888 // d = UInt(D:Vd); n = UInt(Rn); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
10889 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
10890 n = Bits32 (opcode, 19, 16);
10891 imm32 = Bits32 (opcode, 7, 0) << 2;
10893 // regs = UInt(imm8) DIV 2; // If UInt(imm8) is odd, see ÒFSTMXÓ.
10894 regs = Bits32 (opcode, 7, 0) / 2;
10896 // if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;
10897 if ((n == 15) && (wback || (CurrentInstrSet() != eModeARM)))
10900 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
10901 if ((regs == 0) || (regs > 16) || ((d + regs) > 32))
10908 // if P == Ô0Õ && U == Ô0Õ && W == Ô0Õ then SEE ÒRelated encodingsÓ;
10909 // if P == Ô1Õ && U == Ô0Õ && W == Ô1Õ && Rn == Ô1101Õ then SEE VPUSH;
10910 // if P == Ô1Õ && W == Ô0Õ then SEE VSTR;
10911 // if P == U && W == Ô1Õ then UNDEFINED;
10912 if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21))
10915 // // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
10916 // single_regs = TRUE; add = (U == Ô1Õ); wback = (W == Ô1Õ); d = UInt(Vd:D); n = UInt(Rn);
10917 single_regs = true;
10918 add = BitIsSet (opcode, 23);
10919 wback = BitIsSet (opcode, 21);
10920 d = (Bits32 (opcode, 15, 12) << 1) | Bit32 (opcode, 22);
10921 n = Bits32 (opcode, 19, 16);
10923 // imm32 = ZeroExtend(imm8:Õ00Õ, 32); regs = UInt(imm8);
10924 imm32 = Bits32 (opcode, 7, 0) << 2;
10925 regs = Bits32 (opcode, 7, 0);
10927 // if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;
10928 if ((n == 15) && (wback || (CurrentInstrSet () != eModeARM)))
10931 // if regs == 0 || (d+regs) > 32 then UNPREDICTABLE;
10932 if ((regs == 0) || ((d + regs) > 32))
10941 RegisterInfo base_reg;
10942 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
10944 uint32_t Rn = ReadCoreReg (n, &success);
10948 // address = if add then R[n] else R[n]-imm32;
10953 address = Rn - imm32;
10955 EmulateInstruction::Context context;
10956 // if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
10961 value = Rn + imm32;
10963 value = Rn - imm32;
10965 context.type = eContextAdjustBaseRegister;
10966 context.SetRegisterPlusOffset (base_reg, value - Rn);
10968 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, value))
10972 const uint32_t addr_byte_size = GetAddressByteSize();
10973 uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
10975 context.type = eContextRegisterStore;
10976 // for r = 0 to regs-1
10977 for (uint32_t r = 0; r < regs; ++r)
10982 // MemA[address,4] = S[d+r]; address = address+4;
10983 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, start_reg + d + r, 0, &success);
10987 RegisterInfo data_reg;
10988 GetRegisterInfo (eRegisterKindDWARF, start_reg + d + r, data_reg);
10989 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10990 if (!MemAWrite (context, address, data, addr_byte_size))
10993 address = address + 4;
10997 // // Store as two word-aligned words in the correct order for current endianness.
10998 // MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
10999 // MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
11000 uint64_t data = ReadRegisterUnsigned (eRegisterKindDWARF, start_reg + d + r, 0, &success);
11004 RegisterInfo data_reg;
11005 GetRegisterInfo (eRegisterKindDWARF, start_reg + d + r, data_reg);
11007 if (GetByteOrder() == eByteOrderBig)
11009 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
11010 if (!MemAWrite (context, address, Bits64 (data, 63, 32), addr_byte_size))
11013 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
11014 if (!MemAWrite (context, address+ 4, Bits64 (data, 31, 0), addr_byte_size))
11019 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
11020 if (!MemAWrite (context, address, Bits64 (data, 31, 0), addr_byte_size))
11023 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
11024 if (!MemAWrite (context, address + 4, Bits64 (data, 63, 32), addr_byte_size))
11027 // address = address+8;
11028 address = address + 8;
11036 // This instruciton loads a single extension register fronm memory, using an address from an ARM core register, with
11037 // an optional offset.
11039 EmulateInstructionARM::EmulateVLDR (const uint32_t opcode, ARMEncoding encoding)
11042 if ConditionPassed() then
11043 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(n);
11044 base = if n == 15 then Align(PC,4) else R[n];
11045 address = if add then (base + imm32) else (base - imm32);
11047 S[d] = MemA[address,4];
11049 word1 = MemA[address,4]; word2 = MemA[address+4,4];
11050 // Combine the word-aligned words in the correct order for current endianness.
11051 D[d] = if BigEndian() then word1:word2 else word2:word1;
11054 bool success = false;
11056 if (ConditionPassed (opcode))
11068 // single_reg = FALSE; add = (U == Ô1Õ); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
11069 single_reg = false;
11070 add = BitIsSet (opcode, 23);
11071 imm32 = Bits32 (opcode, 7, 0) << 2;
11073 // d = UInt(D:Vd); n = UInt(Rn);
11074 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11075 n = Bits32 (opcode, 19, 16);
11081 // single_reg = TRUE; add = (U == Ô1Õ); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
11083 add = BitIsSet (opcode, 23);
11084 imm32 = Bits32 (opcode, 7, 0) << 2;
11086 // d = UInt(Vd:D); n = UInt(Rn);
11087 d = (Bits32 (opcode, 15, 12) << 1) | Bit32 (opcode, 22);
11088 n = Bits32 (opcode, 19, 16);
11095 RegisterInfo base_reg;
11096 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
11098 uint32_t Rn = ReadCoreReg (n, &success);
11102 // base = if n == 15 then Align(PC,4) else R[n];
11105 base = AlignPC (Rn);
11109 // address = if add then (base + imm32) else (base - imm32);
11112 address = base + imm32;
11114 address = base - imm32;
11116 const uint32_t addr_byte_size = GetAddressByteSize();
11117 uint32_t start_reg = single_reg ? dwarf_s0 : dwarf_d0;
11119 EmulateInstruction::Context context;
11120 context.type = eContextRegisterLoad;
11121 context.SetRegisterPlusOffset (base_reg, address - base);
11125 // S[d] = MemA[address,4];
11126 uint32_t data = MemARead (context, address, addr_byte_size, 0, &success);
11130 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, start_reg + d, data))
11135 // word1 = MemA[address,4]; word2 = MemA[address+4,4];
11136 uint32_t word1 = MemARead (context, address, addr_byte_size, 0, &success);
11140 context.SetRegisterPlusOffset (base_reg, (address + 4) - base);
11141 uint32_t word2 = MemARead (context, address + 4, addr_byte_size, 0, &success);
11144 // // Combine the word-aligned words in the correct order for current endianness.
11145 // D[d] = if BigEndian() then word1:word2 else word2:word1;
11147 if (GetByteOrder() == eByteOrderBig)
11150 data64 = (data64 << 32) | word2;
11155 data64 = (data64 << 32) | word1;
11158 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, start_reg + d, data64))
11166 // This instruction stores a signle extension register to memory, using an address from an ARM core register, with an
11167 // optional offset.
11169 EmulateInstructionARM::EmulateVSTR (const uint32_t opcode, ARMEncoding encoding)
11172 if ConditionPassed() then
11173 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(n);
11174 address = if add then (R[n] + imm32) else (R[n] - imm32);
11176 MemA[address,4] = S[d];
11178 // Store as two word-aligned words in the correct order for current endianness.
11179 MemA[address,4] = if BigEndian() then D[d]<63:32> else D[d]<31:0>;
11180 MemA[address+4,4] = if BigEndian() then D[d]<31:0> else D[d]<63:32>;
11183 bool success = false;
11185 if (ConditionPassed (opcode))
11197 // single_reg = FALSE; add = (U == Ô1Õ); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
11198 single_reg = false;
11199 add = BitIsSet (opcode, 23);
11200 imm32 = Bits32 (opcode, 7, 0) << 2;
11202 // d = UInt(D:Vd); n = UInt(Rn);
11203 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11204 n = Bits32 (opcode, 19, 16);
11206 // if n == 15 && CurrentInstrSet() != InstrSet_ARM then UNPREDICTABLE;
11207 if ((n == 15) && (CurrentInstrSet() != eModeARM))
11214 // single_reg = TRUE; add = (U == Ô1Õ); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
11216 add = BitIsSet (opcode, 23);
11217 imm32 = Bits32 (opcode, 7, 0) << 2;
11219 // d = UInt(Vd:D); n = UInt(Rn);
11220 d = (Bits32 (opcode, 15, 12) << 1) | Bit32 (opcode, 22);
11221 n = Bits32 (opcode, 19, 16);
11223 // if n == 15 && CurrentInstrSet() != InstrSet_ARM then UNPREDICTABLE;
11224 if ((n == 15) && (CurrentInstrSet() != eModeARM))
11233 RegisterInfo base_reg;
11234 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
11236 uint32_t Rn = ReadCoreReg (n, &success);
11240 // address = if add then (R[n] + imm32) else (R[n] - imm32);
11243 address = Rn + imm32;
11245 address = Rn - imm32;
11247 const uint32_t addr_byte_size = GetAddressByteSize();
11248 uint32_t start_reg = single_reg ? dwarf_s0 : dwarf_d0;
11250 RegisterInfo data_reg;
11251 GetRegisterInfo (eRegisterKindDWARF, start_reg + d, data_reg);
11252 EmulateInstruction::Context context;
11253 context.type = eContextRegisterStore;
11254 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
11258 // MemA[address,4] = S[d];
11259 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, start_reg + d, 0, &success);
11263 if (!MemAWrite (context, address, data, addr_byte_size))
11268 // // Store as two word-aligned words in the correct order for current endianness.
11269 // MemA[address,4] = if BigEndian() then D[d]<63:32> else D[d]<31:0>;
11270 // MemA[address+4,4] = if BigEndian() then D[d]<31:0> else D[d]<63:32>;
11271 uint64_t data = ReadRegisterUnsigned (eRegisterKindDWARF, start_reg + d, 0, &success);
11275 if (GetByteOrder() == eByteOrderBig)
11277 if (!MemAWrite (context, address, Bits64 (data, 63, 32), addr_byte_size))
11280 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
11281 if (!MemAWrite (context, address + 4, Bits64 (data, 31, 0), addr_byte_size))
11286 if (!MemAWrite (context, address, Bits64 (data, 31, 0), addr_byte_size))
11289 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
11290 if (!MemAWrite (context, address + 4, Bits64 (data, 63, 32), addr_byte_size))
11298 // A8.6.307 VLDI1 (multiple single elements)
11299 // This instruction loads elements from memory into one, two, three or four registers, without de-interleaving. Every
11300 // element of each register is loaded.
11302 EmulateInstructionARM::EmulateVLD1Multiple (const uint32_t opcode, ARMEncoding encoding)
11305 if ConditionPassed() then
11306 EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
11307 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11308 if wback then R[n] = R[n] + (if register_index then R[m] else 8*regs);
11309 for r = 0 to regs-1
11310 for e = 0 to elements-1
11311 Elem[D[d+r],e,esize] = MemU[address,ebytes];
11312 address = address + ebytes;
11315 bool success = false;
11317 if (ConditionPassed (opcode))
11320 uint32_t alignment;
11328 bool register_index;
11337 // regs = 1; if align<1> == Ô1Õ then UNDEFINED;
11339 // regs = 2; if align == Ô11Õ then UNDEFINED;
11341 // regs = 3; if align<1> == Ô1Õ then UNDEFINED;
11345 // SEE ÒRelated encodingsÓ;
11346 uint32_t type = Bits32 (opcode, 11, 8);
11347 uint32_t align = Bits32 (opcode, 5, 4);
11348 if (type == 7) // '0111'
11351 if (BitIsSet (align, 1))
11354 else if (type == 10) // '1010'
11361 else if (type == 6) // '0110'
11364 if (BitIsSet (align, 1))
11367 else if (type == 2) // '0010'
11374 // alignment = if align == Ô00Õ then 1 else 4 << UInt(align);
11378 alignment = 4 << align;
11380 // ebytes = 1 << UInt(size); esize = 8 * ebytes; elements = 8 DIV ebytes;
11381 ebytes = 1 << Bits32 (opcode, 7, 6);
11382 esize = 8 * ebytes;
11383 elements = 8 / ebytes;
11385 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11386 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11387 n = Bits32 (opcode, 19, 15);
11388 m = Bits32 (opcode, 3, 0);
11390 // wback = (m != 15); register_index = (m != 15 && m != 13);
11392 register_index = ((m != 15) && (m != 13));
11394 // if d+regs > 32 then UNPREDICTABLE;
11395 if ((d + regs) > 32)
11404 RegisterInfo base_reg;
11405 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
11407 uint32_t Rn = ReadCoreReg (n, &success);
11411 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11412 addr_t address = Rn;
11413 if ((address % alignment) != 0)
11416 EmulateInstruction::Context context;
11417 // if wback then R[n] = R[n] + (if register_index then R[m] else 8*regs);
11420 uint32_t Rm = ReadCoreReg (m, &success);
11425 if (register_index)
11430 uint32_t value = Rn + offset;
11431 context.type = eContextAdjustBaseRegister;
11432 context.SetRegisterPlusOffset (base_reg, offset);
11434 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, value))
11439 // for r = 0 to regs-1
11440 for (uint32_t r = 0; r < regs; ++r)
11442 // for e = 0 to elements-1
11443 uint64_t assembled_data = 0;
11444 for (uint32_t e = 0; e < elements; ++e)
11446 // Elem[D[d+r],e,esize] = MemU[address,ebytes];
11447 context.type = eContextRegisterLoad;
11448 context.SetRegisterPlusOffset (base_reg, address - Rn);
11449 uint64_t data = MemURead (context, address, ebytes, 0, &success);
11453 assembled_data = (data << (e * esize)) | assembled_data; // New data goes to the left of existing data
11455 // address = address + ebytes;
11456 address = address + ebytes;
11458 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_d0 + d + r, assembled_data))
11465 // A8.6.308 VLD1 (single element to one lane)
11468 EmulateInstructionARM::EmulateVLD1Single (const uint32_t opcode, const ARMEncoding encoding)
11471 if ConditionPassed() then
11472 EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
11473 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11474 if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11475 Elem[D[d],index,esize] = MemU[address,ebytes];
11478 bool success = false;
11480 if (ConditionPassed (opcode))
11485 uint32_t alignment;
11490 bool register_index;
11497 uint32_t size = Bits32 (opcode, 11, 10);
11498 uint32_t index_align = Bits32 (opcode, 7, 4);
11499 // if size == Ô11Õ then SEE VLD1 (single element to all lanes);
11501 return EmulateVLD1SingleAll (opcode, encoding);
11503 if (size == 0) // when '00'
11505 // if index_align<0> != Ô0Õ then UNDEFINED;
11506 if (BitIsClear (index_align, 0))
11509 // ebytes = 1; esize = 8; index = UInt(index_align<3:1>); alignment = 1;
11512 index = Bits32 (index_align, 3, 1);
11515 else if (size == 1) // when Ô01Õ
11517 // if index_align<1> != Ô0Õ then UNDEFINED;
11518 if (BitIsClear (index_align, 1))
11521 // ebytes = 2; esize = 16; index = UInt(index_align<3:2>);
11524 index = Bits32 (index_align, 3, 2);
11526 // alignment = if index_align<0> == Ô0Õ then 1 else 2;
11527 if (BitIsClear (index_align, 0))
11532 else if (size == 2) // when Ô10Õ
11534 // if index_align<2> != Ô0Õ then UNDEFINED;
11535 if (BitIsClear (index_align, 2))
11538 // if index_align<1:0> != Ô00Õ && index_align<1:0> != Ô11Õ then UNDEFINED;
11539 if ((Bits32 (index_align, 1, 0) != 0) && (Bits32 (index_align, 1, 0) != 3))
11542 // ebytes = 4; esize = 32; index = UInt(index_align<3>);
11545 index = Bit32 (index_align, 3);
11547 // alignment = if index_align<1:0> == Ô00Õ then 1 else 4;
11548 if (Bits32 (index_align, 1, 0) == 0)
11557 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11558 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11559 n = Bits32 (opcode, 19, 16);
11560 m = Bits32 (opcode, 3, 0);
11562 // wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 then UNPREDICTABLE;
11564 register_index = ((m != 15) && (m != 13));
11576 RegisterInfo base_reg;
11577 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
11579 uint32_t Rn = ReadCoreReg (n, &success);
11583 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11584 addr_t address = Rn;
11585 if ((address % alignment) != 0)
11588 EmulateInstruction::Context context;
11589 // if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11592 uint32_t Rm = ReadCoreReg (m, &success);
11597 if (register_index)
11602 uint32_t value = Rn + offset;
11604 context.type = eContextAdjustBaseRegister;
11605 context.SetRegisterPlusOffset (base_reg, offset);
11607 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, value))
11611 // Elem[D[d],index,esize] = MemU[address,ebytes];
11612 uint32_t element = MemURead (context, address, esize, 0, &success);
11616 element = element << (index * esize);
11618 uint64_t reg_data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_d0 + d, 0, &success);
11622 uint64_t all_ones = -1;
11623 uint64_t mask = all_ones << ((index+1) * esize); // mask is all 1's to left of where 'element' goes, & all 0's
11624 // at element & to the right of element.
11626 mask = mask | Bits64 (all_ones, (index * esize) - 1, 0); // add 1's to the right of where 'element' goes.
11627 // now mask should be 0's where element goes & 1's
11628 // everywhere else.
11630 uint64_t masked_reg = reg_data & mask; // Take original reg value & zero out 'element' bits
11631 reg_data = masked_reg & element; // Put 'element' into those bits in reg_data.
11633 context.type = eContextRegisterLoad;
11634 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, reg_data))
11640 // A8.6.391 VST1 (multiple single elements)
11641 // Vector Store (multiple single elements) stores elements to memory from one, two, three, or four regsiters, without
11642 // interleaving. Every element of each register is stored.
11644 EmulateInstructionARM::EmulateVST1Multiple (const uint32_t opcode, ARMEncoding encoding)
11647 if ConditionPassed() then
11648 EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
11649 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11650 if wback then R[n] = R[n] + (if register_index then R[m] else 8*regs);
11651 for r = 0 to regs-1
11652 for e = 0 to elements-1
11653 MemU[address,ebytes] = Elem[D[d+r],e,esize];
11654 address = address + ebytes;
11657 bool success = false;
11659 if (ConditionPassed (opcode))
11662 uint32_t alignment;
11670 bool register_index;
11677 uint32_t type = Bits32 (opcode, 11, 8);
11678 uint32_t align = Bits32 (opcode, 5, 4);
11681 if (type == 7) // when Ô0111Õ
11683 // regs = 1; if align<1> == Ô1Õ then UNDEFINED;
11685 if (BitIsSet (align, 1))
11688 else if (type == 10) // when Ô1010Õ
11690 // regs = 2; if align == Ô11Õ then UNDEFINED;
11695 else if (type == 6) // when Ô0110Õ
11697 // regs = 3; if align<1> == Ô1Õ then UNDEFINED;
11699 if (BitIsSet (align, 1))
11702 else if (type == 2) // when Ô0010Õ
11706 // SEE ÒRelated encodingsÓ;
11709 // alignment = if align == Ô00Õ then 1 else 4 << UInt(align);
11713 alignment = 4 << align;
11715 // ebytes = 1 << UInt(size); esize = 8 * ebytes; elements = 8 DIV ebytes;
11716 ebytes = 1 << Bits32 (opcode,7, 6);
11717 esize = 8 * ebytes;
11718 elements = 8 / ebytes;
11720 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11721 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11722 n = Bits32 (opcode, 19, 16);
11723 m = Bits32 (opcode, 3, 0);
11725 // wback = (m != 15); register_index = (m != 15 && m != 13);
11727 register_index = ((m != 15) && (m != 13));
11729 // if d+regs > 32 then UNPREDICTABLE; if n == 15 then UNPREDICTABLE;
11730 if ((d + regs) > 32)
11743 RegisterInfo base_reg;
11744 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
11746 uint32_t Rn = ReadCoreReg (n, &success);
11750 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11751 addr_t address = Rn;
11752 if ((address % alignment) != 0)
11755 EmulateInstruction::Context context;
11756 // if wback then R[n] = R[n] + (if register_index then R[m] else 8*regs);
11759 uint32_t Rm = ReadCoreReg (m, &success);
11764 if (register_index)
11769 context.type = eContextAdjustBaseRegister;
11770 context.SetRegisterPlusOffset (base_reg, offset);
11772 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn + offset))
11776 RegisterInfo data_reg;
11777 context.type = eContextRegisterStore;
11778 // for r = 0 to regs-1
11779 for (uint32_t r = 0; r < regs; ++r)
11781 GetRegisterInfo (eRegisterKindDWARF, dwarf_d0 + d + r, data_reg);
11782 uint64_t register_data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_d0 + d + r, 0, &success);
11786 // for e = 0 to elements-1
11787 for (uint32_t e = 0; e < elements; ++e)
11789 // MemU[address,ebytes] = Elem[D[d+r],e,esize];
11790 uint64_t word = Bits64 (register_data, ((e + 1) * esize) - 1, e * esize);
11792 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
11793 if (!MemUWrite (context, address, word, ebytes))
11796 // address = address + ebytes;
11797 address = address + ebytes;
11804 // A8.6.392 VST1 (single element from one lane)
11805 // This instruction stores one element to memory from one element of a register.
11807 EmulateInstructionARM::EmulateVST1Single (const uint32_t opcode, ARMEncoding encoding)
11810 if ConditionPassed() then
11811 EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
11812 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11813 if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11814 MemU[address,ebytes] = Elem[D[d],index,esize];
11817 bool success = false;
11819 if (ConditionPassed (opcode))
11824 uint32_t alignment;
11829 bool register_index;
11836 uint32_t size = Bits32 (opcode, 11, 10);
11837 uint32_t index_align = Bits32 (opcode, 7, 4);
11839 // if size == Ô11Õ then UNDEFINED;
11844 if (size == 0) // when Ô00Õ
11846 // if index_align<0> != Ô0Õ then UNDEFINED;
11847 if (BitIsClear (index_align, 0))
11849 // ebytes = 1; esize = 8; index = UInt(index_align<3:1>); alignment = 1;
11852 index = Bits32 (index_align, 3, 1);
11855 else if (size == 1) // when Ô01Õ
11857 // if index_align<1> != Ô0Õ then UNDEFINED;
11858 if (BitIsClear (index_align, 1))
11861 // ebytes = 2; esize = 16; index = UInt(index_align<3:2>);
11864 index = Bits32 (index_align, 3, 2);
11866 // alignment = if index_align<0> == Ô0Õ then 1 else 2;
11867 if (BitIsClear (index_align, 0))
11872 else if (size == 2) // when Ô10Õ
11874 // if index_align<2> != Ô0Õ then UNDEFINED;
11875 if (BitIsClear (index_align, 2))
11878 // if index_align<1:0> != Ô00Õ && index_align<1:0> != Ô11Õ then UNDEFINED;
11879 if ((Bits32 (index_align, 1, 0) != 0) && (Bits32 (index_align, 1, 0) != 3))
11882 // ebytes = 4; esize = 32; index = UInt(index_align<3>);
11885 index = Bit32 (index_align, 3);
11887 // alignment = if index_align<1:0> == Ô00Õ then 1 else 4;
11888 if (Bits32 (index_align, 1, 0) == 0)
11897 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11898 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11899 n = Bits32 (opcode, 19, 16);
11900 m = Bits32 (opcode, 3, 0);
11902 // wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 then UNPREDICTABLE;
11904 register_index = ((m != 15) && (m != 13));
11915 RegisterInfo base_reg;
11916 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
11918 uint32_t Rn = ReadCoreReg (n, &success);
11922 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11923 addr_t address = Rn;
11924 if ((address % alignment) != 0)
11927 EmulateInstruction::Context context;
11928 // if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11931 uint32_t Rm = ReadCoreReg (m, &success);
11936 if (register_index)
11941 context.type = eContextAdjustBaseRegister;
11942 context.SetRegisterPlusOffset (base_reg, offset);
11944 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn + offset))
11948 // MemU[address,ebytes] = Elem[D[d],index,esize];
11949 uint64_t register_data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_d0 + d, 0, &success);
11953 uint64_t word = Bits64 (register_data, ((index + 1) * esize) - 1, index * esize);
11955 RegisterInfo data_reg;
11956 GetRegisterInfo (eRegisterKindDWARF, dwarf_d0 + d, data_reg);
11957 context.type = eContextRegisterStore;
11958 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
11960 if (!MemUWrite (context, address, word, ebytes))
11966 // A8.6.309 VLD1 (single element to all lanes)
11967 // This instruction loads one element from memory into every element of one or two vectors.
11969 EmulateInstructionARM::EmulateVLD1SingleAll (const uint32_t opcode, const ARMEncoding encoding)
11972 if ConditionPassed() then
11973 EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
11974 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11975 if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11976 replicated_element = Replicate(MemU[address,ebytes], elements);
11977 for r = 0 to regs-1
11978 D[d+r] = replicated_element;
11981 bool success = false;
11983 if (ConditionPassed (opcode))
11988 uint32_t alignment;
11993 bool register_index;
12000 //if size == Ô11Õ || (size == Ô00Õ && a == Ô1Õ) then UNDEFINED;
12001 uint32_t size = Bits32 (opcode, 7, 6);
12002 if ((size == 3) || ((size == 0) && BitIsSet (opcode, 4)))
12005 //ebytes = 1 << UInt(size); elements = 8 DIV ebytes; regs = if T == Ô0Õ then 1 else 2;
12006 ebytes = 1 << size;
12007 elements = 8 / ebytes;
12008 if (BitIsClear (opcode, 5))
12013 //alignment = if a == Ô0Õ then 1 else ebytes;
12014 if (BitIsClear (opcode, 4))
12017 alignment = ebytes;
12019 //d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
12020 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
12021 n = Bits32 (opcode, 19, 16);
12022 m = Bits32 (opcode, 3, 0);
12024 //wback = (m != 15); register_index = (m != 15 && m != 13);
12026 register_index = ((m != 15) && (m != 13));
12028 //if d+regs > 32 then UNPREDICTABLE; if n == 15 then UNPREDICTABLE;
12029 if ((d + regs) > 32)
12041 RegisterInfo base_reg;
12042 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
12044 uint32_t Rn = ReadCoreReg (n, &success);
12048 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
12049 addr_t address = Rn;
12050 if ((address % alignment) != 0)
12053 EmulateInstruction::Context context;
12054 // if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
12057 uint32_t Rm = ReadCoreReg (m, &success);
12062 if (register_index)
12067 context.type = eContextAdjustBaseRegister;
12068 context.SetRegisterPlusOffset (base_reg, offset);
12070 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn + offset))
12074 // replicated_element = Replicate(MemU[address,ebytes], elements);
12076 context.type = eContextRegisterLoad;
12077 uint64_t word = MemURead (context, address, ebytes, 0, &success);
12081 uint64_t replicated_element = 0;
12082 uint32_t esize = ebytes * 8;
12083 for (uint32_t e = 0; e < elements; ++e)
12084 replicated_element = (replicated_element << esize) | Bits64 (word, esize - 1, 0);
12086 // for r = 0 to regs-1
12087 for (uint32_t r = 0; r < regs; ++r)
12089 // D[d+r] = replicated_element;
12090 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_d0 + d + r, replicated_element))
12097 // B6.2.13 SUBS PC, LR and related instructions
12098 //The SUBS PC, LR, #<const? instruction provides an exception return without the use of the stack. It subtracts the
12099 // immediate constant from the LR, branches to the resulting address, and also copies the SPSR to the CPSR.
12101 EmulateInstructionARM::EmulateSUBSPcLrEtc (const uint32_t opcode, const ARMEncoding encoding)
12104 if ConditionPassed() then
12105 EncodingSpecificOperations();
12106 if CurrentInstrSet() == InstrSet_ThumbEE then
12108 operand2 = if register_form then Shift(R[m], shift_t, shift_n, APSR.C) else imm32;
12110 when Ô0000Õ result = R[n] AND operand2; // AND
12111 when Ô0001Õ result = R[n] EOR operand2; // EOR
12112 when Ô0010Õ (result, -, -) = AddWithCarry(R[n], NOT(operand2), Ô1Õ); // SUB
12113 when Ô0011Õ (result, -, -) = AddWithCarry(NOT(R[n]), operand2, Ô1Õ); // RSB
12114 when Ô0100Õ (result, -, -) = AddWithCarry(R[n], operand2, Ô0Õ); // ADD
12115 when Ô0101Õ (result, -, -) = AddWithCarry(R[n], operand2, APSR.c); // ADC
12116 when Ô0110Õ (result, -, -) = AddWithCarry(R[n], NOT(operand2), APSR.C); // SBC
12117 when Ô0111Õ (result, -, -) = AddWithCarry(NOT(R[n]), operand2, APSR.C); // RSC
12118 when Ô1100Õ result = R[n] OR operand2; // ORR
12119 when Ô1101Õ result = operand2; // MOV
12120 when Ô1110Õ result = R[n] AND NOT(operand2); // BIC
12121 when Ô1111Õ result = NOT(operand2); // MVN
12122 CPSRWriteByInstr(SPSR[], Ô1111Õ, TRUE);
12123 BranchWritePC(result);
12126 bool success = false;
12128 if (ConditionPassed (opcode))
12133 bool register_form;
12134 ARM_ShifterType shift_t;
12141 // if CurrentInstrSet() == InstrSet_ThumbEE then UNPREDICTABLE
12142 // n = 14; imm32 = ZeroExtend(imm8, 32); register_form = FALSE; opcode = Ô0010Õ; // = SUB
12144 imm32 = Bits32 (opcode, 7, 0);
12145 register_form = false;
12148 // if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
12149 if (InITBlock() && !LastInITBlock())
12155 // n = UInt(Rn); imm32 = ARMExpandImm(imm12); register_form = FALSE;
12156 n = Bits32 (opcode, 19, 16);
12157 imm32 = ARMExpandImm (opcode);
12158 register_form = false;
12159 code = Bits32 (opcode, 24, 21);
12164 // n = UInt(Rn); m = UInt(Rm); register_form = TRUE;
12165 n = Bits32 (opcode, 19, 16);
12166 m = Bits32 (opcode, 3, 0);
12167 register_form = true;
12169 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
12170 shift_n = DecodeImmShiftARM (opcode, shift_t);
12178 // operand2 = if register_form then Shift(R[m], shift_t, shift_n, APSR.C) else imm32;
12182 uint32_t Rm = ReadCoreReg (m, &success);
12186 operand2 = Shift (Rm, shift_t, shift_n, APSR_C, &success);
12195 uint32_t Rn = ReadCoreReg (n, &success);
12199 AddWithCarryResult result;
12204 case 0: // when Ô0000Õ
12205 // result = R[n] AND operand2; // AND
12206 result.result = Rn & operand2;
12209 case 1: // when Ô0001Õ
12210 // result = R[n] EOR operand2; // EOR
12211 result.result = Rn ^ operand2;
12214 case 2: // when Ô0010Õ
12215 // (result, -, -) = AddWithCarry(R[n], NOT(operand2), Ô1Õ); // SUB
12216 result = AddWithCarry (Rn, ~(operand2), 1);
12219 case 3: // when Ô0011Õ
12220 // (result, -, -) = AddWithCarry(NOT(R[n]), operand2, Ô1Õ); // RSB
12221 result = AddWithCarry (~(Rn), operand2, 1);
12224 case 4: // when Ô0100Õ
12225 // (result, -, -) = AddWithCarry(R[n], operand2, Ô0Õ); // ADD
12226 result = AddWithCarry (Rn, operand2, 0);
12229 case 5: // when Ô0101Õ
12230 // (result, -, -) = AddWithCarry(R[n], operand2, APSR.c); // ADC
12231 result = AddWithCarry (Rn, operand2, APSR_C);
12234 case 6: // when Ô0110Õ
12235 // (result, -, -) = AddWithCarry(R[n], NOT(operand2), APSR.C); // SBC
12236 result = AddWithCarry (Rn, ~(operand2), APSR_C);
12239 case 7: // when Ô0111Õ
12240 // (result, -, -) = AddWithCarry(NOT(R[n]), operand2, APSR.C); // RSC
12241 result = AddWithCarry (~(Rn), operand2, APSR_C);
12244 case 10: // when Ô1100Õ
12245 // result = R[n] OR operand2; // ORR
12246 result.result = Rn | operand2;
12249 case 11: // when Ô1101Õ
12250 // result = operand2; // MOV
12251 result.result = operand2;
12254 case 12: // when Ô1110Õ
12255 // result = R[n] AND NOT(operand2); // BIC
12256 result.result = Rn & ~(operand2);
12259 case 15: // when Ô1111Õ
12260 // result = NOT(operand2); // MVN
12261 result.result = ~(operand2);
12267 // CPSRWriteByInstr(SPSR[], Ô1111Õ, TRUE);
12269 // For now, in emulation mode, we don't have access to the SPSR, so we will use the CPSR instead, and hope for
12271 uint32_t spsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_cpsr, 0, &success);
12275 CPSRWriteByInstr (spsr, 15, true);
12277 // BranchWritePC(result);
12278 EmulateInstruction::Context context;
12279 context.type = eContextAdjustPC;
12280 context.SetImmediate (result.result);
12282 BranchWritePC (context, result.result);
12287 EmulateInstructionARM::ARMOpcode*
12288 EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode, uint32_t arm_isa)
12293 //----------------------------------------------------------------------
12294 // Prologue instructions
12295 //----------------------------------------------------------------------
12297 // push register(s)
12298 { 0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulatePUSH, "push <registers>" },
12299 { 0x0fff0fff, 0x052d0004, ARMvAll, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulatePUSH, "push <register>" },
12301 // set r7 to point to a stack offset
12302 { 0x0ffff000, 0x028d7000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDRdSPImm, "add r7, sp, #<const>" },
12303 { 0x0ffff000, 0x024c7000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBR7IPImm, "sub r7, ip, #<const>"},
12304 // copy the stack pointer to ip
12305 { 0x0fffffff, 0x01a0c00d, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdSP, "mov ip, sp" },
12306 { 0x0ffff000, 0x028dc000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDRdSPImm, "add ip, sp, #<const>" },
12307 { 0x0ffff000, 0x024dc000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBIPSPImm, "sub ip, sp, #<const>"},
12309 // adjust the stack pointer
12310 { 0x0ffff000, 0x024dd000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub sp, sp, #<const>"},
12311 { 0x0fef0010, 0x004d0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPReg, "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}" },
12313 // push one register
12314 // if Rn == '1101' && imm12 == '000000000100' then SEE PUSH;
12315 { 0x0e5f0000, 0x040d0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRRtSP, "str Rt, [sp, #-imm12]!" },
12317 // vector push consecutive extension register(s)
12318 { 0x0fbf0f00, 0x0d2d0b00, ARMV6T2_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"},
12319 { 0x0fbf0f00, 0x0d2d0a00, ARMV6T2_ABOVE, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"},
12321 //----------------------------------------------------------------------
12322 // Epilogue instructions
12323 //----------------------------------------------------------------------
12325 { 0x0fff0000, 0x08bd0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulatePOP, "pop <registers>"},
12326 { 0x0fff0fff, 0x049d0004, ARMvAll, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulatePOP, "pop <register>"},
12327 { 0x0fbf0f00, 0x0cbd0b00, ARMV6T2_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"},
12328 { 0x0fbf0f00, 0x0cbd0a00, ARMV6T2_ABOVE, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"},
12330 //----------------------------------------------------------------------
12331 // Supervisor Call (previously Software Interrupt)
12332 //----------------------------------------------------------------------
12333 { 0x0f000000, 0x0f000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSVC, "svc #imm24"},
12335 //----------------------------------------------------------------------
12336 // Branch instructions
12337 //----------------------------------------------------------------------
12338 { 0x0f000000, 0x0a000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateB, "b #imm24"},
12339 // To resolve ambiguity, "blx <label>" should come before "bl <label>".
12340 { 0xfe000000, 0xfa000000, ARMV5_ABOVE, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"},
12341 { 0x0f000000, 0x0b000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"},
12342 { 0x0ffffff0, 0x012fff30, ARMV5_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"},
12343 // for example, "bx lr"
12344 { 0x0ffffff0, 0x012fff10, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"},
12346 { 0x0ffffff0, 0x012fff20, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"},
12348 //----------------------------------------------------------------------
12349 // Data-processing instructions
12350 //----------------------------------------------------------------------
12352 { 0x0fe00000, 0x02a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #const"},
12354 { 0x0fe00010, 0x00a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCReg, "adc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12356 { 0x0fe00000, 0x02800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDImmARM, "add{s}<c> <Rd>, <Rn>, #const"},
12358 { 0x0fe00010, 0x00800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDReg, "add{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12359 // add (register-shifted register)
12360 { 0x0fe00090, 0x00800010, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDRegShift, "add{s}<c> <Rd>, <Rn>, <Rm>, <type> <RS>"},
12362 { 0x0fff0000, 0x028f0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12363 { 0x0fff0000, 0x024f0000, ARMvAll, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"},
12365 { 0x0fe00000, 0x02000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #const"},
12367 { 0x0fe00010, 0x00000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12369 { 0x0fe00000, 0x03c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #const"},
12371 { 0x0fe00010, 0x01c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICReg, "bic{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12373 { 0x0fe00000, 0x02200000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #const"},
12375 { 0x0fe00010, 0x00200000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12377 { 0x0fe00000, 0x03800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #const"},
12379 { 0x0fe00010, 0x01800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12381 { 0x0fe00000, 0x02600000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s}<c> <Rd>, <Rn>, #<const>"},
12383 { 0x0fe00010, 0x00600000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12385 { 0x0fe00000, 0x02e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSCImm, "rsc{s}<c> <Rd>, <Rn>, #<const>"},
12387 { 0x0fe00010, 0x00e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSCReg, "rsc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12389 { 0x0fe00000, 0x02c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
12391 { 0x0fe00010, 0x00c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12392 // sub (immediate, ARM)
12393 { 0x0fe00000, 0x02400000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBImmARM, "sub{s}<c> <Rd>, <Rn>, #<const>"},
12394 // sub (sp minus immediate)
12395 { 0x0fef0000, 0x024d0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}<c> <Rd>, sp, #<const>"},
12397 { 0x0fe00010, 0x00400000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBReg, "sub{s}<c> <Rd>, <Rn>, <Rm>{,<shift>}"},
12399 { 0x0ff0f000, 0x03300000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq<c> <Rn>, #const"},
12401 { 0x0ff0f010, 0x01300000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"},
12403 { 0x0ff0f000, 0x03100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tst<c> <Rn>, #const"},
12405 { 0x0ff0f010, 0x01100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst<c> <Rn>, <Rm> {,<shift>}"},
12408 { 0x0fef0000, 0x03a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}<c> <Rd>, #<const>"},
12409 { 0x0ff00000, 0x03000000, ARMV6T2_ABOVE, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "movw<c> <Rd>, #<imm16>" },
12411 { 0x0fef0ff0, 0x01a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c> <Rd>, <Rm>"},
12413 { 0x0fef0000, 0x03e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMVNImm, "mvn{s}<c> <Rd>, #<const>"},
12415 { 0x0fef0010, 0x01e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s}<c> <Rd>, <Rm> {,<shift>}"},
12417 { 0x0ff0f000, 0x03700000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNImm, "cmn<c> <Rn>, #<const>"},
12419 { 0x0ff0f010, 0x01700000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"},
12421 { 0x0ff0f000, 0x03500000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMPImm, "cmp<c> <Rn>, #<const>"},
12423 { 0x0ff0f010, 0x01500000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm> {,<shift>}"},
12425 { 0x0fef0070, 0x01a00040, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s}<c> <Rd>, <Rm>, #imm"},
12427 { 0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c> <Rd>, <Rn>, <Rm>"},
12429 { 0x0fef0070, 0x01a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c> <Rd>, <Rm>, #imm"},
12431 { 0x0fef00f0, 0x01a00010, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c> <Rd>, <Rn>, <Rm>"},
12433 { 0x0fef0070, 0x01a00020, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c> <Rd>, <Rm>, #imm"},
12435 { 0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c> <Rd>, <Rn>, <Rm>"},
12436 // rrx is a special case encoding of ror (immediate)
12437 { 0x0fef0ff0, 0x01a00060, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRRX, "rrx{s}<c> <Rd>, <Rm>"},
12439 { 0x0fef0070, 0x01a00060, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORImm, "ror{s}<c> <Rd>, <Rm>, #imm"},
12441 { 0x0fef00f0, 0x01a00070, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORReg, "ror{s}<c> <Rd>, <Rn>, <Rm>"},
12443 { 0x0fe000f0, 0x00000090, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMUL, "mul{s}<c> <Rd>,<R>,<Rm>" },
12445 // subs pc, lr and related instructions
12446 { 0x0e10f000, 0x0210f000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPcLrEtc, "<opc>S<c> PC,#<const> | <Rn>,#<const>" },
12447 { 0x0e10f010, 0x0010f000, ARMvAll, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPcLrEtc, "<opc>S<c> PC,<Rn>,<Rm{,<shift>}" },
12449 //----------------------------------------------------------------------
12450 // Load instructions
12451 //----------------------------------------------------------------------
12452 { 0x0fd00000, 0x08900000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" },
12453 { 0x0fd00000, 0x08100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDMDA, "ldmda<c> <Rn>{!} <registers>" },
12454 { 0x0fd00000, 0x09100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" },
12455 { 0x0fd00000, 0x09900000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDMIB, "ldmib<c> <Rn<{!} <registers>" },
12456 { 0x0e500000, 0x04100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRImmediateARM, "ldr<c> <Rt> [<Rn> {#+/-<imm12>}]" },
12457 { 0x0e500010, 0x06100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt> [<Rn> +/-<Rm> {<shift>}] {!}" },
12458 { 0x0e5f0000, 0x045f0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>, [...]"},
12459 { 0xfe500010, 0x06500000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>, [<Rn>,+/-<Rm>{, <shift>}]{!}" },
12460 { 0x0e5f00f0, 0x005f00b0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" },
12461 { 0x0e5000f0, 0x001000b0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12462 { 0x0e5000f0, 0x005000d0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>, [<Rn>{,#+/-<imm8>}]" },
12463 { 0x0e5f00f0, 0x005f00d0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBLiteral, "ldrsb<c> <Rt> <label>" },
12464 { 0x0e5000f0, 0x001000d0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12465 { 0x0e5000f0, 0x005000f0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>{,#+/-<imm8>}]"},
12466 { 0x0e5f00f0, 0x005f00f0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHLiteral, "ldrsh<c> <Rt>,<label>" },
12467 { 0x0e5000f0, 0x001000f0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12468 { 0x0e5000f0, 0x004000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm8>]!"},
12469 { 0x0e500ff0, 0x000000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDRegister, "ldrd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
12470 { 0x0e100f00, 0x0c100b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
12471 { 0x0e100f00, 0x0c100a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
12472 { 0x0f300f00, 0x0d100b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
12473 { 0x0f300f00, 0x0d100a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Sd>, [<Rn>{,#+/-<imm>}]"},
12474 { 0xffb00000, 0xf4200000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Multiple, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12475 { 0xffb00300, 0xf4a00000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Single, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12476 { 0xffb00f00, 0xf4a00c00, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1SingleAll, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12478 //----------------------------------------------------------------------
12479 // Store instructions
12480 //----------------------------------------------------------------------
12481 { 0x0fd00000, 0x08800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" },
12482 { 0x0fd00000, 0x08000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTMDA, "stmda<c> <Rn>{!} <registers>" },
12483 { 0x0fd00000, 0x09000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTMDB, "stmdb<c> <Rn>{!} <registers>" },
12484 { 0x0fd00000, 0x09800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTMIB, "stmib<c> <Rn>{!} <registers>" },
12485 { 0x0e500010, 0x06000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRRegister, "str<c> <Rt> [<Rn> +/-<Rm> {<shift>}]{!}" },
12486 { 0x0e5000f0, 0x000000b0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,+/-<Rm>[{!}" },
12487 { 0x0ff00ff0, 0x01800f90, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn>]"},
12488 { 0x0e500000, 0x04400000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRBImmARM, "strb<c> <Rt>,[<Rn>,#+/-<imm12>]!"},
12489 { 0x0e500000, 0x04000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRImmARM, "str<c> <Rt>,[<Rn>,#+/-<imm12>]!"},
12490 { 0x0e5000f0, 0x004000f0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDImm, "strd<c> <Rt>, <Rt2>, [<Rn> #+/-<imm8>]!"},
12491 { 0x0e500ff0, 0x000000f0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDReg, "strd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
12492 { 0x0e100f00, 0x0c000b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!} <list>"},
12493 { 0x0e100f00, 0x0c000a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!} <list>"},
12494 { 0x0f300f00, 0x0d000b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Dd> [<Rn>{,#+/-<imm>}]"},
12495 { 0x0f300f00, 0x0d000a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Sd> [<Rn>{,#+/-<imm>}]"},
12496 { 0xffb00000, 0xf4000000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Multiple, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12497 { 0xffb00300, 0xf4800000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Single, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12499 //----------------------------------------------------------------------
12500 // Other instructions
12501 //----------------------------------------------------------------------
12502 { 0x0fff00f0, 0x06af00f0, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>{,<rotation>}" },
12503 { 0x0fff00f0, 0x06bf0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>{,<rotation>}" },
12504 { 0x0fff00f0, 0x06ef0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>{,<rotation>}" },
12505 { 0x0fff00f0, 0x06ff0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>{,<rotation>}" },
12506 { 0xfe500000, 0xf8100000, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRFE, "rfe{<amode>} <Rn>{!}" }
12509 static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode);
12511 for (size_t i=0; i<k_num_arm_opcodes; ++i)
12513 if ((g_arm_opcodes[i].mask & opcode) == g_arm_opcodes[i].value &&
12514 (g_arm_opcodes[i].variants & arm_isa) != 0)
12515 return &g_arm_opcodes[i];
12521 EmulateInstructionARM::ARMOpcode*
12522 EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode, uint32_t arm_isa)
12526 g_thumb_opcodes[] =
12528 //----------------------------------------------------------------------
12529 // Prologue instructions
12530 //----------------------------------------------------------------------
12532 // push register(s)
12533 { 0xfffffe00, 0x0000b400, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulatePUSH, "push <registers>" },
12534 { 0xffff0000, 0xe92d0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulatePUSH, "push.w <registers>" },
12535 { 0xffff0fff, 0xf84d0d04, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulatePUSH, "push.w <register>" },
12537 // set r7 to point to a stack offset
12538 { 0xffffff00, 0x0000af00, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDRdSPImm, "add r7, sp, #imm" },
12539 // copy the stack pointer to r7
12540 { 0xffffffff, 0x0000466f, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVRdSP, "mov r7, sp" },
12541 // move from high register to low register (comes after "mov r7, sp" to resolve ambiguity)
12542 { 0xffffffc0, 0x00004640, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVLowHigh, "mov r0-r7, r8-r15" },
12544 // PC-relative load into register (see also EmulateADDSPRm)
12545 { 0xfffff800, 0x00004800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr <Rt>, [PC, #imm]"},
12547 // adjust the stack pointer
12548 { 0xffffff87, 0x00004485, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDSPRm, "add sp, <Rm>"},
12549 { 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSUBSPImm, "sub sp, sp, #imm"},
12550 { 0xfbef8f00, 0xf1ad0d00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub.w sp, sp, #<const>"},
12551 { 0xfbff8f00, 0xf2ad0d00, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw sp, sp, #imm12"},
12552 { 0xffef8000, 0xebad0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPReg, "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}" },
12554 // vector push consecutive extension register(s)
12555 { 0xffbf0f00, 0xed2d0b00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"},
12556 { 0xffbf0f00, 0xed2d0a00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"},
12558 //----------------------------------------------------------------------
12559 // Epilogue instructions
12560 //----------------------------------------------------------------------
12562 { 0xfffff800, 0x0000a800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDSPImm, "add<c> <Rd>, sp, #imm"},
12563 { 0xffffff80, 0x0000b000, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDSPImm, "add sp, #imm"},
12564 { 0xfffffe00, 0x0000bc00, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulatePOP, "pop <registers>"},
12565 { 0xffff0000, 0xe8bd0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulatePOP, "pop.w <registers>" },
12566 { 0xffff0fff, 0xf85d0d04, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulatePOP, "pop.w <register>" },
12567 { 0xffbf0f00, 0xecbd0b00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"},
12568 { 0xffbf0f00, 0xecbd0a00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"},
12570 //----------------------------------------------------------------------
12571 // Supervisor Call (previously Software Interrupt)
12572 //----------------------------------------------------------------------
12573 { 0xffffff00, 0x0000df00, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSVC, "svc #imm8"},
12575 //----------------------------------------------------------------------
12576 // If Then makes up to four following instructions conditional.
12577 //----------------------------------------------------------------------
12578 // The next 5 opcode _must_ come before the if then instruction
12579 { 0xffffffff, 0x0000bf00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateNop, "nop"},
12580 { 0xffffffff, 0x0000bf10, ARMV7_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateNop, "nop YIELD (yield hint)"},
12581 { 0xffffffff, 0x0000bf20, ARMV7_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateNop, "nop WFE (wait for event hint)"},
12582 { 0xffffffff, 0x0000bf30, ARMV7_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateNop, "nop WFI (wait for interrupt hint)"},
12583 { 0xffffffff, 0x0000bf40, ARMV7_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateNop, "nop SEV (send event hint)"},
12584 { 0xffffff00, 0x0000bf00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateIT, "it{<x>{<y>{<z>}}} <firstcond>"},
12586 //----------------------------------------------------------------------
12587 // Branch instructions
12588 //----------------------------------------------------------------------
12589 // To resolve ambiguity, "b<c> #imm8" should come after "svc #imm8".
12590 { 0xfffff000, 0x0000d000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateB, "b<c> #imm8 (outside IT)"},
12591 { 0xfffff800, 0x0000e000, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateB, "b<c> #imm11 (outside or last in IT)"},
12592 { 0xf800d000, 0xf0008000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateB, "b<c>.w #imm8 (outside IT)"},
12593 { 0xf800d000, 0xf0009000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateB, "b<c>.w #imm8 (outside or last in IT)"},
12595 { 0xf800d000, 0xf000d000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"},
12597 { 0xf800d001, 0xf000c000, ARMV5_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"},
12598 { 0xffffff87, 0x00004780, ARMV5_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"},
12599 // for example, "bx lr"
12600 { 0xffffff87, 0x00004700, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"},
12602 { 0xfff0ffff, 0xf3c08f00, ARMV5J_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"},
12603 // compare and branch
12604 { 0xfffff500, 0x0000b100, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCB, "cb{n}z <Rn>, <label>"},
12605 // table branch byte
12606 { 0xfff0fff0, 0xe8d0f000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTB, "tbb<c> <Rn>, <Rm>"},
12607 // table branch halfword
12608 { 0xfff0fff0, 0xe8d0f010, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTB, "tbh<c> <Rn>, <Rm>, lsl #1"},
12610 //----------------------------------------------------------------------
12611 // Data-processing instructions
12612 //----------------------------------------------------------------------
12614 { 0xfbe08000, 0xf1400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #<const>"},
12616 { 0xffffffc0, 0x00004140, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADCReg, "adcs|adc<c> <Rdn>, <Rm>"},
12617 { 0xffe08000, 0xeb400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCReg, "adc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12619 { 0xfffffe00, 0x00001800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDReg, "adds|add<c> <Rd>, <Rn>, <Rm>"},
12620 // Make sure "add sp, <Rm>" comes before this instruction, so there's no ambiguity decoding the two.
12621 { 0xffffff00, 0x00004400, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDReg, "add<c> <Rdn>, <Rm>"},
12623 { 0xfffff800, 0x0000a000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12624 { 0xfbff8000, 0xf2af0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"},
12625 { 0xfbff8000, 0xf20f0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12627 { 0xfbe08000, 0xf0000000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #<const>"},
12629 { 0xffffffc0, 0x00004000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateANDReg, "ands|and<c> <Rdn>, <Rm>"},
12630 { 0xffe08000, 0xea000000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12632 { 0xfbe08000, 0xf0200000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #<const>"},
12634 { 0xffffffc0, 0x00004380, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateBICReg, "bics|bic<c> <Rdn>, <Rm>"},
12635 { 0xffe08000, 0xea200000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICReg, "bic{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12637 { 0xfbe08000, 0xf0800000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #<const>"},
12639 { 0xffffffc0, 0x00004040, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateEORReg, "eors|eor<c> <Rdn>, <Rm>"},
12640 { 0xffe08000, 0xea800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12642 { 0xfbe08000, 0xf0400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #<const>"},
12644 { 0xffffffc0, 0x00004300, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateORRReg, "orrs|orr<c> <Rdn>, <Rm>"},
12645 { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12647 { 0xffffffc0, 0x00004240, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateRSBImm, "rsbs|rsb<c> <Rd>, <Rn>, #0"},
12648 { 0xfbe08000, 0xf1c00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s}<c>.w <Rd>, <Rn>, #<const>"},
12650 { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12652 { 0xfbe08000, 0xf1600000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
12654 { 0xffffffc0, 0x00004180, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSBCReg, "sbcs|sbc<c> <Rdn>, <Rm>"},
12655 { 0xffe08000, 0xeb600000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12656 // add (immediate, Thumb)
12657 { 0xfffffe00, 0x00001c00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDImmThumb, "adds|add<c> <Rd>,<Rn>,#<imm3>" },
12658 { 0xfffff800, 0x00003000, ARMV4T_ABOVE, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDImmThumb, "adds|add<c> <Rdn>,#<imm8>" },
12659 { 0xfbe08000, 0xf1000000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDImmThumb, "add{s}<c>.w <Rd>,<Rn>,#<const>" },
12660 { 0xfbf08000, 0xf2000000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDImmThumb, "addw<c> <Rd>,<Rn>,#<imm12>" },
12661 // sub (immediate, Thumb)
12662 { 0xfffffe00, 0x00001e00, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSUBImmThumb, "subs|sub<c> <Rd>, <Rn> #imm3"},
12663 { 0xfffff800, 0x00003800, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateSUBImmThumb, "subs|sub<c> <Rdn>, #imm8"},
12664 { 0xfbe08000, 0xf1a00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBImmThumb, "sub{s}<c>.w <Rd>, <Rn>, #<const>"},
12665 { 0xfbf08000, 0xf2a00000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBImmThumb, "subw<c> <Rd>, <Rn>, #imm12"},
12666 // sub (sp minus immediate)
12667 { 0xfbef8000, 0xf1ad0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}.w <Rd>, sp, #<const>"},
12668 { 0xfbff8000, 0xf2ad0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw<c> <Rd>, sp, #imm12"},
12670 { 0xfffffe00, 0x00001a00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSUBReg, "subs|sub<c> <Rd>, <Rn>, <Rm>"},
12671 { 0xffe08000, 0xeba00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBReg, "sub{s}<c>.w <Rd>, <Rn>, <Rm>{,<shift>}"},
12673 { 0xfbf08f00, 0xf0900f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq<c> <Rn>, #<const>"},
12675 { 0xfff08f00, 0xea900f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"},
12677 { 0xfbf08f00, 0xf0100f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tst<c> <Rn>, #<const>"},
12679 { 0xffffffc0, 0x00004200, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateTSTReg, "tst<c> <Rdn>, <Rm>"},
12680 { 0xfff08f00, 0xea100f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst<c>.w <Rn>, <Rm> {,<shift>}"},
12683 // move from high register to high register
12684 { 0xffffff00, 0x00004600, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVRdRm, "mov<c> <Rd>, <Rm>"},
12685 // move from low register to low register
12686 { 0xffffffc0, 0x00000000, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVRdRm, "movs <Rd>, <Rm>"},
12687 // mov{s}<c>.w <Rd>, <Rm>
12688 { 0xffeff0f0, 0xea4f0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c>.w <Rd>, <Rm>"},
12690 { 0xfffff800, 0x00002000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVRdImm, "movs|mov<c> <Rd>, #imm8"},
12691 { 0xfbef8000, 0xf04f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}<c>.w <Rd>, #<const>"},
12692 { 0xfbf08000, 0xf2400000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "movw<c> <Rd>,#<imm16>"},
12694 { 0xfbef8000, 0xf06f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMVNImm, "mvn{s} <Rd>, #<const>"},
12696 { 0xffffffc0, 0x000043c0, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMVNReg, "mvns|mvn<c> <Rd>, <Rm>"},
12697 { 0xffef8000, 0xea6f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s}<c>.w <Rd>, <Rm> {,<shift>}"},
12699 { 0xfbf08f00, 0xf1100f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNImm, "cmn<c> <Rn>, #<const>"},
12701 { 0xffffffc0, 0x000042c0, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm>"},
12702 { 0xfff08f00, 0xeb100f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"},
12704 { 0xfffff800, 0x00002800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPImm, "cmp<c> <Rn>, #imm8"},
12705 { 0xfbf08f00, 0xf1b00f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMPImm, "cmp<c>.w <Rn>, #<const>"},
12706 // cmp (register) (Rn and Rm both from r0-r7)
12707 { 0xffffffc0, 0x00004280, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"},
12708 // cmp (register) (Rn and Rm not both from r0-r7)
12709 { 0xffffff00, 0x00004500, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"},
12711 { 0xfffff800, 0x00001000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateASRImm, "asrs|asr<c> <Rd>, <Rm>, #imm"},
12712 { 0xffef8030, 0xea4f0020, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s}<c>.w <Rd>, <Rm>, #imm"},
12714 { 0xffffffc0, 0x00004100, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateASRReg, "asrs|asr<c> <Rdn>, <Rm>"},
12715 { 0xffe0f0f0, 0xfa40f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c>.w <Rd>, <Rn>, <Rm>"},
12717 { 0xfffff800, 0x00000000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSLImm, "lsls|lsl<c> <Rd>, <Rm>, #imm"},
12718 { 0xffef8030, 0xea4f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c>.w <Rd>, <Rm>, #imm"},
12720 { 0xffffffc0, 0x00004080, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSLReg, "lsls|lsl<c> <Rdn>, <Rm>"},
12721 { 0xffe0f0f0, 0xfa00f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c>.w <Rd>, <Rn>, <Rm>"},
12723 { 0xfffff800, 0x00000800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSRImm, "lsrs|lsr<c> <Rd>, <Rm>, #imm"},
12724 { 0xffef8030, 0xea4f0010, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c>.w <Rd>, <Rm>, #imm"},
12726 { 0xffffffc0, 0x000040c0, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSRReg, "lsrs|lsr<c> <Rdn>, <Rm>"},
12727 { 0xffe0f0f0, 0xfa20f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c>.w <Rd>, <Rn>, <Rm>"},
12728 // rrx is a special case encoding of ror (immediate)
12729 { 0xffeff0f0, 0xea4f0030, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRRX, "rrx{s}<c>.w <Rd>, <Rm>"},
12731 { 0xffef8030, 0xea4f0030, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORImm, "ror{s}<c>.w <Rd>, <Rm>, #imm"},
12733 { 0xffffffc0, 0x000041c0, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateRORReg, "rors|ror<c> <Rdn>, <Rm>"},
12734 { 0xffe0f0f0, 0xfa60f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORReg, "ror{s}<c>.w <Rd>, <Rn>, <Rm>"},
12736 { 0xffffffc0, 0x00004340, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMUL, "muls <Rdm>,<Rn>,<Rdm>" },
12738 { 0xfff0f0f0, 0xfb00f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMUL, "mul<c> <Rd>,<Rn>,<Rm>" },
12740 // subs pc, lr and related instructions
12741 { 0xffffff00, 0xf3de8f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPcLrEtc, "SUBS<c> PC, LR, #<imm8>" },
12743 //----------------------------------------------------------------------
12744 // RFE instructions *** IMPORTANT *** THESE MUST BE LISTED **BEFORE** THE LDM.. Instructions in this table;
12745 // otherwise the wrong instructions will be selected.
12746 //----------------------------------------------------------------------
12748 { 0xffd0ffff, 0xe810c000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRFE, "rfedb<c> <Rn>{!}" },
12749 { 0xffd0ffff, 0xe990c000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateRFE, "rfe{ia}<c> <Rn>{!}" },
12751 //----------------------------------------------------------------------
12752 // Load instructions
12753 //----------------------------------------------------------------------
12754 { 0xfffff800, 0x0000c800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" },
12755 { 0xffd02000, 0xe8900000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c>.w <Rn>{!} <registers>" },
12756 { 0xffd00000, 0xe9100000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" },
12757 { 0xfffff800, 0x00006800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#imm}]"},
12758 { 0xfffff800, 0x00009800, ARMV4T_ABOVE, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [SP{,#imm}]"},
12759 { 0xfff00000, 0xf8d00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c>.w <Rt>, [<Rn>{,#imm12}]"},
12760 { 0xfff00800, 0xf8500800, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#+/-<imm8>}]{!}"},
12761 // Thumb2 PC-relative load into register
12762 { 0xff7f0000, 0xf85f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr<c>.w <Rt>, [PC, +/-#imm}]"},
12763 { 0xfffffe00, 0x00005800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt>, [<Rn>, <Rm>]" },
12764 { 0xfff00fc0, 0xf8500000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c>.w <Rt>, [<Rn>,<Rm>{,LSL #<imm2>}]" },
12765 { 0xfffff800, 0x00007800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c> <Rt>,[<Rn>{,#<imm5>}]" },
12766 { 0xfff00000, 0xf8900000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c>.w <Rt>,[<Rn>{,#<imm12>}]" },
12767 { 0xfff00800, 0xf8100800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c> <Rt>,[<Rn>, #+/-<imm8>]{!}" },
12768 { 0xff7f0000, 0xf81f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>,[...]" },
12769 { 0xfffffe00, 0x00005c00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>,[<Rn>,<Rm>]" },
12770 { 0xfff00fc0, 0xf8100000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]" },
12771 { 0xfffff800, 0x00008800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>, [<Rn>{,#<imm>}]" },
12772 { 0xfff00000, 0xf8b00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]" },
12773 { 0xfff00800, 0xf8300800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]{!}" },
12774 { 0xff7f0000, 0xf83f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" },
12775 { 0xfffffe00, 0x00005a00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>, [<Rn>,<Rm>]" },
12776 { 0xfff00fc0, 0xf8300000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12777 { 0xfff00000, 0xf9900000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>,[<Rn>,#<imm12>]" },
12778 { 0xfff00800, 0xf9100800, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>,[<Rn>,#+/-<imm8>]" },
12779 { 0xff7f0000, 0xf91f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBLiteral, "ldrsb<c> <Rt>, <label>" },
12780 { 0xfffffe00, 0x00005600, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c> <Rt>,[<Rn>,<Rm>]" },
12781 { 0xfff00fc0, 0xf9100000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]" },
12782 { 0xfff00000, 0xf9b00000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>,#<imm12>]" },
12783 { 0xfff00800, 0xf9300800, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>,#+/-<imm8>]" },
12784 { 0xff7f0000, 0xf93f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHLiteral, "ldrsh<c> <Rt>,<label>" },
12785 { 0xfffffe00, 0x00005e00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,<Rm>]" },
12786 { 0xfff00fc0, 0xf9300000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12787 { 0xfe500000, 0xe8500000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm>]!"},
12788 { 0xfe100f00, 0xec100b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
12789 { 0xfe100f00, 0xec100a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>" },
12790 { 0xffe00f00, 0xed100b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
12791 { 0xff300f00, 0xed100a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Sd>, {<Rn>{,#+/-<imm>}]"},
12792 { 0xffb00000, 0xf9200000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Multiple, "vld1<c>.<size> <list>, [<Rn>{@<align>}],<Rm>"},
12793 { 0xffb00300, 0xf9a00000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Single, "vld1<c>.<size> <list>, [<Rn>{@<align>}],<Rm>"},
12794 { 0xffb00f00, 0xf9a00c00, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1SingleAll, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12796 //----------------------------------------------------------------------
12797 // Store instructions
12798 //----------------------------------------------------------------------
12799 { 0xfffff800, 0x0000c000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" },
12800 { 0xffd00000, 0xe8800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c>.w <Rn>{!} <registers>" },
12801 { 0xffd00000, 0xe9000000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTMDB, "stmdb<c> <Rn>{!} <registers>" },
12802 { 0xfffff800, 0x00006000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [<Rn>{,#<imm>}]" },
12803 { 0xfffff800, 0x00009000, ARMV4T_ABOVE, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [SP,#<imm>]" },
12804 { 0xfff00000, 0xf8c00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRThumb, "str<c>.w <Rt>, [<Rn>,#<imm12>]" },
12805 { 0xfff00800, 0xf8400800, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [<Rn>,#+/-<imm8>]" },
12806 { 0xfffffe00, 0x00005000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRRegister, "str<c> <Rt> ,{<Rn>, <Rm>]" },
12807 { 0xfff00fc0, 0xf8400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRRegister, "str<c>.w <Rt>, [<Rn>, <Rm> {lsl #imm2>}]" },
12808 { 0xfffff800, 0x00007000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c> <Rt>, [<Rn>, #<imm5>]" },
12809 { 0xfff00000, 0xf8800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c>.w <Rt>, [<Rn>, #<imm12>]" },
12810 { 0xfff00800, 0xf8000800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c> <Rt> ,[<Rn>, #+/-<imm8>]{!}" },
12811 { 0xfffffe00, 0x00005200, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,<Rm>]" },
12812 { 0xfff00fc0, 0xf8200000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12813 { 0xfff00000, 0xe8400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn{,#<imm>}]" },
12814 { 0xfe500000, 0xe8400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDImm, "strd<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!"},
12815 { 0xfe100f00, 0xec000b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!}, <list>"},
12816 { 0xfea00f00, 0xec000a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!}, <list>"},
12817 { 0xff300f00, 0xed000b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
12818 { 0xff300f00, 0xed000a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Sd>, [<Rn>{,#+/-<imm>}]"},
12819 { 0xffb00000, 0xf9000000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Multiple, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12820 { 0xffb00300, 0xf9800000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Single, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12822 //----------------------------------------------------------------------
12823 // Other instructions
12824 //----------------------------------------------------------------------
12825 { 0xffffffc0, 0x0000b240, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>" },
12826 { 0xfffff080, 0xfa4ff080, ARMV6_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c>.w <Rd>,<Rm>{,<rotation>}" },
12827 { 0xffffffc0, 0x0000b200, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>" },
12828 { 0xfffff080, 0xfa0ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTH, "sxth<c>.w <Rd>,<Rm>{,<rotation>}" },
12829 { 0xffffffc0, 0x0000b2c0, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>" },
12830 { 0xfffff080, 0xfa5ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTB, "uxtb<c>.w <Rd>,<Rm>{,<rotation>}" },
12831 { 0xffffffc0, 0x0000b280, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>" },
12832 { 0xfffff080, 0xfa1ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTH, "uxth<c>.w <Rd>,<Rm>{,<rotation>}" },
12835 const size_t k_num_thumb_opcodes = sizeof(g_thumb_opcodes)/sizeof(ARMOpcode);
12836 for (size_t i=0; i<k_num_thumb_opcodes; ++i)
12838 if ((g_thumb_opcodes[i].mask & opcode) == g_thumb_opcodes[i].value &&
12839 (g_thumb_opcodes[i].variants & arm_isa) != 0)
12840 return &g_thumb_opcodes[i];
12846 EmulateInstructionARM::SetArchitecture (const ArchSpec &arch)
12850 const char *arch_cstr = arch.GetArchitectureName ();
12853 if (0 == ::strcasecmp(arch_cstr, "armv4t")) m_arm_isa = ARMv4T;
12854 else if (0 == ::strcasecmp(arch_cstr, "armv5tej")) m_arm_isa = ARMv5TEJ;
12855 else if (0 == ::strcasecmp(arch_cstr, "armv5te")) m_arm_isa = ARMv5TE;
12856 else if (0 == ::strcasecmp(arch_cstr, "armv5t")) m_arm_isa = ARMv5T;
12857 else if (0 == ::strcasecmp(arch_cstr, "armv6k")) m_arm_isa = ARMv6K;
12858 else if (0 == ::strcasecmp(arch_cstr, "armv6t2")) m_arm_isa = ARMv6T2;
12859 else if (0 == ::strcasecmp(arch_cstr, "armv7s")) m_arm_isa = ARMv7S;
12860 else if (0 == ::strcasecmp(arch_cstr, "arm")) m_arm_isa = ARMvAll;
12861 else if (0 == ::strcasecmp(arch_cstr, "thumb")) m_arm_isa = ARMvAll;
12862 else if (0 == ::strncasecmp(arch_cstr,"armv4", 5)) m_arm_isa = ARMv4;
12863 else if (0 == ::strncasecmp(arch_cstr,"armv6", 5)) m_arm_isa = ARMv6;
12864 else if (0 == ::strncasecmp(arch_cstr,"armv7", 5)) m_arm_isa = ARMv7;
12865 else if (0 == ::strncasecmp(arch_cstr,"armv8", 5)) m_arm_isa = ARMv8;
12867 return m_arm_isa != 0;
12871 EmulateInstructionARM::SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target)
12873 if (EmulateInstruction::SetInstruction (insn_opcode, inst_addr, target))
12875 if (m_arch.GetTriple().getArch() == llvm::Triple::thumb)
12876 m_opcode_mode = eModeThumb;
12879 AddressClass addr_class = inst_addr.GetAddressClass();
12881 if ((addr_class == eAddressClassCode) || (addr_class == eAddressClassUnknown))
12882 m_opcode_mode = eModeARM;
12883 else if (addr_class == eAddressClassCodeAlternateISA)
12884 m_opcode_mode = eModeThumb;
12888 if (m_opcode_mode == eModeThumb)
12889 m_opcode_cpsr = CPSR_MODE_USR | MASK_CPSR_T;
12891 m_opcode_cpsr = CPSR_MODE_USR;
12898 EmulateInstructionARM::ReadInstruction ()
12900 bool success = false;
12901 m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, 0, &success);
12904 addr_t pc = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS, &success);
12907 Context read_inst_context;
12908 read_inst_context.type = eContextReadOpcode;
12909 read_inst_context.SetNoArgs ();
12911 if (m_opcode_cpsr & MASK_CPSR_T)
12913 m_opcode_mode = eModeThumb;
12914 uint32_t thumb_opcode = MemARead(read_inst_context, pc, 2, 0, &success);
12918 if ((thumb_opcode & 0xe000) != 0xe000 || ((thumb_opcode & 0x1800u) == 0))
12920 m_opcode.SetOpcode16 (thumb_opcode, GetByteOrder());
12924 m_opcode.SetOpcode32 ((thumb_opcode << 16) | MemARead(read_inst_context, pc + 2, 2, 0, &success), GetByteOrder());
12930 m_opcode_mode = eModeARM;
12931 m_opcode.SetOpcode32 (MemARead(read_inst_context, pc, 4, 0, &success), GetByteOrder());
12937 m_opcode_mode = eModeInvalid;
12938 m_addr = LLDB_INVALID_ADDRESS;
12944 EmulateInstructionARM::ArchVersion ()
12950 EmulateInstructionARM::ConditionPassed (const uint32_t opcode, bool *is_conditional)
12952 // If we are ignoring conditions, then always return true.
12953 // this allows us to iterate over disassembly code and still
12954 // emulate an instruction even if we don't have all the right
12955 // bits set in the CPSR register...
12956 if (m_ignore_conditions)
12959 if (is_conditional)
12960 *is_conditional = true;
12962 const uint32_t cond = CurrentCond (opcode);
12964 if (cond == UINT32_MAX)
12967 bool result = false;
12968 switch (UnsignedBits(cond, 3, 1))
12971 if (m_opcode_cpsr == 0)
12974 result = (m_opcode_cpsr & MASK_CPSR_Z) != 0;
12977 if (m_opcode_cpsr == 0)
12980 result = (m_opcode_cpsr & MASK_CPSR_C) != 0;
12983 if (m_opcode_cpsr == 0)
12986 result = (m_opcode_cpsr & MASK_CPSR_N) != 0;
12989 if (m_opcode_cpsr == 0)
12992 result = (m_opcode_cpsr & MASK_CPSR_V) != 0;
12995 if (m_opcode_cpsr == 0)
12998 result = ((m_opcode_cpsr & MASK_CPSR_C) != 0) && ((m_opcode_cpsr & MASK_CPSR_Z) == 0);
13001 if (m_opcode_cpsr == 0)
13005 bool n = (m_opcode_cpsr & MASK_CPSR_N);
13006 bool v = (m_opcode_cpsr & MASK_CPSR_V);
13011 if (m_opcode_cpsr == 0)
13015 bool n = (m_opcode_cpsr & MASK_CPSR_N);
13016 bool v = (m_opcode_cpsr & MASK_CPSR_V);
13017 result = n == v && ((m_opcode_cpsr & MASK_CPSR_Z) == 0);
13021 // Always execute (cond == 0b1110, or the special 0b1111 which gives
13022 // opcodes different meanings, but always means execution happpens.
13023 if (is_conditional)
13024 *is_conditional = false;
13035 EmulateInstructionARM::CurrentCond (const uint32_t opcode)
13037 switch (m_opcode_mode)
13043 return UnsignedBits(opcode, 31, 28);
13046 // For T1 and T3 encodings of the Branch instruction, it returns the 4-bit
13047 // 'cond' field of the encoding.
13049 const uint32_t byte_size = m_opcode.GetByteSize();
13050 if (byte_size == 2)
13052 if (Bits32(opcode, 15, 12) == 0x0d && Bits32(opcode, 11, 7) != 0x0f)
13053 return Bits32(opcode, 11, 7);
13055 else if (byte_size == 4)
13057 if (Bits32(opcode, 31, 27) == 0x1e &&
13058 Bits32(opcode, 15, 14) == 0x02 &&
13059 Bits32(opcode, 12, 12) == 0x00 &&
13060 Bits32(opcode, 25, 22) <= 0x0d)
13062 return Bits32(opcode, 25, 22);
13066 // We have an invalid thumb instruction, let's bail out.
13069 return m_it_session.GetCond();
13072 return UINT32_MAX; // Return invalid value
13076 EmulateInstructionARM::InITBlock()
13078 return CurrentInstrSet() == eModeThumb && m_it_session.InITBlock();
13082 EmulateInstructionARM::LastInITBlock()
13084 return CurrentInstrSet() == eModeThumb && m_it_session.LastInITBlock();
13088 EmulateInstructionARM::BadMode (uint32_t mode)
13093 case 16: return false; // '10000'
13094 case 17: return false; // '10001'
13095 case 18: return false; // '10010'
13096 case 19: return false; // '10011'
13097 case 22: return false; // '10110'
13098 case 23: return false; // '10111'
13099 case 27: return false; // '11011'
13100 case 31: return false; // '11111'
13101 default: return true;
13107 EmulateInstructionARM::CurrentModeIsPrivileged ()
13109 uint32_t mode = Bits32 (m_opcode_cpsr, 4, 0);
13111 if (BadMode (mode))
13121 EmulateInstructionARM::CPSRWriteByInstr (uint32_t value, uint32_t bytemask, bool affect_execstate)
13123 bool privileged = CurrentModeIsPrivileged();
13125 uint32_t tmp_cpsr = Bits32 (m_opcode_cpsr, 23, 20) << 20;
13127 if (BitIsSet (bytemask, 3))
13129 tmp_cpsr = tmp_cpsr | (Bits32 (value, 31, 27) << 27);
13130 if (affect_execstate)
13131 tmp_cpsr = tmp_cpsr | (Bits32 (value, 26, 24) << 24);
13134 if (BitIsSet (bytemask, 2))
13136 tmp_cpsr = tmp_cpsr | (Bits32 (value, 19, 16) << 16);
13139 if (BitIsSet (bytemask, 1))
13141 if (affect_execstate)
13142 tmp_cpsr = tmp_cpsr | (Bits32 (value, 15, 10) << 10);
13143 tmp_cpsr = tmp_cpsr | (Bit32 (value, 9) << 9);
13145 tmp_cpsr = tmp_cpsr | (Bit32 (value, 8) << 8);
13148 if (BitIsSet (bytemask, 0))
13151 tmp_cpsr = tmp_cpsr | (Bits32 (value, 7, 6) << 6);
13152 if (affect_execstate)
13153 tmp_cpsr = tmp_cpsr | (Bit32 (value, 5) << 5);
13155 tmp_cpsr = tmp_cpsr | Bits32 (value, 4, 0);
13158 m_opcode_cpsr = tmp_cpsr;
13163 EmulateInstructionARM::BranchWritePC (const Context &context, uint32_t addr)
13167 // Check the current instruction set.
13168 if (CurrentInstrSet() == eModeARM)
13169 target = addr & 0xfffffffc;
13171 target = addr & 0xfffffffe;
13173 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target))
13179 // As a side effect, BXWritePC sets context.arg2 to eModeARM or eModeThumb by inspecting addr.
13181 EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr)
13184 // If the CPSR is changed due to switching between ARM and Thumb ISETSTATE,
13185 // we want to record it and issue a WriteRegister callback so the clients
13186 // can track the mode changes accordingly.
13187 bool cpsr_changed = false;
13189 if (BitIsSet(addr, 0))
13191 if (CurrentInstrSet() != eModeThumb)
13193 SelectInstrSet(eModeThumb);
13194 cpsr_changed = true;
13196 target = addr & 0xfffffffe;
13197 context.SetISA (eModeThumb);
13199 else if (BitIsClear(addr, 1))
13201 if (CurrentInstrSet() != eModeARM)
13203 SelectInstrSet(eModeARM);
13204 cpsr_changed = true;
13206 target = addr & 0xfffffffc;
13207 context.SetISA (eModeARM);
13210 return false; // address<1:0> == '10' => UNPREDICTABLE
13214 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr))
13217 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target))
13223 // Dispatches to either BXWritePC or BranchWritePC based on architecture versions.
13225 EmulateInstructionARM::LoadWritePC (Context &context, uint32_t addr)
13227 if (ArchVersion() >= ARMv5T)
13228 return BXWritePC(context, addr);
13230 return BranchWritePC((const Context)context, addr);
13233 // Dispatches to either BXWritePC or BranchWritePC based on architecture versions and current instruction set.
13235 EmulateInstructionARM::ALUWritePC (Context &context, uint32_t addr)
13237 if (ArchVersion() >= ARMv7 && CurrentInstrSet() == eModeARM)
13238 return BXWritePC(context, addr);
13240 return BranchWritePC((const Context)context, addr);
13243 EmulateInstructionARM::Mode
13244 EmulateInstructionARM::CurrentInstrSet ()
13246 return m_opcode_mode;
13249 // Set the 'T' bit of our CPSR. The m_opcode_mode gets updated when the next
13250 // ReadInstruction() is performed. This function has a side effect of updating
13251 // the m_new_inst_cpsr member variable if necessary.
13253 EmulateInstructionARM::SelectInstrSet (Mode arm_or_thumb)
13255 m_new_inst_cpsr = m_opcode_cpsr;
13256 switch (arm_or_thumb)
13261 // Clear the T bit.
13262 m_new_inst_cpsr &= ~MASK_CPSR_T;
13266 m_new_inst_cpsr |= MASK_CPSR_T;
13272 // This function returns TRUE if the processor currently provides support for
13273 // unaligned memory accesses, or FALSE otherwise. This is always TRUE in ARMv7,
13274 // controllable by the SCTLR.U bit in ARMv6, and always FALSE before ARMv6.
13276 EmulateInstructionARM::UnalignedSupport()
13278 return (ArchVersion() >= ARMv7);
13281 // The main addition and subtraction instructions can produce status information
13282 // about both unsigned carry and signed overflow conditions. This status
13283 // information can be used to synthesize multi-word additions and subtractions.
13284 EmulateInstructionARM::AddWithCarryResult
13285 EmulateInstructionARM::AddWithCarry (uint32_t x, uint32_t y, uint8_t carry_in)
13291 uint64_t unsigned_sum = x + y + carry_in;
13292 int64_t signed_sum = (int32_t)x + (int32_t)y + (int32_t)carry_in;
13294 result = UnsignedBits(unsigned_sum, 31, 0);
13295 // carry_out = (result == unsigned_sum ? 0 : 1);
13296 overflow = ((int32_t)result == signed_sum ? 0 : 1);
13299 carry_out = ((int32_t) x >= (int32_t) (~y)) ? 1 : 0;
13301 carry_out = ((int32_t) x > (int32_t) y) ? 1 : 0;
13303 AddWithCarryResult res = { result, carry_out, overflow };
13308 EmulateInstructionARM::ReadCoreReg(uint32_t num, bool *success)
13310 uint32_t reg_kind, reg_num;
13314 reg_kind = eRegisterKindGeneric;
13315 reg_num = LLDB_REGNUM_GENERIC_SP;
13318 reg_kind = eRegisterKindGeneric;
13319 reg_num = LLDB_REGNUM_GENERIC_RA;
13322 reg_kind = eRegisterKindGeneric;
13323 reg_num = LLDB_REGNUM_GENERIC_PC;
13328 reg_kind = eRegisterKindDWARF;
13329 reg_num = dwarf_r0 + num;
13333 //assert(0 && "Invalid register number");
13340 // Read our register.
13341 uint32_t val = ReadRegisterUnsigned (reg_kind, reg_num, 0, success);
13343 // When executing an ARM instruction , PC reads as the address of the current
13344 // instruction plus 8.
13345 // When executing a Thumb instruction , PC reads as the address of the current
13346 // instruction plus 4.
13349 if (CurrentInstrSet() == eModeARM)
13358 // Write the result to the ARM core register Rd, and optionally update the
13359 // condition flags based on the result.
13361 // This helper method tries to encapsulate the following pseudocode from the
13362 // ARM Architecture Reference Manual:
13364 // if d == 15 then // Can only occur for encoding A1
13365 // ALUWritePC(result); // setflags is always FALSE here
13368 // if setflags then
13369 // APSR.N = result<31>;
13370 // APSR.Z = IsZeroBit(result);
13372 // // APSR.V unchanged
13374 // In the above case, the API client does not pass in the overflow arg, which
13375 // defaults to ~0u.
13377 EmulateInstructionARM::WriteCoreRegOptionalFlags (Context &context,
13378 const uint32_t result,
13381 const uint32_t carry,
13382 const uint32_t overflow)
13386 if (!ALUWritePC (context, result))
13391 uint32_t reg_kind, reg_num;
13395 reg_kind = eRegisterKindGeneric;
13396 reg_num = LLDB_REGNUM_GENERIC_SP;
13399 reg_kind = eRegisterKindGeneric;
13400 reg_num = LLDB_REGNUM_GENERIC_RA;
13403 reg_kind = eRegisterKindDWARF;
13404 reg_num = dwarf_r0 + Rd;
13406 if (!WriteRegisterUnsigned (context, reg_kind, reg_num, result))
13409 return WriteFlags (context, result, carry, overflow);
13414 // This helper method tries to encapsulate the following pseudocode from the
13415 // ARM Architecture Reference Manual:
13417 // APSR.N = result<31>;
13418 // APSR.Z = IsZeroBit(result);
13420 // APSR.V = overflow
13422 // Default arguments can be specified for carry and overflow parameters, which means
13423 // not to update the respective flags.
13425 EmulateInstructionARM::WriteFlags (Context &context,
13426 const uint32_t result,
13427 const uint32_t carry,
13428 const uint32_t overflow)
13430 m_new_inst_cpsr = m_opcode_cpsr;
13431 SetBit32(m_new_inst_cpsr, CPSR_N_POS, Bit32(result, CPSR_N_POS));
13432 SetBit32(m_new_inst_cpsr, CPSR_Z_POS, result == 0 ? 1 : 0);
13434 SetBit32(m_new_inst_cpsr, CPSR_C_POS, carry);
13435 if (overflow != ~0u)
13436 SetBit32(m_new_inst_cpsr, CPSR_V_POS, overflow);
13437 if (m_new_inst_cpsr != m_opcode_cpsr)
13439 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr))
13446 EmulateInstructionARM::EvaluateInstruction (uint32_t evaluate_options)
13448 // Advance the ITSTATE bits to their values for the next instruction.
13449 if (m_opcode_mode == eModeThumb && m_it_session.InITBlock())
13450 m_it_session.ITAdvance();
13452 ARMOpcode *opcode_data = NULL;
13454 if (m_opcode_mode == eModeThumb)
13455 opcode_data = GetThumbOpcodeForInstruction (m_opcode.GetOpcode32(), m_arm_isa);
13456 else if (m_opcode_mode == eModeARM)
13457 opcode_data = GetARMOpcodeForInstruction (m_opcode.GetOpcode32(), m_arm_isa);
13459 if (opcode_data == NULL)
13462 const bool auto_advance_pc = evaluate_options & eEmulateInstructionOptionAutoAdvancePC;
13463 m_ignore_conditions = evaluate_options & eEmulateInstructionOptionIgnoreConditions;
13465 bool success = false;
13466 if (m_opcode_cpsr == 0 || m_ignore_conditions == false)
13468 m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindDWARF,
13474 // Only return false if we are unable to read the CPSR if we care about conditions
13475 if (success == false && m_ignore_conditions == false)
13478 uint32_t orig_pc_value = 0;
13479 if (auto_advance_pc)
13481 orig_pc_value = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc, 0, &success);
13486 // Call the Emulate... function.
13487 success = (this->*opcode_data->callback) (m_opcode.GetOpcode32(), opcode_data->encoding);
13491 if (auto_advance_pc)
13493 uint32_t after_pc_value = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc, 0, &success);
13497 if (auto_advance_pc && (after_pc_value == orig_pc_value))
13499 if (opcode_data->size == eSize32)
13500 after_pc_value += 4;
13501 else if (opcode_data->size == eSize16)
13502 after_pc_value += 2;
13504 EmulateInstruction::Context context;
13505 context.type = eContextAdvancePC;
13506 context.SetNoArgs();
13507 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc, after_pc_value))
13516 EmulateInstructionARM::TestEmulation (Stream *out_stream, ArchSpec &arch, OptionValueDictionary *test_data)
13520 out_stream->Printf ("TestEmulation: Missing test data.\n");
13524 static ConstString opcode_key ("opcode");
13525 static ConstString before_key ("before_state");
13526 static ConstString after_key ("after_state");
13528 OptionValueSP value_sp = test_data->GetValueForKey (opcode_key);
13530 uint32_t test_opcode;
13531 if ((value_sp.get() == NULL) || (value_sp->GetType() != OptionValue::eTypeUInt64))
13533 out_stream->Printf ("TestEmulation: Error reading opcode from test file.\n");
13536 test_opcode = value_sp->GetUInt64Value ();
13538 if (arch.GetTriple().getArch() == llvm::Triple::arm)
13540 m_opcode_mode = eModeARM;
13541 m_opcode.SetOpcode32 (test_opcode, GetByteOrder());
13543 else if (arch.GetTriple().getArch() == llvm::Triple::thumb)
13545 m_opcode_mode = eModeThumb;
13546 if (test_opcode < 0x10000)
13547 m_opcode.SetOpcode16 (test_opcode, GetByteOrder());
13549 m_opcode.SetOpcode32 (test_opcode, GetByteOrder());
13554 out_stream->Printf ("TestEmulation: Invalid arch.\n");
13558 EmulationStateARM before_state;
13559 EmulationStateARM after_state;
13561 value_sp = test_data->GetValueForKey (before_key);
13562 if ((value_sp.get() == NULL) || (value_sp->GetType() != OptionValue::eTypeDictionary))
13564 out_stream->Printf ("TestEmulation: Failed to find 'before' state.\n");
13568 OptionValueDictionary *state_dictionary = value_sp->GetAsDictionary ();
13569 if (!before_state.LoadStateFromDictionary (state_dictionary))
13571 out_stream->Printf ("TestEmulation: Failed loading 'before' state.\n");
13575 value_sp = test_data->GetValueForKey (after_key);
13576 if ((value_sp.get() == NULL) || (value_sp->GetType() != OptionValue::eTypeDictionary))
13578 out_stream->Printf ("TestEmulation: Failed to find 'after' state.\n");
13582 state_dictionary = value_sp->GetAsDictionary ();
13583 if (!after_state.LoadStateFromDictionary (state_dictionary))
13585 out_stream->Printf ("TestEmulation: Failed loading 'after' state.\n");
13589 SetBaton ((void *) &before_state);
13590 SetCallbacks (&EmulationStateARM::ReadPseudoMemory,
13591 &EmulationStateARM::WritePseudoMemory,
13592 &EmulationStateARM::ReadPseudoRegister,
13593 &EmulationStateARM::WritePseudoRegister);
13595 bool success = EvaluateInstruction (eEmulateInstructionOptionAutoAdvancePC);
13598 out_stream->Printf ("TestEmulation: EvaluateInstruction() failed.\n");
13602 success = before_state.CompareState (after_state);
13604 out_stream->Printf ("TestEmulation: 'before' and 'after' states do not match.\n");
13611 //EmulateInstructionARM::GetRegisterName (uint32_t reg_kind, uint32_t reg_num)
13613 // if (reg_kind == eRegisterKindGeneric)
13615 // switch (reg_num)
13617 // case LLDB_REGNUM_GENERIC_PC: return "pc";
13618 // case LLDB_REGNUM_GENERIC_SP: return "sp";
13619 // case LLDB_REGNUM_GENERIC_FP: return "fp";
13620 // case LLDB_REGNUM_GENERIC_RA: return "lr";
13621 // case LLDB_REGNUM_GENERIC_FLAGS: return "cpsr";
13622 // default: return NULL;
13625 // else if (reg_kind == eRegisterKindDWARF)
13627 // return GetARMDWARFRegisterName (reg_num);
13633 EmulateInstructionARM::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan)
13635 unwind_plan.Clear();
13636 unwind_plan.SetRegisterKind (eRegisterKindDWARF);
13638 UnwindPlan::RowSP row(new UnwindPlan::Row);
13640 // Our previous Call Frame Address is the stack pointer
13641 row->SetCFARegister (dwarf_sp);
13643 // Our previous PC is in the LR
13644 row->SetRegisterLocationToRegister(dwarf_pc, dwarf_lr, true);
13645 unwind_plan.AppendRow (row);
13647 // All other registers are the same.
13649 unwind_plan.SetSourceName ("EmulateInstructionARM");
13650 unwind_plan.SetSourcedFromCompiler (eLazyBoolNo);
13651 unwind_plan.SetUnwindPlanValidAtAllInstructions (eLazyBoolYes);