lib/libpmc/libpmc.c

   1 /*-
   2  * Copyright (c) 2003-2008 Joseph Koshy
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/types.h>
  31 #include <sys/param.h>
  32 #include <sys/module.h>
  33 #include <sys/pmc.h>
  34 #include <sys/syscall.h>
  35
  36 #include <ctype.h>
  37 #include <errno.h>
  38 #include <fcntl.h>
  39 #include <pmc.h>
  40 #include <stdio.h>
  41 #include <stdlib.h>
  42 #include <string.h>
  43 #include <strings.h>
  44 #include <unistd.h>
  45
  46 #include "libpmcinternal.h"
  47
  48 /* Function prototypes */
  49 #if defined(__i386__)
  50 static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  51     struct pmc_op_pmcallocate *_pmc_config);
  52 #endif
  53 #if defined(__amd64__) || defined(__i386__)
  54 static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  55     struct pmc_op_pmcallocate *_pmc_config);
  56 static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  57     struct pmc_op_pmcallocate *_pmc_config);
  58 static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  59     struct pmc_op_pmcallocate *_pmc_config);
  60 static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  61     struct pmc_op_pmcallocate *_pmc_config);
  62 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  63     struct pmc_op_pmcallocate *_pmc_config);
  64 static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  65     struct pmc_op_pmcallocate *_pmc_config);
  66 #endif
  67 #if defined(__i386__)
  68 static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  69     struct pmc_op_pmcallocate *_pmc_config);
  70 static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  71     struct pmc_op_pmcallocate *_pmc_config);
  72 #endif
  73 #if defined(__amd64__) || defined(__i386__)
  74 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  75     struct pmc_op_pmcallocate *_pmc_config);
  76 #endif
  77 #if defined(__XSCALE__)
  78 static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  79     struct pmc_op_pmcallocate *_pmc_config);
  80 #endif
  81 #if defined(__mips__)
  82 static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec,
  83                              struct pmc_op_pmcallocate *_pmc_config);
  84 #endif /* __mips__ */
  85 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  86     struct pmc_op_pmcallocate *_pmc_config);
  87
  88 #if defined(__powerpc__)
  89 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec,
  90                              struct pmc_op_pmcallocate *_pmc_config);
  91 #endif /* __powerpc__ */
  92
  93 #define PMC_CALL(cmd, params)                           \
  94         syscall(pmc_syscall, PMC_OP_##cmd, (params))
  95
  96 /*
  97  * Event aliases provide a way for the user to ask for generic events
  98  * like "cache-misses", or "instructions-retired".  These aliases are
  99  * mapped to the appropriate canonical event descriptions using a
 100  * lookup table.
 101  */
 102 struct pmc_event_alias {
 103         const char      *pm_alias;
 104         const char      *pm_spec;
 105 };
 106
 107 static const struct pmc_event_alias *pmc_mdep_event_aliases;
 108
 109 /*
 110  * The pmc_event_descr structure maps symbolic names known to the user
 111  * to integer codes used by the PMC KLD.
 112  */
 113 struct pmc_event_descr {
 114         const char      *pm_ev_name;
 115         enum pmc_event  pm_ev_code;
 116 };
 117
 118 /*
 119  * The pmc_class_descr structure maps class name prefixes for
 120  * event names to event tables and other PMC class data.
 121  */
 122 struct pmc_class_descr {
 123         const char      *pm_evc_name;
 124         size_t          pm_evc_name_size;
 125         enum pmc_class  pm_evc_class;
 126         const struct pmc_event_descr *pm_evc_event_table;
 127         size_t          pm_evc_event_table_size;
 128         int             (*pm_evc_allocate_pmc)(enum pmc_event _pe,
 129                             char *_ctrspec, struct pmc_op_pmcallocate *_pa);
 130 };
 131
 132 #define PMC_TABLE_SIZE(N)       (sizeof(N)/sizeof(N[0]))
 133 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table)
 134
 135 #undef  __PMC_EV
 136 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N },
 137
 138 /*
 139  * PMC_CLASSDEP_TABLE(NAME, CLASS)
 140  *
 141  * Define a table mapping event names and aliases to HWPMC event IDs.
 142  */
 143 #define PMC_CLASSDEP_TABLE(N, C)                                \
 144         static const struct pmc_event_descr N##_event_table[] = \
 145         {                                                       \
 146                 __PMC_EV_##C()                                  \
 147         }
 148
 149 PMC_CLASSDEP_TABLE(iaf, IAF);
 150 PMC_CLASSDEP_TABLE(k7, K7);
 151 PMC_CLASSDEP_TABLE(k8, K8);
 152 PMC_CLASSDEP_TABLE(p4, P4);
 153 PMC_CLASSDEP_TABLE(p5, P5);
 154 PMC_CLASSDEP_TABLE(p6, P6);
 155 PMC_CLASSDEP_TABLE(xscale, XSCALE);
 156 PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
 157 PMC_CLASSDEP_TABLE(octeon, OCTEON);
 158 PMC_CLASSDEP_TABLE(ucf, UCF);
 159 PMC_CLASSDEP_TABLE(ppc7450, PPC7450);
 160 PMC_CLASSDEP_TABLE(ppc970, PPC970);
 161
 162 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT];
 163
 164 #undef  __PMC_EV_ALIAS
 165 #define __PMC_EV_ALIAS(N,CODE)  { N, PMC_EV_##CODE },
 166
 167 static const struct pmc_event_descr atom_event_table[] =
 168 {
 169         __PMC_EV_ALIAS_ATOM()
 170 };
 171
 172 static const struct pmc_event_descr atom_silvermont_event_table[] =
 173 {
 174         __PMC_EV_ALIAS_ATOM_SILVERMONT()
 175 };
 176
 177 static const struct pmc_event_descr core_event_table[] =
 178 {
 179         __PMC_EV_ALIAS_CORE()
 180 };
 181
 182
 183 static const struct pmc_event_descr core2_event_table[] =
 184 {
 185         __PMC_EV_ALIAS_CORE2()
 186 };
 187
 188 static const struct pmc_event_descr corei7_event_table[] =
 189 {
 190         __PMC_EV_ALIAS_COREI7()
 191 };
 192
 193 static const struct pmc_event_descr nehalem_ex_event_table[] =
 194 {
 195         __PMC_EV_ALIAS_COREI7()
 196 };
 197
 198 static const struct pmc_event_descr haswell_event_table[] =
 199 {
 200         __PMC_EV_ALIAS_HASWELL()
 201 };
 202
 203 static const struct pmc_event_descr haswell_xeon_event_table[] =
 204 {
 205         __PMC_EV_ALIAS_HASWELL_XEON()
 206 };
 207
 208
 209 static const struct pmc_event_descr ivybridge_event_table[] =
 210 {
 211         __PMC_EV_ALIAS_IVYBRIDGE()
 212 };
 213
 214 static const struct pmc_event_descr ivybridge_xeon_event_table[] =
 215 {
 216         __PMC_EV_ALIAS_IVYBRIDGE_XEON()
 217 };
 218
 219 static const struct pmc_event_descr sandybridge_event_table[] =
 220 {
 221         __PMC_EV_ALIAS_SANDYBRIDGE()
 222 };
 223
 224 static const struct pmc_event_descr sandybridge_xeon_event_table[] =
 225 {
 226         __PMC_EV_ALIAS_SANDYBRIDGE_XEON()
 227 };
 228
 229 static const struct pmc_event_descr westmere_event_table[] =
 230 {
 231         __PMC_EV_ALIAS_WESTMERE()
 232 };
 233
 234 static const struct pmc_event_descr westmere_ex_event_table[] =
 235 {
 236         __PMC_EV_ALIAS_WESTMERE()
 237 };
 238
 239 static const struct pmc_event_descr corei7uc_event_table[] =
 240 {
 241         __PMC_EV_ALIAS_COREI7UC()
 242 };
 243
 244 static const struct pmc_event_descr haswelluc_event_table[] =
 245 {
 246         __PMC_EV_ALIAS_HASWELLUC()
 247 };
 248
 249 static const struct pmc_event_descr sandybridgeuc_event_table[] =
 250 {
 251         __PMC_EV_ALIAS_SANDYBRIDGEUC()
 252 };
 253
 254 static const struct pmc_event_descr westmereuc_event_table[] =
 255 {
 256         __PMC_EV_ALIAS_WESTMEREUC()
 257 };
 258
 259 /*
 260  * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...)
 261  *
 262  * Map a CPU to the PMC classes it supports.
 263  */
 264 #define PMC_MDEP_TABLE(N,C,...)                         \
 265         static const enum pmc_class N##_pmc_classes[] = {       \
 266                 PMC_CLASS_##C, __VA_ARGS__                      \
 267         }
 268
 269 PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 270 PMC_MDEP_TABLE(atom_silvermont, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 271 PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 272 PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 273 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 274 PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 275 PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 276 PMC_MDEP_TABLE(haswell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 277 PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 278 PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 279 PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 280 PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 281 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 282 PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 283 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 284 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 285 PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 286 PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 287 PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 288 PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE);
 289 PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K);
 290 PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON);
 291 PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450);
 292 PMC_MDEP_TABLE(ppc970, PPC970, PMC_CLASS_SOFT, PMC_CLASS_PPC970);
 293 PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT);
 294
 295 static const struct pmc_event_descr tsc_event_table[] =
 296 {
 297         __PMC_EV_TSC()
 298 };
 299
 300 #undef  PMC_CLASS_TABLE_DESC
 301 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR)    \
 302 static const struct pmc_class_descr NAME##_class_table_descr =  \
 303         {                                                       \
 304                 .pm_evc_name  = #CLASS "-",                     \
 305                 .pm_evc_name_size = sizeof(#CLASS "-") - 1,     \
 306                 .pm_evc_class = PMC_CLASS_##CLASS ,             \
 307                 .pm_evc_event_table = EVENTS##_event_table ,    \
 308                 .pm_evc_event_table_size =                      \
 309                         PMC_EVENT_TABLE_SIZE(EVENTS),           \
 310                 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \
 311         }
 312
 313 #if     defined(__i386__) || defined(__amd64__)
 314 PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf);
 315 PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
 316 PMC_CLASS_TABLE_DESC(atom_silvermont, IAP, atom_silvermont, iap);
 317 PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
 318 PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
 319 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
 320 PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap);
 321 PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap);
 322 PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell, iap);
 323 PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
 324 PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap);
 325 PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
 326 PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap);
 327 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
 328 PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap);
 329 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
 330 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
 331 PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp);
 332 PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp);
 333 PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
 334 #endif
 335 #if     defined(__i386__)
 336 PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
 337 #endif
 338 #if     defined(__i386__) || defined(__amd64__)
 339 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
 340 PMC_CLASS_TABLE_DESC(p4, P4, p4, p4);
 341 #endif
 342 #if     defined(__i386__)
 343 PMC_CLASS_TABLE_DESC(p5, P5, p5, p5);
 344 PMC_CLASS_TABLE_DESC(p6, P6, p6, p6);
 345 #endif
 346 #if     defined(__i386__) || defined(__amd64__)
 347 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
 348 #endif
 349 #if     defined(__XSCALE__)
 350 PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale);
 351 #endif
 352 #if defined(__mips__)
 353 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips);
 354 PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips);
 355 #endif /* __mips__ */
 356 #if defined(__powerpc__)
 357 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc);
 358 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc);
 359 #endif
 360
 361 static struct pmc_class_descr soft_class_table_descr =
 362 {
 363         .pm_evc_name  = "SOFT-",
 364         .pm_evc_name_size = sizeof("SOFT-") - 1,
 365         .pm_evc_class = PMC_CLASS_SOFT,
 366         .pm_evc_event_table = NULL,
 367         .pm_evc_event_table_size = 0,
 368         .pm_evc_allocate_pmc = soft_allocate_pmc
 369 };
 370
 371 #undef  PMC_CLASS_TABLE_DESC
 372
 373 static const struct pmc_class_descr **pmc_class_table;
 374 #define PMC_CLASS_TABLE_SIZE    cpu_info.pm_nclass
 375
 376 static const enum pmc_class *pmc_mdep_class_list;
 377 static size_t pmc_mdep_class_list_size;
 378
 379 /*
 380  * Mapping tables, mapping enumeration values to human readable
 381  * strings.
 382  */
 383
 384 static const char * pmc_capability_names[] = {
 385 #undef  __PMC_CAP
 386 #define __PMC_CAP(N,V,D)        #N ,
 387         __PMC_CAPS()
 388 };
 389
 390 static const char * pmc_class_names[] = {
 391 #undef  __PMC_CLASS
 392 #define __PMC_CLASS(C)  #C ,
 393         __PMC_CLASSES()
 394 };
 395
 396 struct pmc_cputype_map {
 397         enum pmc_cputype pm_cputype;
 398         const char      *pm_name;
 399 };
 400
 401 static const struct pmc_cputype_map pmc_cputype_names[] = {
 402 #undef  __PMC_CPU
 403 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } ,
 404         __PMC_CPUS()
 405 };
 406
 407 static const char * pmc_disposition_names[] = {
 408 #undef  __PMC_DISP
 409 #define __PMC_DISP(D)   #D ,
 410         __PMC_DISPOSITIONS()
 411 };
 412
 413 static const char * pmc_mode_names[] = {
 414 #undef  __PMC_MODE
 415 #define __PMC_MODE(M,N) #M ,
 416         __PMC_MODES()
 417 };
 418
 419 static const char * pmc_state_names[] = {
 420 #undef  __PMC_STATE
 421 #define __PMC_STATE(S) #S ,
 422         __PMC_STATES()
 423 };
 424
 425 /*
 426  * Filled in by pmc_init().
 427  */
 428 static int pmc_syscall = -1;
 429 static struct pmc_cpuinfo cpu_info;
 430 static struct pmc_op_getdyneventinfo soft_event_info;
 431
 432 /* Event masks for events */
 433 struct pmc_masks {
 434         const char      *pm_name;
 435         const uint64_t  pm_value;
 436 };
 437 #define PMCMASK(N,V)    { .pm_name = #N, .pm_value = (V) }
 438 #define NULLMASK        { .pm_name = NULL }
 439
 440 #if defined(__amd64__) || defined(__i386__)
 441 static int
 442 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask)
 443 {
 444         const struct pmc_masks *pm;
 445         char *q, *r;
 446         int c;
 447
 448         if (pmask == NULL)      /* no mask keywords */
 449                 return (-1);
 450         q = strchr(p, '=');     /* skip '=' */
 451         if (*++q == '\0')       /* no more data */
 452                 return (-1);
 453         c = 0;                  /* count of mask keywords seen */
 454         while ((r = strsep(&q, "+")) != NULL) {
 455                 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name);
 456                     pm++)
 457                         ;
 458                 if (pm->pm_name == NULL) /* not found */
 459                         return (-1);
 460                 *evmask |= pm->pm_value;
 461                 c++;
 462         }
 463         return (c);
 464 }
 465 #endif
 466
 467 #define KWMATCH(p,kw)           (strcasecmp((p), (kw)) == 0)
 468 #define KWPREFIXMATCH(p,kw)     (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
 469 #define EV_ALIAS(N,S)           { .pm_alias = N, .pm_spec = S }
 470
 471 #if defined(__i386__)
 472
 473 /*
 474  * AMD K7 (Athlon) CPUs.
 475  */
 476
 477 static struct pmc_event_alias k7_aliases[] = {
 478         EV_ALIAS("branches",            "k7-retired-branches"),
 479         EV_ALIAS("branch-mispredicts",  "k7-retired-branches-mispredicted"),
 480         EV_ALIAS("cycles",              "tsc"),
 481         EV_ALIAS("dc-misses",           "k7-dc-misses"),
 482         EV_ALIAS("ic-misses",           "k7-ic-misses"),
 483         EV_ALIAS("instructions",        "k7-retired-instructions"),
 484         EV_ALIAS("interrupts",          "k7-hardware-interrupts"),
 485         EV_ALIAS(NULL, NULL)
 486 };
 487
 488 #define K7_KW_COUNT     "count"
 489 #define K7_KW_EDGE      "edge"
 490 #define K7_KW_INV       "inv"
 491 #define K7_KW_OS        "os"
 492 #define K7_KW_UNITMASK  "unitmask"
 493 #define K7_KW_USR       "usr"
 494
 495 static int
 496 k7_allocate_pmc(enum pmc_event pe, char *ctrspec,
 497     struct pmc_op_pmcallocate *pmc_config)
 498 {
 499         char            *e, *p, *q;
 500         int             c, has_unitmask;
 501         uint32_t        count, unitmask;
 502
 503         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
 504         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 505
 506         if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 ||
 507             pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM ||
 508             pe == PMC_EV_K7_DC_WRITEBACKS) {
 509                 has_unitmask = 1;
 510                 unitmask = AMD_PMC_UNITMASK_MOESI;
 511         } else
 512                 unitmask = has_unitmask = 0;
 513
 514         while ((p = strsep(&ctrspec, ",")) != NULL) {
 515                 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) {
 516                         q = strchr(p, '=');
 517                         if (*++q == '\0') /* skip '=' */
 518                                 return (-1);
 519
 520                         count = strtol(q, &e, 0);
 521                         if (e == q || *e != '\0')
 522                                 return (-1);
 523
 524                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
 525                         pmc_config->pm_md.pm_amd.pm_amd_config |=
 526                             AMD_PMC_TO_COUNTER(count);
 527
 528                 } else if (KWMATCH(p, K7_KW_EDGE)) {
 529                         pmc_config->pm_caps |= PMC_CAP_EDGE;
 530                 } else if (KWMATCH(p, K7_KW_INV)) {
 531                         pmc_config->pm_caps |= PMC_CAP_INVERT;
 532                 } else if (KWMATCH(p, K7_KW_OS)) {
 533                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 534                 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) {
 535                         if (has_unitmask == 0)
 536                                 return (-1);
 537                         unitmask = 0;
 538                         q = strchr(p, '=');
 539                         if (*++q == '\0') /* skip '=' */
 540                                 return (-1);
 541
 542                         while ((c = tolower(*q++)) != 0)
 543                                 if (c == 'm')
 544                                         unitmask |= AMD_PMC_UNITMASK_M;
 545                                 else if (c == 'o')
 546                                         unitmask |= AMD_PMC_UNITMASK_O;
 547                                 else if (c == 'e')
 548                                         unitmask |= AMD_PMC_UNITMASK_E;
 549                                 else if (c == 's')
 550                                         unitmask |= AMD_PMC_UNITMASK_S;
 551                                 else if (c == 'i')
 552                                         unitmask |= AMD_PMC_UNITMASK_I;
 553                                 else if (c == '+')
 554                                         continue;
 555                                 else
 556                                         return (-1);
 557
 558                         if (unitmask == 0)
 559                                 return (-1);
 560
 561                 } else if (KWMATCH(p, K7_KW_USR)) {
 562                         pmc_config->pm_caps |= PMC_CAP_USER;
 563                 } else
 564                         return (-1);
 565         }
 566
 567         if (has_unitmask) {
 568                 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
 569                 pmc_config->pm_md.pm_amd.pm_amd_config |=
 570                     AMD_PMC_TO_UNITMASK(unitmask);
 571         }
 572
 573         return (0);
 574
 575 }
 576
 577 #endif
 578
 579 #if defined(__amd64__) || defined(__i386__)
 580
 581 /*
 582  * Intel Core (Family 6, Model E) PMCs.
 583  */
 584
 585 static struct pmc_event_alias core_aliases[] = {
 586         EV_ALIAS("branches",            "iap-br-instr-ret"),
 587         EV_ALIAS("branch-mispredicts",  "iap-br-mispred-ret"),
 588         EV_ALIAS("cycles",              "tsc-tsc"),
 589         EV_ALIAS("ic-misses",           "iap-icache-misses"),
 590         EV_ALIAS("instructions",        "iap-instr-ret"),
 591         EV_ALIAS("interrupts",          "iap-core-hw-int-rx"),
 592         EV_ALIAS("unhalted-cycles",     "iap-unhalted-core-cycles"),
 593         EV_ALIAS(NULL, NULL)
 594 };
 595
 596 /*
 597  * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H)
 598  * and Atom (Family 6, model 1CH) PMCs.
 599  *
 600  * We map aliases to events on the fixed-function counters if these
 601  * are present.  Note that not all CPUs in this family contain fixed-function
 602  * counters.
 603  */
 604
 605 static struct pmc_event_alias core2_aliases[] = {
 606         EV_ALIAS("branches",            "iap-br-inst-retired.any"),
 607         EV_ALIAS("branch-mispredicts",  "iap-br-inst-retired.mispred"),
 608         EV_ALIAS("cycles",              "tsc-tsc"),
 609         EV_ALIAS("ic-misses",           "iap-l1i-misses"),
 610         EV_ALIAS("instructions",        "iaf-instr-retired.any"),
 611         EV_ALIAS("interrupts",          "iap-hw-int-rcv"),
 612         EV_ALIAS("unhalted-cycles",     "iaf-cpu-clk-unhalted.core"),
 613         EV_ALIAS(NULL, NULL)
 614 };
 615
 616 static struct pmc_event_alias core2_aliases_without_iaf[] = {
 617         EV_ALIAS("branches",            "iap-br-inst-retired.any"),
 618         EV_ALIAS("branch-mispredicts",  "iap-br-inst-retired.mispred"),
 619         EV_ALIAS("cycles",              "tsc-tsc"),
 620         EV_ALIAS("ic-misses",           "iap-l1i-misses"),
 621         EV_ALIAS("instructions",        "iap-inst-retired.any_p"),
 622         EV_ALIAS("interrupts",          "iap-hw-int-rcv"),
 623         EV_ALIAS("unhalted-cycles",     "iap-cpu-clk-unhalted.core_p"),
 624         EV_ALIAS(NULL, NULL)
 625 };
 626
 627 #define atom_aliases                    core2_aliases
 628 #define atom_aliases_without_iaf        core2_aliases_without_iaf
 629 #define atom_silvermont_aliases         core2_aliases
 630 #define atom_silvermont_aliases_without_iaf     core2_aliases_without_iaf
 631 #define corei7_aliases                  core2_aliases
 632 #define corei7_aliases_without_iaf      core2_aliases_without_iaf
 633 #define nehalem_ex_aliases              core2_aliases
 634 #define nehalem_ex_aliases_without_iaf  core2_aliases_without_iaf
 635 #define haswell_aliases                 core2_aliases
 636 #define haswell_aliases_without_iaf     core2_aliases_without_iaf
 637 #define haswell_xeon_aliases                    core2_aliases
 638 #define haswell_xeon_aliases_without_iaf        core2_aliases_without_iaf
 639 #define ivybridge_aliases               core2_aliases
 640 #define ivybridge_aliases_without_iaf   core2_aliases_without_iaf
 641 #define ivybridge_xeon_aliases          core2_aliases
 642 #define ivybridge_xeon_aliases_without_iaf      core2_aliases_without_iaf
 643 #define sandybridge_aliases             core2_aliases
 644 #define sandybridge_aliases_without_iaf core2_aliases_without_iaf
 645 #define sandybridge_xeon_aliases        core2_aliases
 646 #define sandybridge_xeon_aliases_without_iaf    core2_aliases_without_iaf
 647 #define westmere_aliases                core2_aliases
 648 #define westmere_aliases_without_iaf    core2_aliases_without_iaf
 649 #define westmere_ex_aliases             core2_aliases
 650 #define westmere_ex_aliases_without_iaf core2_aliases_without_iaf
 651
 652 #define IAF_KW_OS               "os"
 653 #define IAF_KW_USR              "usr"
 654 #define IAF_KW_ANYTHREAD        "anythread"
 655
 656 /*
 657  * Parse an event specifier for Intel fixed function counters.
 658  */
 659 static int
 660 iaf_allocate_pmc(enum pmc_event pe, char *ctrspec,
 661     struct pmc_op_pmcallocate *pmc_config)
 662 {
 663         char *p;
 664
 665         (void) pe;
 666
 667         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 668         pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0;
 669
 670         while ((p = strsep(&ctrspec, ",")) != NULL) {
 671                 if (KWMATCH(p, IAF_KW_OS))
 672                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 673                 else if (KWMATCH(p, IAF_KW_USR))
 674                         pmc_config->pm_caps |= PMC_CAP_USER;
 675                 else if (KWMATCH(p, IAF_KW_ANYTHREAD))
 676                         pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY;
 677                 else
 678                         return (-1);
 679         }
 680
 681         return (0);
 682 }
 683
 684 /*
 685  * Core/Core2 support.
 686  */
 687
 688 #define IAP_KW_AGENT            "agent"
 689 #define IAP_KW_ANYTHREAD        "anythread"
 690 #define IAP_KW_CACHESTATE       "cachestate"
 691 #define IAP_KW_CMASK            "cmask"
 692 #define IAP_KW_CORE             "core"
 693 #define IAP_KW_EDGE             "edge"
 694 #define IAP_KW_INV              "inv"
 695 #define IAP_KW_OS               "os"
 696 #define IAP_KW_PREFETCH         "prefetch"
 697 #define IAP_KW_SNOOPRESPONSE    "snoopresponse"
 698 #define IAP_KW_SNOOPTYPE        "snooptype"
 699 #define IAP_KW_TRANSITION       "trans"
 700 #define IAP_KW_USR              "usr"
 701 #define IAP_KW_RSP              "rsp"
 702
 703 static struct pmc_masks iap_core_mask[] = {
 704         PMCMASK(all,    (0x3 << 14)),
 705         PMCMASK(this,   (0x1 << 14)),
 706         NULLMASK
 707 };
 708
 709 static struct pmc_masks iap_agent_mask[] = {
 710         PMCMASK(this,   0),
 711         PMCMASK(any,    (0x1 << 13)),
 712         NULLMASK
 713 };
 714
 715 static struct pmc_masks iap_prefetch_mask[] = {
 716         PMCMASK(both,           (0x3 << 12)),
 717         PMCMASK(only,           (0x1 << 12)),
 718         PMCMASK(exclude,        0),
 719         NULLMASK
 720 };
 721
 722 static struct pmc_masks iap_cachestate_mask[] = {
 723         PMCMASK(i,              (1 <<  8)),
 724         PMCMASK(s,              (1 <<  9)),
 725         PMCMASK(e,              (1 << 10)),
 726         PMCMASK(m,              (1 << 11)),
 727         NULLMASK
 728 };
 729
 730 static struct pmc_masks iap_snoopresponse_mask[] = {
 731         PMCMASK(clean,          (1 << 8)),
 732         PMCMASK(hit,            (1 << 9)),
 733         PMCMASK(hitm,           (1 << 11)),
 734         NULLMASK
 735 };
 736
 737 static struct pmc_masks iap_snooptype_mask[] = {
 738         PMCMASK(cmp2s,          (1 << 8)),
 739         PMCMASK(cmp2i,          (1 << 9)),
 740         NULLMASK
 741 };
 742
 743 static struct pmc_masks iap_transition_mask[] = {
 744         PMCMASK(any,            0x00),
 745         PMCMASK(frequency,      0x10),
 746         NULLMASK
 747 };
 748
 749 static struct pmc_masks iap_rsp_mask_i7_wm[] = {
 750         PMCMASK(DMND_DATA_RD,           (1 <<  0)),
 751         PMCMASK(DMND_RFO,               (1 <<  1)),
 752         PMCMASK(DMND_IFETCH,            (1 <<  2)),
 753         PMCMASK(WB,                     (1 <<  3)),
 754         PMCMASK(PF_DATA_RD,             (1 <<  4)),
 755         PMCMASK(PF_RFO,                 (1 <<  5)),
 756         PMCMASK(PF_IFETCH,              (1 <<  6)),
 757         PMCMASK(OTHER,                  (1 <<  7)),
 758         PMCMASK(UNCORE_HIT,             (1 <<  8)),
 759         PMCMASK(OTHER_CORE_HIT_SNP,     (1 <<  9)),
 760         PMCMASK(OTHER_CORE_HITM,        (1 << 10)),
 761         PMCMASK(REMOTE_CACHE_FWD,       (1 << 12)),
 762         PMCMASK(REMOTE_DRAM,            (1 << 13)),
 763         PMCMASK(LOCAL_DRAM,             (1 << 14)),
 764         PMCMASK(NON_DRAM,               (1 << 15)),
 765         NULLMASK
 766 };
 767
 768 static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = {
 769         PMCMASK(REQ_DMND_DATA_RD,       (1ULL <<  0)),
 770         PMCMASK(REQ_DMND_RFO,           (1ULL <<  1)),
 771         PMCMASK(REQ_DMND_IFETCH,        (1ULL <<  2)),
 772         PMCMASK(REQ_WB,                 (1ULL <<  3)),
 773         PMCMASK(REQ_PF_DATA_RD,         (1ULL <<  4)),
 774         PMCMASK(REQ_PF_RFO,             (1ULL <<  5)),
 775         PMCMASK(REQ_PF_IFETCH,          (1ULL <<  6)),
 776         PMCMASK(REQ_PF_LLC_DATA_RD,     (1ULL <<  7)),
 777         PMCMASK(REQ_PF_LLC_RFO,         (1ULL <<  8)),
 778         PMCMASK(REQ_PF_LLC_IFETCH,      (1ULL <<  9)),
 779         PMCMASK(REQ_BUS_LOCKS,          (1ULL << 10)),
 780         PMCMASK(REQ_STRM_ST,            (1ULL << 11)),
 781         PMCMASK(REQ_OTHER,              (1ULL << 15)),
 782         PMCMASK(RES_ANY,                (1ULL << 16)),
 783         PMCMASK(RES_SUPPLIER_SUPP,      (1ULL << 17)),
 784         PMCMASK(RES_SUPPLIER_LLC_HITM,  (1ULL << 18)),
 785         PMCMASK(RES_SUPPLIER_LLC_HITE,  (1ULL << 19)),
 786         PMCMASK(RES_SUPPLIER_LLC_HITS,  (1ULL << 20)),
 787         PMCMASK(RES_SUPPLIER_LLC_HITF,  (1ULL << 21)),
 788         PMCMASK(RES_SUPPLIER_LOCAL,     (1ULL << 22)),
 789         PMCMASK(RES_SNOOP_SNP_NONE,     (1ULL << 31)),
 790         PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
 791         PMCMASK(RES_SNOOP_SNP_MISS,     (1ULL << 33)),
 792         PMCMASK(RES_SNOOP_HIT_NO_FWD,   (1ULL << 34)),
 793         PMCMASK(RES_SNOOP_HIT_FWD,      (1ULL << 35)),
 794         PMCMASK(RES_SNOOP_HITM,         (1ULL << 36)),
 795         PMCMASK(RES_NON_DRAM,           (1ULL << 37)),
 796         NULLMASK
 797 };
 798
 799 static struct pmc_masks iap_rsp_mask_haswell[] = {
 800         PMCMASK(REQ_DMND_DATA_RD,       (1ULL <<  0)),
 801         PMCMASK(REQ_DMND_RFO,           (1ULL <<  1)),
 802         PMCMASK(REQ_DMND_IFETCH,        (1ULL <<  2)),
 803         PMCMASK(REQ_PF_DATA_RD,         (1ULL <<  4)),
 804         PMCMASK(REQ_PF_RFO,             (1ULL <<  5)),
 805         PMCMASK(REQ_PF_IFETCH,          (1ULL <<  6)),
 806         PMCMASK(REQ_OTHER,              (1ULL << 15)),
 807         PMCMASK(RES_ANY,                (1ULL << 16)),
 808         PMCMASK(RES_SUPPLIER_SUPP,      (1ULL << 17)),
 809         PMCMASK(RES_SUPPLIER_LLC_HITM,  (1ULL << 18)),
 810         PMCMASK(RES_SUPPLIER_LLC_HITE,  (1ULL << 19)),
 811         PMCMASK(RES_SUPPLIER_LLC_HITS,  (1ULL << 20)),
 812         PMCMASK(RES_SUPPLIER_LLC_HITF,  (1ULL << 21)),
 813         PMCMASK(RES_SUPPLIER_LOCAL,     (1ULL << 22)),
 814         PMCMASK(RES_SNOOP_SNP_NONE,     (1ULL << 31)),
 815         PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
 816         PMCMASK(RES_SNOOP_SNP_MISS,     (1ULL << 33)),
 817         PMCMASK(RES_SNOOP_HIT_NO_FWD,   (1ULL << 34)),
 818         PMCMASK(RES_SNOOP_HIT_FWD,      (1ULL << 35)),
 819         PMCMASK(RES_SNOOP_HITM,         (1ULL << 36)),
 820         PMCMASK(RES_NON_DRAM,           (1ULL << 37)),
 821         NULLMASK
 822 };
 823
 824 static int
 825 iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
 826     struct pmc_op_pmcallocate *pmc_config)
 827 {
 828         char *e, *p, *q;
 829         uint64_t cachestate, evmask, rsp;
 830         int count, n;
 831
 832         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
 833             PMC_CAP_QUALIFIER);
 834         pmc_config->pm_md.pm_iap.pm_iap_config = 0;
 835
 836         cachestate = evmask = rsp = 0;
 837
 838         /* Parse additional modifiers if present */
 839         while ((p = strsep(&ctrspec, ",")) != NULL) {
 840
 841                 n = 0;
 842                 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) {
 843                         q = strchr(p, '=');
 844                         if (*++q == '\0') /* skip '=' */
 845                                 return (-1);
 846                         count = strtol(q, &e, 0);
 847                         if (e == q || *e != '\0')
 848                                 return (-1);
 849                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
 850                         pmc_config->pm_md.pm_iap.pm_iap_config |=
 851                             IAP_CMASK(count);
 852                 } else if (KWMATCH(p, IAP_KW_EDGE)) {
 853                         pmc_config->pm_caps |= PMC_CAP_EDGE;
 854                 } else if (KWMATCH(p, IAP_KW_INV)) {
 855                         pmc_config->pm_caps |= PMC_CAP_INVERT;
 856                 } else if (KWMATCH(p, IAP_KW_OS)) {
 857                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 858                 } else if (KWMATCH(p, IAP_KW_USR)) {
 859                         pmc_config->pm_caps |= PMC_CAP_USER;
 860                 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) {
 861                         pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY;
 862                 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) {
 863                         n = pmc_parse_mask(iap_core_mask, p, &evmask);
 864                         if (n != 1)
 865                                 return (-1);
 866                 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) {
 867                         n = pmc_parse_mask(iap_agent_mask, p, &evmask);
 868                         if (n != 1)
 869                                 return (-1);
 870                 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) {
 871                         n = pmc_parse_mask(iap_prefetch_mask, p, &evmask);
 872                         if (n != 1)
 873                                 return (-1);
 874                 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) {
 875                         n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate);
 876                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE &&
 877                     KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) {
 878                         n = pmc_parse_mask(iap_transition_mask, p, &evmask);
 879                         if (n != 1)
 880                                 return (-1);
 881                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM ||
 882                     cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT ||
 883                     cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 ||
 884                     cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) {
 885                         if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) {
 886                                 n = pmc_parse_mask(iap_snoopresponse_mask, p,
 887                                     &evmask);
 888                         } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) {
 889                                 n = pmc_parse_mask(iap_snooptype_mask, p,
 890                                     &evmask);
 891                         } else
 892                                 return (-1);
 893                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 ||
 894                     cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE ||
 895                     cpu_info.pm_cputype == PMC_CPU_INTEL_NEHALEM_EX ||
 896                     cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE_EX) {
 897                         if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
 898                                 n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp);
 899                         } else
 900                                 return (-1);
 901                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
 902                     cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON ||
 903                         cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE ||
 904                         cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON ) {
 905                         if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
 906                                 n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp);
 907                         } else
 908                                 return (-1);
 909                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL ||
 910                         cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL_XEON) {
 911                         if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
 912                                 n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp);
 913                         } else
 914                                 return (-1);
 915                 } else
 916                         return (-1);
 917
 918                 if (n < 0)      /* Parsing failed. */
 919                         return (-1);
 920         }
 921
 922         pmc_config->pm_md.pm_iap.pm_iap_config |= evmask;
 923
 924         /*
 925          * If the event requires a 'cachestate' qualifier but was not
 926          * specified by the user, use a sensible default.
 927          */
 928         switch (pe) {
 929         case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */
 930         case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */
 931         case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */
 932         case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */
 933         case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */
 934         case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */
 935         case PMC_EV_IAP_EVENT_32H: /* Core */
 936         case PMC_EV_IAP_EVENT_40H: /* Core */
 937         case PMC_EV_IAP_EVENT_41H: /* Core */
 938         case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */
 939                 if (cachestate == 0)
 940                         cachestate = (0xF << 8);
 941                 break;
 942         case PMC_EV_IAP_EVENT_77H: /* Atom */
 943                 /* IAP_EVENT_77H only accepts a cachestate qualifier on the
 944                  * Atom processor
 945                  */
 946                 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0)
 947                         cachestate = (0xF << 8);
 948             break;
 949         default:
 950                 break;
 951         }
 952
 953         pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate;
 954         pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp;
 955
 956         return (0);
 957 }
 958
 959 /*
 960  * Intel Uncore.
 961  */
 962
 963 static int
 964 ucf_allocate_pmc(enum pmc_event pe, char *ctrspec,
 965     struct pmc_op_pmcallocate *pmc_config)
 966 {
 967         (void) pe;
 968         (void) ctrspec;
 969
 970         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 971         pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0;
 972
 973         return (0);
 974 }
 975
 976 #define UCP_KW_CMASK            "cmask"
 977 #define UCP_KW_EDGE             "edge"
 978 #define UCP_KW_INV              "inv"
 979
 980 static int
 981 ucp_allocate_pmc(enum pmc_event pe, char *ctrspec,
 982     struct pmc_op_pmcallocate *pmc_config)
 983 {
 984         char *e, *p, *q;
 985         int count, n;
 986
 987         (void) pe;
 988
 989         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
 990             PMC_CAP_QUALIFIER);
 991         pmc_config->pm_md.pm_ucp.pm_ucp_config = 0;
 992
 993         /* Parse additional modifiers if present */
 994         while ((p = strsep(&ctrspec, ",")) != NULL) {
 995
 996                 n = 0;
 997                 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) {
 998                         q = strchr(p, '=');
 999                         if (*++q == '\0') /* skip '=' */
1000                                 return (-1);
1001                         count = strtol(q, &e, 0);
1002                         if (e == q || *e != '\0')
1003                                 return (-1);
1004                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1005                         pmc_config->pm_md.pm_ucp.pm_ucp_config |=
1006                             UCP_CMASK(count);
1007                 } else if (KWMATCH(p, UCP_KW_EDGE)) {
1008                         pmc_config->pm_caps |= PMC_CAP_EDGE;
1009                 } else if (KWMATCH(p, UCP_KW_INV)) {
1010                         pmc_config->pm_caps |= PMC_CAP_INVERT;
1011                 } else
1012                         return (-1);
1013
1014                 if (n < 0)      /* Parsing failed. */
1015                         return (-1);
1016         }
1017
1018         return (0);
1019 }
1020
1021 /*
1022  * AMD K8 PMCs.
1023  *
1024  * These are very similar to AMD K7 PMCs, but support more kinds of
1025  * events.
1026  */
1027
1028 static struct pmc_event_alias k8_aliases[] = {
1029         EV_ALIAS("branches",            "k8-fr-retired-taken-branches"),
1030         EV_ALIAS("branch-mispredicts",
1031             "k8-fr-retired-taken-branches-mispredicted"),
1032         EV_ALIAS("cycles",              "tsc"),
1033         EV_ALIAS("dc-misses",           "k8-dc-miss"),
1034         EV_ALIAS("ic-misses",           "k8-ic-miss"),
1035         EV_ALIAS("instructions",        "k8-fr-retired-x86-instructions"),
1036         EV_ALIAS("interrupts",          "k8-fr-taken-hardware-interrupts"),
1037         EV_ALIAS("unhalted-cycles",     "k8-bu-cpu-clk-unhalted"),
1038         EV_ALIAS(NULL, NULL)
1039 };
1040
1041 #define __K8MASK(N,V) PMCMASK(N,(1 << (V)))
1042
1043 /*
1044  * Parsing tables
1045  */
1046
1047 /* fp dispatched fpu ops */
1048 static const struct pmc_masks k8_mask_fdfo[] = {
1049         __K8MASK(add-pipe-excluding-junk-ops,   0),
1050         __K8MASK(multiply-pipe-excluding-junk-ops,      1),
1051         __K8MASK(store-pipe-excluding-junk-ops, 2),
1052         __K8MASK(add-pipe-junk-ops,             3),
1053         __K8MASK(multiply-pipe-junk-ops,        4),
1054         __K8MASK(store-pipe-junk-ops,           5),
1055         NULLMASK
1056 };
1057
1058 /* ls segment register loads */
1059 static const struct pmc_masks k8_mask_lsrl[] = {
1060         __K8MASK(es,    0),
1061         __K8MASK(cs,    1),
1062         __K8MASK(ss,    2),
1063         __K8MASK(ds,    3),
1064         __K8MASK(fs,    4),
1065         __K8MASK(gs,    5),
1066         __K8MASK(hs,    6),
1067         NULLMASK
1068 };
1069
1070 /* ls locked operation */
1071 static const struct pmc_masks k8_mask_llo[] = {
1072         __K8MASK(locked-instructions,   0),
1073         __K8MASK(cycles-in-request,     1),
1074         __K8MASK(cycles-to-complete,    2),
1075         NULLMASK
1076 };
1077
1078 /* dc refill from {l2,system} and dc copyback */
1079 static const struct pmc_masks k8_mask_dc[] = {
1080         __K8MASK(invalid,       0),
1081         __K8MASK(shared,        1),
1082         __K8MASK(exclusive,     2),
1083         __K8MASK(owner,         3),
1084         __K8MASK(modified,      4),
1085         NULLMASK
1086 };
1087
1088 /* dc one bit ecc error */
1089 static const struct pmc_masks k8_mask_dobee[] = {
1090         __K8MASK(scrubber,      0),
1091         __K8MASK(piggyback,     1),
1092         NULLMASK
1093 };
1094
1095 /* dc dispatched prefetch instructions */
1096 static const struct pmc_masks k8_mask_ddpi[] = {
1097         __K8MASK(load,  0),
1098         __K8MASK(store, 1),
1099         __K8MASK(nta,   2),
1100         NULLMASK
1101 };
1102
1103 /* dc dcache accesses by locks */
1104 static const struct pmc_masks k8_mask_dabl[] = {
1105         __K8MASK(accesses,      0),
1106         __K8MASK(misses,        1),
1107         NULLMASK
1108 };
1109
1110 /* bu internal l2 request */
1111 static const struct pmc_masks k8_mask_bilr[] = {
1112         __K8MASK(ic-fill,       0),
1113         __K8MASK(dc-fill,       1),
1114         __K8MASK(tlb-reload,    2),
1115         __K8MASK(tag-snoop,     3),
1116         __K8MASK(cancelled,     4),
1117         NULLMASK
1118 };
1119
1120 /* bu fill request l2 miss */
1121 static const struct pmc_masks k8_mask_bfrlm[] = {
1122         __K8MASK(ic-fill,       0),
1123         __K8MASK(dc-fill,       1),
1124         __K8MASK(tlb-reload,    2),
1125         NULLMASK
1126 };
1127
1128 /* bu fill into l2 */
1129 static const struct pmc_masks k8_mask_bfil[] = {
1130         __K8MASK(dirty-l2-victim,       0),
1131         __K8MASK(victim-from-l2,        1),
1132         NULLMASK
1133 };
1134
1135 /* fr retired fpu instructions */
1136 static const struct pmc_masks k8_mask_frfi[] = {
1137         __K8MASK(x87,                   0),
1138         __K8MASK(mmx-3dnow,             1),
1139         __K8MASK(packed-sse-sse2,       2),
1140         __K8MASK(scalar-sse-sse2,       3),
1141         NULLMASK
1142 };
1143
1144 /* fr retired fastpath double op instructions */
1145 static const struct pmc_masks k8_mask_frfdoi[] = {
1146         __K8MASK(low-op-pos-0,          0),
1147         __K8MASK(low-op-pos-1,          1),
1148         __K8MASK(low-op-pos-2,          2),
1149         NULLMASK
1150 };
1151
1152 /* fr fpu exceptions */
1153 static const struct pmc_masks k8_mask_ffe[] = {
1154         __K8MASK(x87-reclass-microfaults,       0),
1155         __K8MASK(sse-retype-microfaults,        1),
1156         __K8MASK(sse-reclass-microfaults,       2),
1157         __K8MASK(sse-and-x87-microtraps,        3),
1158         NULLMASK
1159 };
1160
1161 /* nb memory controller page access event */
1162 static const struct pmc_masks k8_mask_nmcpae[] = {
1163         __K8MASK(page-hit,      0),
1164         __K8MASK(page-miss,     1),
1165         __K8MASK(page-conflict, 2),
1166         NULLMASK
1167 };
1168
1169 /* nb memory controller turnaround */
1170 static const struct pmc_masks k8_mask_nmct[] = {
1171         __K8MASK(dimm-turnaround,               0),
1172         __K8MASK(read-to-write-turnaround,      1),
1173         __K8MASK(write-to-read-turnaround,      2),
1174         NULLMASK
1175 };
1176
1177 /* nb memory controller bypass saturation */
1178 static const struct pmc_masks k8_mask_nmcbs[] = {
1179         __K8MASK(memory-controller-hi-pri-bypass,       0),
1180         __K8MASK(memory-controller-lo-pri-bypass,       1),
1181         __K8MASK(dram-controller-interface-bypass,      2),
1182         __K8MASK(dram-controller-queue-bypass,          3),
1183         NULLMASK
1184 };
1185
1186 /* nb sized commands */
1187 static const struct pmc_masks k8_mask_nsc[] = {
1188         __K8MASK(nonpostwrszbyte,       0),
1189         __K8MASK(nonpostwrszdword,      1),
1190         __K8MASK(postwrszbyte,          2),
1191         __K8MASK(postwrszdword,         3),
1192         __K8MASK(rdszbyte,              4),
1193         __K8MASK(rdszdword,             5),
1194         __K8MASK(rdmodwr,               6),
1195         NULLMASK
1196 };
1197
1198 /* nb probe result */
1199 static const struct pmc_masks k8_mask_npr[] = {
1200         __K8MASK(probe-miss,            0),
1201         __K8MASK(probe-hit,             1),
1202         __K8MASK(probe-hit-dirty-no-memory-cancel, 2),
1203         __K8MASK(probe-hit-dirty-with-memory-cancel, 3),
1204         NULLMASK
1205 };
1206
1207 /* nb hypertransport bus bandwidth */
1208 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */
1209         __K8MASK(command,       0),
1210         __K8MASK(data,  1),
1211         __K8MASK(buffer-release, 2),
1212         __K8MASK(nop,   3),
1213         NULLMASK
1214 };
1215
1216 #undef  __K8MASK
1217
1218 #define K8_KW_COUNT     "count"
1219 #define K8_KW_EDGE      "edge"
1220 #define K8_KW_INV       "inv"
1221 #define K8_KW_MASK      "mask"
1222 #define K8_KW_OS        "os"
1223 #define K8_KW_USR       "usr"
1224
1225 static int
1226 k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
1227     struct pmc_op_pmcallocate *pmc_config)
1228 {
1229         char            *e, *p, *q;
1230         int             n;
1231         uint32_t        count;
1232         uint64_t        evmask;
1233         const struct pmc_masks  *pm, *pmask;
1234
1235         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1236         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
1237
1238         pmask = NULL;
1239         evmask = 0;
1240
1241 #define __K8SETMASK(M) pmask = k8_mask_##M
1242
1243         /* setup parsing tables */
1244         switch (pe) {
1245         case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1246                 __K8SETMASK(fdfo);
1247                 break;
1248         case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD:
1249                 __K8SETMASK(lsrl);
1250                 break;
1251         case PMC_EV_K8_LS_LOCKED_OPERATION:
1252                 __K8SETMASK(llo);
1253                 break;
1254         case PMC_EV_K8_DC_REFILL_FROM_L2:
1255         case PMC_EV_K8_DC_REFILL_FROM_SYSTEM:
1256         case PMC_EV_K8_DC_COPYBACK:
1257                 __K8SETMASK(dc);
1258                 break;
1259         case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR:
1260                 __K8SETMASK(dobee);
1261                 break;
1262         case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS:
1263                 __K8SETMASK(ddpi);
1264                 break;
1265         case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1266                 __K8SETMASK(dabl);
1267                 break;
1268         case PMC_EV_K8_BU_INTERNAL_L2_REQUEST:
1269                 __K8SETMASK(bilr);
1270                 break;
1271         case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS:
1272                 __K8SETMASK(bfrlm);
1273                 break;
1274         case PMC_EV_K8_BU_FILL_INTO_L2:
1275                 __K8SETMASK(bfil);
1276                 break;
1277         case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1278                 __K8SETMASK(frfi);
1279                 break;
1280         case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1281                 __K8SETMASK(frfdoi);
1282                 break;
1283         case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1284                 __K8SETMASK(ffe);
1285                 break;
1286         case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT:
1287                 __K8SETMASK(nmcpae);
1288                 break;
1289         case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND:
1290                 __K8SETMASK(nmct);
1291                 break;
1292         case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION:
1293                 __K8SETMASK(nmcbs);
1294                 break;
1295         case PMC_EV_K8_NB_SIZED_COMMANDS:
1296                 __K8SETMASK(nsc);
1297                 break;
1298         case PMC_EV_K8_NB_PROBE_RESULT:
1299                 __K8SETMASK(npr);
1300                 break;
1301         case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH:
1302         case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH:
1303         case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH:
1304                 __K8SETMASK(nhbb);
1305                 break;
1306
1307         default:
1308                 break;          /* no options defined */
1309         }
1310
1311         while ((p = strsep(&ctrspec, ",")) != NULL) {
1312                 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) {
1313                         q = strchr(p, '=');
1314                         if (*++q == '\0') /* skip '=' */
1315                                 return (-1);
1316
1317                         count = strtol(q, &e, 0);
1318                         if (e == q || *e != '\0')
1319                                 return (-1);
1320
1321                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1322                         pmc_config->pm_md.pm_amd.pm_amd_config |=
1323                             AMD_PMC_TO_COUNTER(count);
1324
1325                 } else if (KWMATCH(p, K8_KW_EDGE)) {
1326                         pmc_config->pm_caps |= PMC_CAP_EDGE;
1327                 } else if (KWMATCH(p, K8_KW_INV)) {
1328                         pmc_config->pm_caps |= PMC_CAP_INVERT;
1329                 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) {
1330                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1331                                 return (-1);
1332                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1333                 } else if (KWMATCH(p, K8_KW_OS)) {
1334                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1335                 } else if (KWMATCH(p, K8_KW_USR)) {
1336                         pmc_config->pm_caps |= PMC_CAP_USER;
1337                 } else
1338                         return (-1);
1339         }
1340
1341         /* other post processing */
1342         switch (pe) {
1343         case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1344         case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED:
1345         case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS:
1346         case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1347         case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1348         case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1349                 /* XXX only available in rev B and later */
1350                 break;
1351         case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1352                 /* XXX only available in rev C and later */
1353                 break;
1354         case PMC_EV_K8_LS_LOCKED_OPERATION:
1355                 /* XXX CPU Rev A,B evmask is to be zero */
1356                 if (evmask & (evmask - 1)) /* > 1 bit set */
1357                         return (-1);
1358                 if (evmask == 0) {
1359                         evmask = 0x01; /* Rev C and later: #instrs */
1360                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1361                 }
1362                 break;
1363         default:
1364                 if (evmask == 0 && pmask != NULL) {
1365                         for (pm = pmask; pm->pm_name; pm++)
1366                                 evmask |= pm->pm_value;
1367                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1368                 }
1369         }
1370
1371         if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
1372                 pmc_config->pm_md.pm_amd.pm_amd_config =
1373                     AMD_PMC_TO_UNITMASK(evmask);
1374
1375         return (0);
1376 }
1377
1378 #endif
1379
1380 #if defined(__amd64__) || defined(__i386__)
1381
1382 /*
1383  * Intel P4 PMCs
1384  */
1385
1386 static struct pmc_event_alias p4_aliases[] = {
1387         EV_ALIAS("branches",            "p4-branch-retired,mask=mmtp+mmtm"),
1388         EV_ALIAS("branch-mispredicts",  "p4-mispred-branch-retired"),
1389         EV_ALIAS("cycles",              "tsc"),
1390         EV_ALIAS("instructions",
1391             "p4-instr-retired,mask=nbogusntag+nbogustag"),
1392         EV_ALIAS("unhalted-cycles",     "p4-global-power-events"),
1393         EV_ALIAS(NULL, NULL)
1394 };
1395
1396 #define P4_KW_ACTIVE    "active"
1397 #define P4_KW_ACTIVE_ANY "any"
1398 #define P4_KW_ACTIVE_BOTH "both"
1399 #define P4_KW_ACTIVE_NONE "none"
1400 #define P4_KW_ACTIVE_SINGLE "single"
1401 #define P4_KW_BUSREQTYPE "busreqtype"
1402 #define P4_KW_CASCADE   "cascade"
1403 #define P4_KW_EDGE      "edge"
1404 #define P4_KW_INV       "complement"
1405 #define P4_KW_OS        "os"
1406 #define P4_KW_MASK      "mask"
1407 #define P4_KW_PRECISE   "precise"
1408 #define P4_KW_TAG       "tag"
1409 #define P4_KW_THRESHOLD "threshold"
1410 #define P4_KW_USR       "usr"
1411
1412 #define __P4MASK(N,V) PMCMASK(N, (1 << (V)))
1413
1414 static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */
1415         __P4MASK(dd, 0),
1416         __P4MASK(db, 1),
1417         __P4MASK(di, 2),
1418         __P4MASK(bd, 3),
1419         __P4MASK(bb, 4),
1420         __P4MASK(bi, 5),
1421         __P4MASK(id, 6),
1422         __P4MASK(ib, 7),
1423         NULLMASK
1424 };
1425
1426 static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */
1427         __P4MASK(tcmiss, 0),
1428         NULLMASK,
1429 };
1430
1431 static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */
1432         __P4MASK(hit, 0),
1433         __P4MASK(miss, 1),
1434         __P4MASK(hit-uc, 2),
1435         NULLMASK
1436 };
1437
1438 static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */
1439         __P4MASK(st-rb-full, 2),
1440         __P4MASK(64k-conf, 3),
1441         NULLMASK
1442 };
1443
1444 static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */
1445         __P4MASK(lsc, 0),
1446         __P4MASK(ssc, 1),
1447         NULLMASK
1448 };
1449
1450 static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */
1451         __P4MASK(split-ld, 1),
1452         NULLMASK
1453 };
1454
1455 static const struct pmc_masks p4_mask_spr[] = { /* store port replay */
1456         __P4MASK(split-st, 1),
1457         NULLMASK
1458 };
1459
1460 static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */
1461         __P4MASK(no-sta, 1),
1462         __P4MASK(no-std, 3),
1463         __P4MASK(partial-data, 4),
1464         __P4MASK(unalgn-addr, 5),
1465         NULLMASK
1466 };
1467
1468 static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */
1469         __P4MASK(dtmiss, 0),
1470         __P4MASK(itmiss, 1),
1471         NULLMASK
1472 };
1473
1474 static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */
1475         __P4MASK(rd-2ndl-hits, 0),
1476         __P4MASK(rd-2ndl-hite, 1),
1477         __P4MASK(rd-2ndl-hitm, 2),
1478         __P4MASK(rd-3rdl-hits, 3),
1479         __P4MASK(rd-3rdl-hite, 4),
1480         __P4MASK(rd-3rdl-hitm, 5),
1481         __P4MASK(rd-2ndl-miss, 8),
1482         __P4MASK(rd-3rdl-miss, 9),
1483         __P4MASK(wr-2ndl-miss, 10),
1484         NULLMASK
1485 };
1486
1487 static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */
1488         __P4MASK(all-read, 5),
1489         __P4MASK(all-write, 6),
1490         __P4MASK(mem-uc, 7),
1491         __P4MASK(mem-wc, 8),
1492         __P4MASK(mem-wt, 9),
1493         __P4MASK(mem-wp, 10),
1494         __P4MASK(mem-wb, 11),
1495         __P4MASK(own, 13),
1496         __P4MASK(other, 14),
1497         __P4MASK(prefetch, 15),
1498         NULLMASK
1499 };
1500
1501 static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */
1502         __P4MASK(all-read, 5),
1503         __P4MASK(all-write, 6),
1504         __P4MASK(mem-uc, 7),
1505         __P4MASK(mem-wc, 8),
1506         __P4MASK(mem-wt, 9),
1507         __P4MASK(mem-wp, 10),
1508         __P4MASK(mem-wb, 11),
1509         __P4MASK(own, 13),
1510         __P4MASK(other, 14),
1511         __P4MASK(prefetch, 15),
1512         NULLMASK
1513 };
1514
1515 static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */
1516         __P4MASK(drdy-drv, 0),
1517         __P4MASK(drdy-own, 1),
1518         __P4MASK(drdy-other, 2),
1519         __P4MASK(dbsy-drv, 3),
1520         __P4MASK(dbsy-own, 4),
1521         __P4MASK(dbsy-other, 5),
1522         NULLMASK
1523 };
1524
1525 static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */
1526         __P4MASK(req-type0, 0),
1527         __P4MASK(req-type1, 1),
1528         __P4MASK(req-len0, 2),
1529         __P4MASK(req-len1, 3),
1530         __P4MASK(req-io-type, 5),
1531         __P4MASK(req-lock-type, 6),
1532         __P4MASK(req-cache-type, 7),
1533         __P4MASK(req-split-type, 8),
1534         __P4MASK(req-dem-type, 9),
1535         __P4MASK(req-ord-type, 10),
1536         __P4MASK(mem-type0, 11),
1537         __P4MASK(mem-type1, 12),
1538         __P4MASK(mem-type2, 13),
1539         NULLMASK
1540 };
1541
1542 static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */
1543         __P4MASK(all, 15),
1544         NULLMASK
1545 };
1546
1547 static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */
1548         __P4MASK(all, 15),
1549         NULLMASK
1550 };
1551
1552 static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */
1553         __P4MASK(all, 15),
1554         NULLMASK
1555 };
1556
1557 static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */
1558         __P4MASK(all, 15),
1559         NULLMASK
1560 };
1561
1562 static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */
1563         __P4MASK(all, 15),
1564         NULLMASK
1565 };
1566
1567 static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */
1568         __P4MASK(all, 15),
1569         NULLMASK
1570 };
1571
1572 static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */
1573         __P4MASK(all, 15),
1574         NULLMASK
1575 };
1576
1577 static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */
1578         __P4MASK(all, 15),
1579         NULLMASK
1580 };
1581
1582 static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */
1583         __P4MASK(allp0, 3),
1584         __P4MASK(allp2, 4),
1585         NULLMASK
1586 };
1587
1588 static const struct pmc_masks p4_mask_gpe[] = { /* global power events */
1589         __P4MASK(running, 0),
1590         NULLMASK
1591 };
1592
1593 static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */
1594         __P4MASK(cisc, 0),
1595         NULLMASK
1596 };
1597
1598 static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */
1599         __P4MASK(from-tc-build, 0),
1600         __P4MASK(from-tc-deliver, 1),
1601         __P4MASK(from-rom, 2),
1602         NULLMASK
1603 };
1604
1605 static const struct pmc_masks p4_mask_rmbt[] = {
1606         /* retired mispred branch type */
1607         __P4MASK(conditional, 1),
1608         __P4MASK(call, 2),
1609         __P4MASK(return, 3),
1610         __P4MASK(indirect, 4),
1611         NULLMASK
1612 };
1613
1614 static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */
1615         __P4MASK(conditional, 1),
1616         __P4MASK(call, 2),
1617         __P4MASK(retired, 3),
1618         __P4MASK(indirect, 4),
1619         NULLMASK
1620 };
1621
1622 static const struct pmc_masks p4_mask_rs[] = { /* resource stall */
1623         __P4MASK(sbfull, 5),
1624         NULLMASK
1625 };
1626
1627 static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */
1628         __P4MASK(wcb-evicts, 0),
1629         __P4MASK(wcb-full-evict, 1),
1630         NULLMASK
1631 };
1632
1633 static const struct pmc_masks p4_mask_fee[] = { /* front end event */
1634         __P4MASK(nbogus, 0),
1635         __P4MASK(bogus, 1),
1636         NULLMASK
1637 };
1638
1639 static const struct pmc_masks p4_mask_ee[] = { /* execution event */
1640         __P4MASK(nbogus0, 0),
1641         __P4MASK(nbogus1, 1),
1642         __P4MASK(nbogus2, 2),
1643         __P4MASK(nbogus3, 3),
1644         __P4MASK(bogus0, 4),
1645         __P4MASK(bogus1, 5),
1646         __P4MASK(bogus2, 6),
1647         __P4MASK(bogus3, 7),
1648         NULLMASK
1649 };
1650
1651 static const struct pmc_masks p4_mask_re[] = { /* replay event */
1652         __P4MASK(nbogus, 0),
1653         __P4MASK(bogus, 1),
1654         NULLMASK
1655 };
1656
1657 static const struct pmc_masks p4_mask_insret[] = { /* instr retired */
1658         __P4MASK(nbogusntag, 0),
1659         __P4MASK(nbogustag, 1),
1660         __P4MASK(bogusntag, 2),
1661         __P4MASK(bogustag, 3),
1662         NULLMASK
1663 };
1664
1665 static const struct pmc_masks p4_mask_ur[] = { /* uops retired */
1666         __P4MASK(nbogus, 0),
1667         __P4MASK(bogus, 1),
1668         NULLMASK
1669 };
1670
1671 static const struct pmc_masks p4_mask_ut[] = { /* uop type */
1672         __P4MASK(tagloads, 1),
1673         __P4MASK(tagstores, 2),
1674         NULLMASK
1675 };
1676
1677 static const struct pmc_masks p4_mask_br[] = { /* branch retired */
1678         __P4MASK(mmnp, 0),
1679         __P4MASK(mmnm, 1),
1680         __P4MASK(mmtp, 2),
1681         __P4MASK(mmtm, 3),
1682         NULLMASK
1683 };
1684
1685 static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */
1686         __P4MASK(nbogus, 0),
1687         NULLMASK
1688 };
1689
1690 static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */
1691         __P4MASK(fpsu, 0),
1692         __P4MASK(fpso, 1),
1693         __P4MASK(poao, 2),
1694         __P4MASK(poau, 3),
1695         __P4MASK(prea, 4),
1696         NULLMASK
1697 };
1698
1699 static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */
1700         __P4MASK(clear, 0),
1701         __P4MASK(moclear, 2),
1702         __P4MASK(smclear, 3),
1703         NULLMASK
1704 };
1705
1706 /* P4 event parser */
1707 static int
1708 p4_allocate_pmc(enum pmc_event pe, char *ctrspec,
1709     struct pmc_op_pmcallocate *pmc_config)
1710 {
1711
1712         char    *e, *p, *q;
1713         int     count, has_tag, has_busreqtype, n;
1714         uint32_t cccractivemask;
1715         uint64_t evmask;
1716         const struct pmc_masks *pm, *pmask;
1717
1718         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1719         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig =
1720             pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0;
1721
1722         pmask   = NULL;
1723         evmask  = 0;
1724         cccractivemask = 0x3;
1725         has_tag = has_busreqtype = 0;
1726
1727 #define __P4SETMASK(M) do {                             \
1728         pmask = p4_mask_##M;                            \
1729 } while (0)
1730
1731         switch (pe) {
1732         case PMC_EV_P4_TC_DELIVER_MODE:
1733                 __P4SETMASK(tcdm);
1734                 break;
1735         case PMC_EV_P4_BPU_FETCH_REQUEST:
1736                 __P4SETMASK(bfr);
1737                 break;
1738         case PMC_EV_P4_ITLB_REFERENCE:
1739                 __P4SETMASK(ir);
1740                 break;
1741         case PMC_EV_P4_MEMORY_CANCEL:
1742                 __P4SETMASK(memcan);
1743                 break;
1744         case PMC_EV_P4_MEMORY_COMPLETE:
1745                 __P4SETMASK(memcomp);
1746                 break;
1747         case PMC_EV_P4_LOAD_PORT_REPLAY:
1748                 __P4SETMASK(lpr);
1749                 break;
1750         case PMC_EV_P4_STORE_PORT_REPLAY:
1751                 __P4SETMASK(spr);
1752                 break;
1753         case PMC_EV_P4_MOB_LOAD_REPLAY:
1754                 __P4SETMASK(mlr);
1755                 break;
1756         case PMC_EV_P4_PAGE_WALK_TYPE:
1757                 __P4SETMASK(pwt);
1758                 break;
1759         case PMC_EV_P4_BSQ_CACHE_REFERENCE:
1760                 __P4SETMASK(bcr);
1761                 break;
1762         case PMC_EV_P4_IOQ_ALLOCATION:
1763                 __P4SETMASK(ia);
1764                 has_busreqtype = 1;
1765                 break;
1766         case PMC_EV_P4_IOQ_ACTIVE_ENTRIES:
1767                 __P4SETMASK(iae);
1768                 has_busreqtype = 1;
1769                 break;
1770         case PMC_EV_P4_FSB_DATA_ACTIVITY:
1771                 __P4SETMASK(fda);
1772                 break;
1773         case PMC_EV_P4_BSQ_ALLOCATION:
1774                 __P4SETMASK(ba);
1775                 break;
1776         case PMC_EV_P4_SSE_INPUT_ASSIST:
1777                 __P4SETMASK(sia);
1778                 break;
1779         case PMC_EV_P4_PACKED_SP_UOP:
1780                 __P4SETMASK(psu);
1781                 break;
1782         case PMC_EV_P4_PACKED_DP_UOP:
1783                 __P4SETMASK(pdu);
1784                 break;
1785         case PMC_EV_P4_SCALAR_SP_UOP:
1786                 __P4SETMASK(ssu);
1787                 break;
1788         case PMC_EV_P4_SCALAR_DP_UOP:
1789                 __P4SETMASK(sdu);
1790                 break;
1791         case PMC_EV_P4_64BIT_MMX_UOP:
1792                 __P4SETMASK(64bmu);
1793                 break;
1794         case PMC_EV_P4_128BIT_MMX_UOP:
1795                 __P4SETMASK(128bmu);
1796                 break;
1797         case PMC_EV_P4_X87_FP_UOP:
1798                 __P4SETMASK(xfu);
1799                 break;
1800         case PMC_EV_P4_X87_SIMD_MOVES_UOP:
1801                 __P4SETMASK(xsmu);
1802                 break;
1803         case PMC_EV_P4_GLOBAL_POWER_EVENTS:
1804                 __P4SETMASK(gpe);
1805                 break;
1806         case PMC_EV_P4_TC_MS_XFER:
1807                 __P4SETMASK(tmx);
1808                 break;
1809         case PMC_EV_P4_UOP_QUEUE_WRITES:
1810                 __P4SETMASK(uqw);
1811                 break;
1812         case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE:
1813                 __P4SETMASK(rmbt);
1814                 break;
1815         case PMC_EV_P4_RETIRED_BRANCH_TYPE:
1816                 __P4SETMASK(rbt);
1817                 break;
1818         case PMC_EV_P4_RESOURCE_STALL:
1819                 __P4SETMASK(rs);
1820                 break;
1821         case PMC_EV_P4_WC_BUFFER:
1822                 __P4SETMASK(wb);
1823                 break;
1824         case PMC_EV_P4_BSQ_ACTIVE_ENTRIES:
1825         case PMC_EV_P4_B2B_CYCLES:
1826         case PMC_EV_P4_BNR:
1827         case PMC_EV_P4_SNOOP:
1828         case PMC_EV_P4_RESPONSE:
1829                 break;
1830         case PMC_EV_P4_FRONT_END_EVENT:
1831                 __P4SETMASK(fee);
1832                 break;
1833         case PMC_EV_P4_EXECUTION_EVENT:
1834                 __P4SETMASK(ee);
1835                 break;
1836         case PMC_EV_P4_REPLAY_EVENT:
1837                 __P4SETMASK(re);
1838                 break;
1839         case PMC_EV_P4_INSTR_RETIRED:
1840                 __P4SETMASK(insret);
1841                 break;
1842         case PMC_EV_P4_UOPS_RETIRED:
1843                 __P4SETMASK(ur);
1844                 break;
1845         case PMC_EV_P4_UOP_TYPE:
1846                 __P4SETMASK(ut);
1847                 break;
1848         case PMC_EV_P4_BRANCH_RETIRED:
1849                 __P4SETMASK(br);
1850                 break;
1851         case PMC_EV_P4_MISPRED_BRANCH_RETIRED:
1852                 __P4SETMASK(mbr);
1853                 break;
1854         case PMC_EV_P4_X87_ASSIST:
1855                 __P4SETMASK(xa);
1856                 break;
1857         case PMC_EV_P4_MACHINE_CLEAR:
1858                 __P4SETMASK(machclr);
1859                 break;
1860         default:
1861                 return (-1);
1862         }
1863
1864         /* process additional flags */
1865         while ((p = strsep(&ctrspec, ",")) != NULL) {
1866                 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) {
1867                         q = strchr(p, '=');
1868                         if (*++q == '\0') /* skip '=' */
1869                                 return (-1);
1870
1871                         if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0)
1872                                 cccractivemask = 0x0;
1873                         else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0)
1874                                 cccractivemask = 0x1;
1875                         else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0)
1876                                 cccractivemask = 0x2;
1877                         else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0)
1878                                 cccractivemask = 0x3;
1879                         else
1880                                 return (-1);
1881
1882                 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) {
1883                         if (has_busreqtype == 0)
1884                                 return (-1);
1885
1886                         q = strchr(p, '=');
1887                         if (*++q == '\0') /* skip '=' */
1888                                 return (-1);
1889
1890                         count = strtol(q, &e, 0);
1891                         if (e == q || *e != '\0')
1892                                 return (-1);
1893                         evmask = (evmask & ~0x1F) | (count & 0x1F);
1894                 } else if (KWMATCH(p, P4_KW_CASCADE))
1895                         pmc_config->pm_caps |= PMC_CAP_CASCADE;
1896                 else if (KWMATCH(p, P4_KW_EDGE))
1897                         pmc_config->pm_caps |= PMC_CAP_EDGE;
1898                 else if (KWMATCH(p, P4_KW_INV))
1899                         pmc_config->pm_caps |= PMC_CAP_INVERT;
1900                 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) {
1901                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1902                                 return (-1);
1903                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1904                 } else if (KWMATCH(p, P4_KW_OS))
1905                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1906                 else if (KWMATCH(p, P4_KW_PRECISE))
1907                         pmc_config->pm_caps |= PMC_CAP_PRECISE;
1908                 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) {
1909                         if (has_tag == 0)
1910                                 return (-1);
1911
1912                         q = strchr(p, '=');
1913                         if (*++q == '\0') /* skip '=' */
1914                                 return (-1);
1915
1916                         count = strtol(q, &e, 0);
1917                         if (e == q || *e != '\0')
1918                                 return (-1);
1919
1920                         pmc_config->pm_caps |= PMC_CAP_TAGGING;
1921                         pmc_config->pm_md.pm_p4.pm_p4_escrconfig |=
1922                             P4_ESCR_TO_TAG_VALUE(count);
1923                 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) {
1924                         q = strchr(p, '=');
1925                         if (*++q == '\0') /* skip '=' */
1926                                 return (-1);
1927
1928                         count = strtol(q, &e, 0);
1929                         if (e == q || *e != '\0')
1930                                 return (-1);
1931
1932                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1933                         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &=
1934                             ~P4_CCCR_THRESHOLD_MASK;
1935                         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1936                             P4_CCCR_TO_THRESHOLD(count);
1937                 } else if (KWMATCH(p, P4_KW_USR))
1938                         pmc_config->pm_caps |= PMC_CAP_USER;
1939                 else
1940                         return (-1);
1941         }
1942
1943         /* other post processing */
1944         if (pe == PMC_EV_P4_IOQ_ALLOCATION ||
1945             pe == PMC_EV_P4_FSB_DATA_ACTIVITY ||
1946             pe == PMC_EV_P4_BSQ_ALLOCATION)
1947                 pmc_config->pm_caps |= PMC_CAP_EDGE;
1948
1949         /* fill in thread activity mask */
1950         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1951             P4_CCCR_TO_ACTIVE_THREAD(cccractivemask);
1952
1953         if (evmask)
1954                 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1955
1956         switch (pe) {
1957         case PMC_EV_P4_FSB_DATA_ACTIVITY:
1958                 if ((evmask & 0x06) == 0x06 ||
1959                     (evmask & 0x18) == 0x18)
1960                         return (-1); /* can't have own+other bits together */
1961                 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */
1962                         evmask = 0x1D;
1963                 break;
1964         case PMC_EV_P4_MACHINE_CLEAR:
1965                 /* only one bit is allowed to be set */
1966                 if ((evmask & (evmask - 1)) != 0)
1967                         return (-1);
1968                 if (evmask == 0) {
1969                         evmask = 0x1;   /* 'CLEAR' */
1970                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1971                 }
1972                 break;
1973         default:
1974                 if (evmask == 0 && pmask) {
1975                         for (pm = pmask; pm->pm_name; pm++)
1976                                 evmask |= pm->pm_value;
1977                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1978                 }
1979         }
1980
1981         pmc_config->pm_md.pm_p4.pm_p4_escrconfig =
1982             P4_ESCR_TO_EVENT_MASK(evmask);
1983
1984         return (0);
1985 }
1986
1987 #endif
1988
1989 #if defined(__i386__)
1990
1991 /*
1992  * Pentium style PMCs
1993  */
1994
1995 static struct pmc_event_alias p5_aliases[] = {
1996         EV_ALIAS("branches",            "p5-taken-branches"),
1997         EV_ALIAS("cycles",              "tsc"),
1998         EV_ALIAS("dc-misses",           "p5-data-read-miss-or-write-miss"),
1999         EV_ALIAS("ic-misses",           "p5-code-cache-miss"),
2000         EV_ALIAS("instructions",        "p5-instructions-executed"),
2001         EV_ALIAS("interrupts",          "p5-hardware-interrupts"),
2002         EV_ALIAS("unhalted-cycles",
2003             "p5-number-of-cycles-not-in-halt-state"),
2004         EV_ALIAS(NULL, NULL)
2005 };
2006
2007 static int
2008 p5_allocate_pmc(enum pmc_event pe, char *ctrspec,
2009     struct pmc_op_pmcallocate *pmc_config)
2010 {
2011         return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */
2012 }
2013
2014 /*
2015  * Pentium Pro style PMCs.  These PMCs are found in Pentium II, Pentium III,
2016  * and Pentium M CPUs.
2017  */
2018
2019 static struct pmc_event_alias p6_aliases[] = {
2020         EV_ALIAS("branches",            "p6-br-inst-retired"),
2021         EV_ALIAS("branch-mispredicts",  "p6-br-miss-pred-retired"),
2022         EV_ALIAS("cycles",              "tsc"),
2023         EV_ALIAS("dc-misses",           "p6-dcu-lines-in"),
2024         EV_ALIAS("ic-misses",           "p6-ifu-fetch-miss"),
2025         EV_ALIAS("instructions",        "p6-inst-retired"),
2026         EV_ALIAS("interrupts",          "p6-hw-int-rx"),
2027         EV_ALIAS("unhalted-cycles",     "p6-cpu-clk-unhalted"),
2028         EV_ALIAS(NULL, NULL)
2029 };
2030
2031 #define P6_KW_CMASK     "cmask"
2032 #define P6_KW_EDGE      "edge"
2033 #define P6_KW_INV       "inv"
2034 #define P6_KW_OS        "os"
2035 #define P6_KW_UMASK     "umask"
2036 #define P6_KW_USR       "usr"
2037
2038 static struct pmc_masks p6_mask_mesi[] = {
2039         PMCMASK(m,      0x01),
2040         PMCMASK(e,      0x02),
2041         PMCMASK(s,      0x04),
2042         PMCMASK(i,      0x08),
2043         NULLMASK
2044 };
2045
2046 static struct pmc_masks p6_mask_mesihw[] = {
2047         PMCMASK(m,      0x01),
2048         PMCMASK(e,      0x02),
2049         PMCMASK(s,      0x04),
2050         PMCMASK(i,      0x08),
2051         PMCMASK(nonhw,  0x00),
2052         PMCMASK(hw,     0x10),
2053         PMCMASK(both,   0x30),
2054         NULLMASK
2055 };
2056
2057 static struct pmc_masks p6_mask_hw[] = {
2058         PMCMASK(nonhw,  0x00),
2059         PMCMASK(hw,     0x10),
2060         PMCMASK(both,   0x30),
2061         NULLMASK
2062 };
2063
2064 static struct pmc_masks p6_mask_any[] = {
2065         PMCMASK(self,   0x00),
2066         PMCMASK(any,    0x20),
2067         NULLMASK
2068 };
2069
2070 static struct pmc_masks p6_mask_ekp[] = {
2071         PMCMASK(nta,    0x00),
2072         PMCMASK(t1,     0x01),
2073         PMCMASK(t2,     0x02),
2074         PMCMASK(wos,    0x03),
2075         NULLMASK
2076 };
2077
2078 static struct pmc_masks p6_mask_pps[] = {
2079         PMCMASK(packed-and-scalar, 0x00),
2080         PMCMASK(scalar, 0x01),
2081         NULLMASK
2082 };
2083
2084 static struct pmc_masks p6_mask_mite[] = {
2085         PMCMASK(packed-multiply,         0x01),
2086         PMCMASK(packed-shift,           0x02),
2087         PMCMASK(pack,                   0x04),
2088         PMCMASK(unpack,                 0x08),
2089         PMCMASK(packed-logical,         0x10),
2090         PMCMASK(packed-arithmetic,      0x20),
2091         NULLMASK
2092 };
2093
2094 static struct pmc_masks p6_mask_fmt[] = {
2095         PMCMASK(mmxtofp,        0x00),
2096         PMCMASK(fptommx,        0x01),
2097         NULLMASK
2098 };
2099
2100 static struct pmc_masks p6_mask_sr[] = {
2101         PMCMASK(es,     0x01),
2102         PMCMASK(ds,     0x02),
2103         PMCMASK(fs,     0x04),
2104         PMCMASK(gs,     0x08),
2105         NULLMASK
2106 };
2107
2108 static struct pmc_masks p6_mask_eet[] = {
2109         PMCMASK(all,    0x00),
2110         PMCMASK(freq,   0x02),
2111         NULLMASK
2112 };
2113
2114 static struct pmc_masks p6_mask_efur[] = {
2115         PMCMASK(all,    0x00),
2116         PMCMASK(loadop, 0x01),
2117         PMCMASK(stdsta, 0x02),
2118         NULLMASK
2119 };
2120
2121 static struct pmc_masks p6_mask_essir[] = {
2122         PMCMASK(sse-packed-single,      0x00),
2123         PMCMASK(sse-packed-single-scalar-single, 0x01),
2124         PMCMASK(sse2-packed-double,     0x02),
2125         PMCMASK(sse2-scalar-double,     0x03),
2126         NULLMASK
2127 };
2128
2129 static struct pmc_masks p6_mask_esscir[] = {
2130         PMCMASK(sse-packed-single,      0x00),
2131         PMCMASK(sse-scalar-single,      0x01),
2132         PMCMASK(sse2-packed-double,     0x02),
2133         PMCMASK(sse2-scalar-double,     0x03),
2134         NULLMASK
2135 };
2136
2137 /* P6 event parser */
2138 static int
2139 p6_allocate_pmc(enum pmc_event pe, char *ctrspec,
2140     struct pmc_op_pmcallocate *pmc_config)
2141 {
2142         char *e, *p, *q;
2143         uint64_t evmask;
2144         int count, n;
2145         const struct pmc_masks *pm, *pmask;
2146
2147         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2148         pmc_config->pm_md.pm_ppro.pm_ppro_config = 0;
2149
2150         evmask = 0;
2151
2152 #define P6MASKSET(M)    pmask = p6_mask_ ## M
2153
2154         switch(pe) {
2155         case PMC_EV_P6_L2_IFETCH:       P6MASKSET(mesi); break;
2156         case PMC_EV_P6_L2_LD:           P6MASKSET(mesi); break;
2157         case PMC_EV_P6_L2_ST:           P6MASKSET(mesi); break;
2158         case PMC_EV_P6_L2_RQSTS:        P6MASKSET(mesi); break;
2159         case PMC_EV_P6_BUS_DRDY_CLOCKS:
2160         case PMC_EV_P6_BUS_LOCK_CLOCKS:
2161         case PMC_EV_P6_BUS_TRAN_BRD:
2162         case PMC_EV_P6_BUS_TRAN_RFO:
2163         case PMC_EV_P6_BUS_TRANS_WB:
2164         case PMC_EV_P6_BUS_TRAN_IFETCH:
2165         case PMC_EV_P6_BUS_TRAN_INVAL:
2166         case PMC_EV_P6_BUS_TRAN_PWR:
2167         case PMC_EV_P6_BUS_TRANS_P:
2168         case PMC_EV_P6_BUS_TRANS_IO:
2169         case PMC_EV_P6_BUS_TRAN_DEF:
2170         case PMC_EV_P6_BUS_TRAN_BURST:
2171         case PMC_EV_P6_BUS_TRAN_ANY:
2172         case PMC_EV_P6_BUS_TRAN_MEM:
2173                 P6MASKSET(any); break;
2174         case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED:
2175         case PMC_EV_P6_EMON_KNI_PREF_MISS:
2176                 P6MASKSET(ekp); break;
2177         case PMC_EV_P6_EMON_KNI_INST_RETIRED:
2178         case PMC_EV_P6_EMON_KNI_COMP_INST_RET:
2179                 P6MASKSET(pps); break;
2180         case PMC_EV_P6_MMX_INSTR_TYPE_EXEC:
2181                 P6MASKSET(mite); break;
2182         case PMC_EV_P6_FP_MMX_TRANS:
2183                 P6MASKSET(fmt); break;
2184         case PMC_EV_P6_SEG_RENAME_STALLS:
2185         case PMC_EV_P6_SEG_REG_RENAMES:
2186                 P6MASKSET(sr);  break;
2187         case PMC_EV_P6_EMON_EST_TRANS:
2188                 P6MASKSET(eet); break;
2189         case PMC_EV_P6_EMON_FUSED_UOPS_RET:
2190                 P6MASKSET(efur); break;
2191         case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED:
2192                 P6MASKSET(essir); break;
2193         case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED:
2194                 P6MASKSET(esscir); break;
2195         default:
2196                 pmask = NULL;
2197                 break;
2198         }
2199
2200         /* Pentium M PMCs have a few events with different semantics */
2201         if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) {
2202                 if (pe == PMC_EV_P6_L2_LD ||
2203                     pe == PMC_EV_P6_L2_LINES_IN ||
2204                     pe == PMC_EV_P6_L2_LINES_OUT)
2205                         P6MASKSET(mesihw);
2206                 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM)
2207                         P6MASKSET(hw);
2208         }
2209
2210         /* Parse additional modifiers if present */
2211         while ((p = strsep(&ctrspec, ",")) != NULL) {
2212                 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) {
2213                         q = strchr(p, '=');
2214                         if (*++q == '\0') /* skip '=' */
2215                                 return (-1);
2216                         count = strtol(q, &e, 0);
2217                         if (e == q || *e != '\0')
2218                                 return (-1);
2219                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
2220                         pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2221                             P6_EVSEL_TO_CMASK(count);
2222                 } else if (KWMATCH(p, P6_KW_EDGE)) {
2223                         pmc_config->pm_caps |= PMC_CAP_EDGE;
2224                 } else if (KWMATCH(p, P6_KW_INV)) {
2225                         pmc_config->pm_caps |= PMC_CAP_INVERT;
2226                 } else if (KWMATCH(p, P6_KW_OS)) {
2227                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2228                 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) {
2229                         evmask = 0;
2230                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
2231                                 return (-1);
2232                         if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS ||
2233                              pe == PMC_EV_P6_BUS_LOCK_CLOCKS ||
2234                              pe == PMC_EV_P6_BUS_TRAN_BRD ||
2235                              pe == PMC_EV_P6_BUS_TRAN_RFO ||
2236                              pe == PMC_EV_P6_BUS_TRAN_IFETCH ||
2237                              pe == PMC_EV_P6_BUS_TRAN_INVAL ||
2238                              pe == PMC_EV_P6_BUS_TRAN_PWR ||
2239                              pe == PMC_EV_P6_BUS_TRAN_DEF ||
2240                              pe == PMC_EV_P6_BUS_TRAN_BURST ||
2241                              pe == PMC_EV_P6_BUS_TRAN_ANY ||
2242                              pe == PMC_EV_P6_BUS_TRAN_MEM ||
2243                              pe == PMC_EV_P6_BUS_TRANS_IO ||
2244                              pe == PMC_EV_P6_BUS_TRANS_P ||
2245                              pe == PMC_EV_P6_BUS_TRANS_WB ||
2246                              pe == PMC_EV_P6_EMON_EST_TRANS ||
2247                              pe == PMC_EV_P6_EMON_FUSED_UOPS_RET ||
2248                              pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET ||
2249                              pe == PMC_EV_P6_EMON_KNI_INST_RETIRED ||
2250                              pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED ||
2251                              pe == PMC_EV_P6_EMON_KNI_PREF_MISS ||
2252                              pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED ||
2253                              pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED ||
2254                              pe == PMC_EV_P6_FP_MMX_TRANS)
2255                             && (n > 1)) /* Only one mask keyword is allowed. */
2256                                 return (-1);
2257                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2258                 } else if (KWMATCH(p, P6_KW_USR)) {
2259                         pmc_config->pm_caps |= PMC_CAP_USER;
2260                 } else
2261                         return (-1);
2262         }
2263
2264         /* post processing */
2265         switch (pe) {
2266
2267                 /*
2268                  * The following events default to an evmask of 0
2269                  */
2270
2271                 /* default => 'self' */
2272         case PMC_EV_P6_BUS_DRDY_CLOCKS:
2273         case PMC_EV_P6_BUS_LOCK_CLOCKS:
2274         case PMC_EV_P6_BUS_TRAN_BRD:
2275         case PMC_EV_P6_BUS_TRAN_RFO:
2276         case PMC_EV_P6_BUS_TRANS_WB:
2277         case PMC_EV_P6_BUS_TRAN_IFETCH:
2278         case PMC_EV_P6_BUS_TRAN_INVAL:
2279         case PMC_EV_P6_BUS_TRAN_PWR:
2280         case PMC_EV_P6_BUS_TRANS_P:
2281         case PMC_EV_P6_BUS_TRANS_IO:
2282         case PMC_EV_P6_BUS_TRAN_DEF:
2283         case PMC_EV_P6_BUS_TRAN_BURST:
2284         case PMC_EV_P6_BUS_TRAN_ANY:
2285         case PMC_EV_P6_BUS_TRAN_MEM:
2286
2287                 /* default => 'nta' */
2288         case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED:
2289         case PMC_EV_P6_EMON_KNI_PREF_MISS:
2290
2291                 /* default => 'packed and scalar' */
2292         case PMC_EV_P6_EMON_KNI_INST_RETIRED:
2293         case PMC_EV_P6_EMON_KNI_COMP_INST_RET:
2294
2295                 /* default => 'mmx to fp transitions' */
2296         case PMC_EV_P6_FP_MMX_TRANS:
2297
2298                 /* default => 'SSE Packed Single' */
2299         case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED:
2300         case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED:
2301
2302                 /* default => 'all fused micro-ops' */
2303         case PMC_EV_P6_EMON_FUSED_UOPS_RET:
2304
2305                 /* default => 'all transitions' */
2306         case PMC_EV_P6_EMON_EST_TRANS:
2307                 break;
2308
2309         case PMC_EV_P6_MMX_UOPS_EXEC:
2310                 evmask = 0x0F;          /* only value allowed */
2311                 break;
2312
2313         default:
2314                 /*
2315                  * For all other events, set the default event mask
2316                  * to a logical OR of all the allowed event mask bits.
2317                  */
2318                 if (evmask == 0 && pmask) {
2319                         for (pm = pmask; pm->pm_name; pm++)
2320                                 evmask |= pm->pm_value;
2321                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2322                 }
2323
2324                 break;
2325         }
2326
2327         if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
2328                 pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2329                     P6_EVSEL_TO_UMASK(evmask);
2330
2331         return (0);
2332 }
2333
2334 #endif
2335
2336 #if     defined(__i386__) || defined(__amd64__)
2337 static int
2338 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec,
2339     struct pmc_op_pmcallocate *pmc_config)
2340 {
2341         if (pe != PMC_EV_TSC_TSC)
2342                 return (-1);
2343
2344         /* TSC events must be unqualified. */
2345         if (ctrspec && *ctrspec != '\0')
2346                 return (-1);
2347
2348         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
2349         pmc_config->pm_caps |= PMC_CAP_READ;
2350
2351         return (0);
2352 }
2353 #endif
2354
2355 static struct pmc_event_alias generic_aliases[] = {
2356         EV_ALIAS("instructions",                "SOFT-CLOCK.HARD"),
2357         EV_ALIAS(NULL, NULL)
2358 };
2359
2360 static int
2361 soft_allocate_pmc(enum pmc_event pe, char *ctrspec,
2362     struct pmc_op_pmcallocate *pmc_config)
2363 {
2364         (void)ctrspec;
2365         (void)pmc_config;
2366
2367         if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST)
2368                 return (-1);
2369
2370         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2371         return (0);
2372 }
2373
2374 #if     defined(__XSCALE__)
2375
2376 static struct pmc_event_alias xscale_aliases[] = {
2377         EV_ALIAS("branches",            "BRANCH_RETIRED"),
2378         EV_ALIAS("branch-mispredicts",  "BRANCH_MISPRED"),
2379         EV_ALIAS("dc-misses",           "DC_MISS"),
2380         EV_ALIAS("ic-misses",           "IC_MISS"),
2381         EV_ALIAS("instructions",        "INSTR_RETIRED"),
2382         EV_ALIAS(NULL, NULL)
2383 };
2384 static int
2385 xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2386     struct pmc_op_pmcallocate *pmc_config __unused)
2387 {
2388         switch (pe) {
2389         default:
2390                 break;
2391         }
2392
2393         return (0);
2394 }
2395 #endif
2396
2397 #if defined(__mips__)
2398
2399 static struct pmc_event_alias mips24k_aliases[] = {
2400         EV_ALIAS("instructions",        "INSTR_EXECUTED"),
2401         EV_ALIAS("branches",            "BRANCH_COMPLETED"),
2402         EV_ALIAS("branch-mispredicts",  "BRANCH_MISPRED"),
2403         EV_ALIAS(NULL, NULL)
2404 };
2405
2406 static struct pmc_event_alias octeon_aliases[] = {
2407         EV_ALIAS("instructions",        "RET"),
2408         EV_ALIAS("branches",            "BR"),
2409         EV_ALIAS("branch-mispredicts",  "BRMIS"),
2410         EV_ALIAS(NULL, NULL)
2411 };
2412
2413 #define MIPS_KW_OS              "os"
2414 #define MIPS_KW_USR             "usr"
2415 #define MIPS_KW_ANYTHREAD       "anythread"
2416
2417 static int
2418 mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2419                   struct pmc_op_pmcallocate *pmc_config __unused)
2420 {
2421         char *p;
2422
2423         (void) pe;
2424
2425         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2426
2427         while ((p = strsep(&ctrspec, ",")) != NULL) {
2428                 if (KWMATCH(p, MIPS_KW_OS))
2429                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2430                 else if (KWMATCH(p, MIPS_KW_USR))
2431                         pmc_config->pm_caps |= PMC_CAP_USER;
2432                 else if (KWMATCH(p, MIPS_KW_ANYTHREAD))
2433                         pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
2434                 else
2435                         return (-1);
2436         }
2437
2438         return (0);
2439 }
2440
2441 #endif /* __mips__ */
2442
2443 #if defined(__powerpc__)
2444
2445 static struct pmc_event_alias ppc7450_aliases[] = {
2446         EV_ALIAS("instructions",        "INSTR_COMPLETED"),
2447         EV_ALIAS("branches",            "BRANCHES_COMPLETED"),
2448         EV_ALIAS("branch-mispredicts",  "MISPREDICTED_BRANCHES"),
2449         EV_ALIAS(NULL, NULL)
2450 };
2451
2452 static struct pmc_event_alias ppc970_aliases[] = {
2453         EV_ALIAS("instructions", "INSTR_COMPLETED"),
2454         EV_ALIAS("cycles",       "CYCLES"),
2455         EV_ALIAS(NULL, NULL)
2456 };
2457
2458 #define POWERPC_KW_OS           "os"
2459 #define POWERPC_KW_USR          "usr"
2460 #define POWERPC_KW_ANYTHREAD    "anythread"
2461
2462 static int
2463 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2464                      struct pmc_op_pmcallocate *pmc_config __unused)
2465 {
2466         char *p;
2467
2468         (void) pe;
2469
2470         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2471
2472         while ((p = strsep(&ctrspec, ",")) != NULL) {
2473                 if (KWMATCH(p, POWERPC_KW_OS))
2474                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2475                 else if (KWMATCH(p, POWERPC_KW_USR))
2476                         pmc_config->pm_caps |= PMC_CAP_USER;
2477                 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD))
2478                         pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
2479                 else
2480                         return (-1);
2481         }
2482
2483         return (0);
2484 }
2485
2486 #endif /* __powerpc__ */
2487
2488
2489 /*
2490  * Match an event name `name' with its canonical form.
2491  *
2492  * Matches are case insensitive and spaces, periods, underscores and
2493  * hyphen characters are considered to match each other.
2494  *
2495  * Returns 1 for a match, 0 otherwise.
2496  */
2497
2498 static int
2499 pmc_match_event_name(const char *name, const char *canonicalname)
2500 {
2501         int cc, nc;
2502         const unsigned char *c, *n;
2503
2504         c = (const unsigned char *) canonicalname;
2505         n = (const unsigned char *) name;
2506
2507         for (; (nc = *n) && (cc = *c); n++, c++) {
2508
2509                 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') &&
2510                     (cc == ' ' || cc == '_' || cc == '-' || cc == '.'))
2511                         continue;
2512
2513                 if (toupper(nc) == toupper(cc))
2514                         continue;
2515
2516
2517                 return (0);
2518         }
2519
2520         if (*n == '\0' && *c == '\0')
2521                 return (1);
2522
2523         return (0);
2524 }
2525
2526 /*
2527  * Match an event name against all the event named supported by a
2528  * PMC class.
2529  *
2530  * Returns an event descriptor pointer on match or NULL otherwise.
2531  */
2532 static const struct pmc_event_descr *
2533 pmc_match_event_class(const char *name,
2534     const struct pmc_class_descr *pcd)
2535 {
2536         size_t n;
2537         const struct pmc_event_descr *ev;
2538
2539         ev = pcd->pm_evc_event_table;
2540         for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++)
2541                 if (pmc_match_event_name(name, ev->pm_ev_name))
2542                         return (ev);
2543
2544         return (NULL);
2545 }
2546
2547 static int
2548 pmc_mdep_is_compatible_class(enum pmc_class pc)
2549 {
2550         size_t n;
2551
2552         for (n = 0; n < pmc_mdep_class_list_size; n++)
2553                 if (pmc_mdep_class_list[n] == pc)
2554                         return (1);
2555         return (0);
2556 }
2557
2558 /*
2559  * API entry points
2560  */
2561
2562 int
2563 pmc_allocate(const char *ctrspec, enum pmc_mode mode,
2564     uint32_t flags, int cpu, pmc_id_t *pmcid)
2565 {
2566         size_t n;
2567         int retval;
2568         char *r, *spec_copy;
2569         const char *ctrname;
2570         const struct pmc_event_descr *ev;
2571         const struct pmc_event_alias *alias;
2572         struct pmc_op_pmcallocate pmc_config;
2573         const struct pmc_class_descr *pcd;
2574
2575         spec_copy = NULL;
2576         retval    = -1;
2577
2578         if (mode != PMC_MODE_SS && mode != PMC_MODE_TS &&
2579             mode != PMC_MODE_SC && mode != PMC_MODE_TC) {
2580                 errno = EINVAL;
2581                 goto out;
2582         }
2583
2584         /* replace an event alias with the canonical event specifier */
2585         if (pmc_mdep_event_aliases)
2586                 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++)
2587                         if (!strcasecmp(ctrspec, alias->pm_alias)) {
2588                                 spec_copy = strdup(alias->pm_spec);
2589                                 break;
2590                         }
2591
2592         if (spec_copy == NULL)
2593                 spec_copy = strdup(ctrspec);
2594
2595         r = spec_copy;
2596         ctrname = strsep(&r, ",");
2597
2598         /*
2599          * If a explicit class prefix was given by the user, restrict the
2600          * search for the event to the specified PMC class.
2601          */
2602         ev = NULL;
2603         for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) {
2604                 pcd = pmc_class_table[n];
2605                 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) &&
2606                     strncasecmp(ctrname, pcd->pm_evc_name,
2607                                 pcd->pm_evc_name_size) == 0) {
2608                         if ((ev = pmc_match_event_class(ctrname +
2609                             pcd->pm_evc_name_size, pcd)) == NULL) {
2610                                 errno = EINVAL;
2611                                 goto out;
2612                         }
2613                         break;
2614                 }
2615         }
2616
2617         /*
2618          * Otherwise, search for this event in all compatible PMC
2619          * classes.
2620          */
2621         for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) {
2622                 pcd = pmc_class_table[n];
2623                 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class))
2624                         ev = pmc_match_event_class(ctrname, pcd);
2625         }
2626
2627         if (ev == NULL) {
2628                 errno = EINVAL;
2629                 goto out;
2630         }
2631
2632         bzero(&pmc_config, sizeof(pmc_config));
2633         pmc_config.pm_ev    = ev->pm_ev_code;
2634         pmc_config.pm_class = pcd->pm_evc_class;
2635         pmc_config.pm_cpu   = cpu;
2636         pmc_config.pm_mode  = mode;
2637         pmc_config.pm_flags = flags;
2638
2639         if (PMC_IS_SAMPLING_MODE(mode))
2640                 pmc_config.pm_caps |= PMC_CAP_INTERRUPT;
2641
2642         if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) {
2643                 errno = EINVAL;
2644                 goto out;
2645         }
2646
2647         if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0)
2648                 goto out;
2649
2650         *pmcid = pmc_config.pm_pmcid;
2651
2652         retval = 0;
2653
2654  out:
2655         if (spec_copy)
2656                 free(spec_copy);
2657
2658         return (retval);
2659 }
2660
2661 int
2662 pmc_attach(pmc_id_t pmc, pid_t pid)
2663 {
2664         struct pmc_op_pmcattach pmc_attach_args;
2665
2666         pmc_attach_args.pm_pmc = pmc;
2667         pmc_attach_args.pm_pid = pid;
2668
2669         return (PMC_CALL(PMCATTACH, &pmc_attach_args));
2670 }
2671
2672 int
2673 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps)
2674 {
2675         unsigned int i;
2676         enum pmc_class cl;
2677
2678         cl = PMC_ID_TO_CLASS(pmcid);
2679         for (i = 0; i < cpu_info.pm_nclass; i++)
2680                 if (cpu_info.pm_classes[i].pm_class == cl) {
2681                         *caps = cpu_info.pm_classes[i].pm_caps;
2682                         return (0);
2683                 }
2684         errno = EINVAL;
2685         return (-1);
2686 }
2687
2688 int
2689 pmc_configure_logfile(int fd)
2690 {
2691         struct pmc_op_configurelog cla;
2692
2693         cla.pm_logfd = fd;
2694         if (PMC_CALL(CONFIGURELOG, &cla) < 0)
2695                 return (-1);
2696         return (0);
2697 }
2698
2699 int
2700 pmc_cpuinfo(const struct pmc_cpuinfo **pci)
2701 {
2702         if (pmc_syscall == -1) {
2703                 errno = ENXIO;
2704                 return (-1);
2705         }
2706
2707         *pci = &cpu_info;
2708         return (0);
2709 }
2710
2711 int
2712 pmc_detach(pmc_id_t pmc, pid_t pid)
2713 {
2714         struct pmc_op_pmcattach pmc_detach_args;
2715
2716         pmc_detach_args.pm_pmc = pmc;
2717         pmc_detach_args.pm_pid = pid;
2718         return (PMC_CALL(PMCDETACH, &pmc_detach_args));
2719 }
2720
2721 int
2722 pmc_disable(int cpu, int pmc)
2723 {
2724         struct pmc_op_pmcadmin ssa;
2725
2726         ssa.pm_cpu = cpu;
2727         ssa.pm_pmc = pmc;
2728         ssa.pm_state = PMC_STATE_DISABLED;
2729         return (PMC_CALL(PMCADMIN, &ssa));
2730 }
2731
2732 int
2733 pmc_enable(int cpu, int pmc)
2734 {
2735         struct pmc_op_pmcadmin ssa;
2736
2737         ssa.pm_cpu = cpu;
2738         ssa.pm_pmc = pmc;
2739         ssa.pm_state = PMC_STATE_FREE;
2740         return (PMC_CALL(PMCADMIN, &ssa));
2741 }
2742
2743 /*
2744  * Return a list of events known to a given PMC class.  'cl' is the
2745  * PMC class identifier, 'eventnames' is the returned list of 'const
2746  * char *' pointers pointing to the names of the events. 'nevents' is
2747  * the number of event name pointers returned.
2748  *
2749  * The space for 'eventnames' is allocated using malloc(3).  The caller
2750  * is responsible for freeing this space when done.
2751  */
2752 int
2753 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
2754     int *nevents)
2755 {
2756         int count;
2757         const char **names;
2758         const struct pmc_event_descr *ev;
2759
2760         switch (cl)
2761         {
2762         case PMC_CLASS_IAF:
2763                 ev = iaf_event_table;
2764                 count = PMC_EVENT_TABLE_SIZE(iaf);
2765                 break;
2766         case PMC_CLASS_IAP:
2767                 /*
2768                  * Return the most appropriate set of event name
2769                  * spellings for the current CPU.
2770                  */
2771                 switch (cpu_info.pm_cputype) {
2772                 default:
2773                 case PMC_CPU_INTEL_ATOM:
2774                         ev = atom_event_table;
2775                         count = PMC_EVENT_TABLE_SIZE(atom);
2776                         break;
2777                 case PMC_CPU_INTEL_ATOM_SILVERMONT:
2778                         ev = atom_silvermont_event_table;
2779                         count = PMC_EVENT_TABLE_SIZE(atom_silvermont);
2780                         break;
2781                 case PMC_CPU_INTEL_CORE:
2782                         ev = core_event_table;
2783                         count = PMC_EVENT_TABLE_SIZE(core);
2784                         break;
2785                 case PMC_CPU_INTEL_CORE2:
2786                 case PMC_CPU_INTEL_CORE2EXTREME:
2787                         ev = core2_event_table;
2788                         count = PMC_EVENT_TABLE_SIZE(core2);
2789                         break;
2790                 case PMC_CPU_INTEL_COREI7:
2791                         ev = corei7_event_table;
2792                         count = PMC_EVENT_TABLE_SIZE(corei7);
2793                         break;
2794                 case PMC_CPU_INTEL_NEHALEM_EX:
2795                         ev = nehalem_ex_event_table;
2796                         count = PMC_EVENT_TABLE_SIZE(nehalem_ex);
2797                         break;
2798                 case PMC_CPU_INTEL_HASWELL:
2799                         ev = haswell_event_table;
2800                         count = PMC_EVENT_TABLE_SIZE(haswell);
2801                         break;
2802                 case PMC_CPU_INTEL_HASWELL_XEON:
2803                         ev = haswell_xeon_event_table;
2804                         count = PMC_EVENT_TABLE_SIZE(haswell_xeon);
2805                         break;
2806                 case PMC_CPU_INTEL_IVYBRIDGE:
2807                         ev = ivybridge_event_table;
2808                         count = PMC_EVENT_TABLE_SIZE(ivybridge);
2809                         break;
2810                 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
2811                         ev = ivybridge_xeon_event_table;
2812                         count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon);
2813                         break;
2814                 case PMC_CPU_INTEL_SANDYBRIDGE:
2815                         ev = sandybridge_event_table;
2816                         count = PMC_EVENT_TABLE_SIZE(sandybridge);
2817                         break;
2818                 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
2819                         ev = sandybridge_xeon_event_table;
2820                         count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon);
2821                         break;
2822                 case PMC_CPU_INTEL_WESTMERE:
2823                         ev = westmere_event_table;
2824                         count = PMC_EVENT_TABLE_SIZE(westmere);
2825                         break;
2826                 case PMC_CPU_INTEL_WESTMERE_EX:
2827                         ev = westmere_ex_event_table;
2828                         count = PMC_EVENT_TABLE_SIZE(westmere_ex);
2829                         break;
2830                 }
2831                 break;
2832         case PMC_CLASS_UCF:
2833                 ev = ucf_event_table;
2834                 count = PMC_EVENT_TABLE_SIZE(ucf);
2835                 break;
2836         case PMC_CLASS_UCP:
2837                 /*
2838                  * Return the most appropriate set of event name
2839                  * spellings for the current CPU.
2840                  */
2841                 switch (cpu_info.pm_cputype) {
2842                 default:
2843                 case PMC_CPU_INTEL_COREI7:
2844                         ev = corei7uc_event_table;
2845                         count = PMC_EVENT_TABLE_SIZE(corei7uc);
2846                         break;
2847                 case PMC_CPU_INTEL_HASWELL:
2848                         ev = haswelluc_event_table;
2849                         count = PMC_EVENT_TABLE_SIZE(haswelluc);
2850                         break;
2851                 case PMC_CPU_INTEL_SANDYBRIDGE:
2852                         ev = sandybridgeuc_event_table;
2853                         count = PMC_EVENT_TABLE_SIZE(sandybridgeuc);
2854                         break;
2855                 case PMC_CPU_INTEL_WESTMERE:
2856                         ev = westmereuc_event_table;
2857                         count = PMC_EVENT_TABLE_SIZE(westmereuc);
2858                         break;
2859                 }
2860                 break;
2861         case PMC_CLASS_TSC:
2862                 ev = tsc_event_table;
2863                 count = PMC_EVENT_TABLE_SIZE(tsc);
2864                 break;
2865         case PMC_CLASS_K7:
2866                 ev = k7_event_table;
2867                 count = PMC_EVENT_TABLE_SIZE(k7);
2868                 break;
2869         case PMC_CLASS_K8:
2870                 ev = k8_event_table;
2871                 count = PMC_EVENT_TABLE_SIZE(k8);
2872                 break;
2873         case PMC_CLASS_P4:
2874                 ev = p4_event_table;
2875                 count = PMC_EVENT_TABLE_SIZE(p4);
2876                 break;
2877         case PMC_CLASS_P5:
2878                 ev = p5_event_table;
2879                 count = PMC_EVENT_TABLE_SIZE(p5);
2880                 break;
2881         case PMC_CLASS_P6:
2882                 ev = p6_event_table;
2883                 count = PMC_EVENT_TABLE_SIZE(p6);
2884                 break;
2885         case PMC_CLASS_XSCALE:
2886                 ev = xscale_event_table;
2887                 count = PMC_EVENT_TABLE_SIZE(xscale);
2888                 break;
2889         case PMC_CLASS_MIPS24K:
2890                 ev = mips24k_event_table;
2891                 count = PMC_EVENT_TABLE_SIZE(mips24k);
2892                 break;
2893         case PMC_CLASS_OCTEON:
2894                 ev = octeon_event_table;
2895                 count = PMC_EVENT_TABLE_SIZE(octeon);
2896                 break;
2897         case PMC_CLASS_PPC7450:
2898                 ev = ppc7450_event_table;
2899                 count = PMC_EVENT_TABLE_SIZE(ppc7450);
2900                 break;
2901         case PMC_CLASS_PPC970:
2902                 ev = ppc970_event_table;
2903                 count = PMC_EVENT_TABLE_SIZE(ppc970);
2904                 break;
2905         case PMC_CLASS_SOFT:
2906                 ev = soft_event_table;
2907                 count = soft_event_info.pm_nevent;
2908                 break;
2909         default:
2910                 errno = EINVAL;
2911                 return (-1);
2912         }
2913
2914         if ((names = malloc(count * sizeof(const char *))) == NULL)
2915                 return (-1);
2916
2917         *eventnames = names;
2918         *nevents = count;
2919
2920         for (;count--; ev++, names++)
2921                 *names = ev->pm_ev_name;
2922
2923         return (0);
2924 }
2925
2926 int
2927 pmc_flush_logfile(void)
2928 {
2929         return (PMC_CALL(FLUSHLOG,0));
2930 }
2931
2932 int
2933 pmc_close_logfile(void)
2934 {
2935         return (PMC_CALL(CLOSELOG,0));
2936 }
2937
2938 int
2939 pmc_get_driver_stats(struct pmc_driverstats *ds)
2940 {
2941         struct pmc_op_getdriverstats gms;
2942
2943         if (PMC_CALL(GETDRIVERSTATS, &gms) < 0)
2944                 return (-1);
2945
2946         /* copy out fields in the current userland<->library interface */
2947         ds->pm_intr_ignored    = gms.pm_intr_ignored;
2948         ds->pm_intr_processed  = gms.pm_intr_processed;
2949         ds->pm_intr_bufferfull = gms.pm_intr_bufferfull;
2950         ds->pm_syscalls        = gms.pm_syscalls;
2951         ds->pm_syscall_errors  = gms.pm_syscall_errors;
2952         ds->pm_buffer_requests = gms.pm_buffer_requests;
2953         ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed;
2954         ds->pm_log_sweeps      = gms.pm_log_sweeps;
2955         return (0);
2956 }
2957
2958 int
2959 pmc_get_msr(pmc_id_t pmc, uint32_t *msr)
2960 {
2961         struct pmc_op_getmsr gm;
2962
2963         gm.pm_pmcid = pmc;
2964         if (PMC_CALL(PMCGETMSR, &gm) < 0)
2965                 return (-1);
2966         *msr = gm.pm_msr;
2967         return (0);
2968 }
2969
2970 int
2971 pmc_init(void)
2972 {
2973         int error, pmc_mod_id;
2974         unsigned int n;
2975         uint32_t abi_version;
2976         struct module_stat pmc_modstat;
2977         struct pmc_op_getcpuinfo op_cpu_info;
2978 #if defined(__amd64__) || defined(__i386__)
2979         int cpu_has_iaf_counters;
2980         unsigned int t;
2981 #endif
2982
2983         if (pmc_syscall != -1) /* already inited */
2984                 return (0);
2985
2986         /* retrieve the system call number from the KLD */
2987         if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0)
2988                 return (-1);
2989
2990         pmc_modstat.version = sizeof(struct module_stat);
2991         if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0)
2992                 return (-1);
2993
2994         pmc_syscall = pmc_modstat.data.intval;
2995
2996         /* check the kernel module's ABI against our compiled-in version */
2997         abi_version = PMC_VERSION;
2998         if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0)
2999                 return (pmc_syscall = -1);
3000
3001         /* ignore patch & minor numbers for the comparision */
3002         if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) {
3003                 errno  = EPROGMISMATCH;
3004                 return (pmc_syscall = -1);
3005         }
3006
3007         if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0)
3008                 return (pmc_syscall = -1);
3009
3010         cpu_info.pm_cputype = op_cpu_info.pm_cputype;
3011         cpu_info.pm_ncpu    = op_cpu_info.pm_ncpu;
3012         cpu_info.pm_npmc    = op_cpu_info.pm_npmc;
3013         cpu_info.pm_nclass  = op_cpu_info.pm_nclass;
3014         for (n = 0; n < cpu_info.pm_nclass; n++)
3015                 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n];
3016
3017         pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE *
3018             sizeof(struct pmc_class_descr *));
3019
3020         if (pmc_class_table == NULL)
3021                 return (-1);
3022
3023         for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++)
3024                 pmc_class_table[n] = NULL;
3025
3026         /*
3027          * Get soft events list.
3028          */
3029         soft_event_info.pm_class = PMC_CLASS_SOFT;
3030         if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0)
3031                 return (pmc_syscall = -1);
3032
3033         /* Map soft events to static list. */
3034         for (n = 0; n < soft_event_info.pm_nevent; n++) {
3035                 soft_event_table[n].pm_ev_name =
3036                     soft_event_info.pm_events[n].pm_ev_name;
3037                 soft_event_table[n].pm_ev_code =
3038                     soft_event_info.pm_events[n].pm_ev_code;
3039         }
3040         soft_class_table_descr.pm_evc_event_table_size = \
3041             soft_event_info.pm_nevent;
3042         soft_class_table_descr.pm_evc_event_table = \
3043             soft_event_table;
3044
3045         /*
3046          * Fill in the class table.
3047          */
3048         n = 0;
3049
3050         /* Fill soft events information. */
3051         pmc_class_table[n++] = &soft_class_table_descr;
3052 #if defined(__amd64__) || defined(__i386__)
3053         if (cpu_info.pm_cputype != PMC_CPU_GENERIC)
3054                 pmc_class_table[n++] = &tsc_class_table_descr;
3055
3056         /*
3057          * Check if this CPU has fixed function counters.
3058          */
3059         cpu_has_iaf_counters = 0;
3060         for (t = 0; t < cpu_info.pm_nclass; t++)
3061                 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF &&
3062                     cpu_info.pm_classes[t].pm_num > 0)
3063                         cpu_has_iaf_counters = 1;
3064 #endif
3065
3066 #define PMC_MDEP_INIT(C) do {                                   \
3067                 pmc_mdep_event_aliases    = C##_aliases;        \
3068                 pmc_mdep_class_list  = C##_pmc_classes;         \
3069                 pmc_mdep_class_list_size =                      \
3070                     PMC_TABLE_SIZE(C##_pmc_classes);            \
3071         } while (0)
3072
3073 #define PMC_MDEP_INIT_INTEL_V2(C) do {                                  \
3074                 PMC_MDEP_INIT(C);                                       \
3075                 pmc_class_table[n++] = &iaf_class_table_descr;          \
3076                 if (!cpu_has_iaf_counters)                              \
3077                         pmc_mdep_event_aliases =                        \
3078                                 C##_aliases_without_iaf;                \
3079                 pmc_class_table[n] = &C##_class_table_descr;            \
3080         } while (0)
3081
3082         /* Configure the event name parser. */
3083         switch (cpu_info.pm_cputype) {
3084 #if defined(__i386__)
3085         case PMC_CPU_AMD_K7:
3086                 PMC_MDEP_INIT(k7);
3087                 pmc_class_table[n] = &k7_class_table_descr;
3088                 break;
3089         case PMC_CPU_INTEL_P5:
3090                 PMC_MDEP_INIT(p5);
3091                 pmc_class_table[n]  = &p5_class_table_descr;
3092                 break;
3093         case PMC_CPU_INTEL_P6:          /* P6 ... Pentium M CPUs have */
3094         case PMC_CPU_INTEL_PII:         /* similar PMCs. */
3095         case PMC_CPU_INTEL_PIII:
3096         case PMC_CPU_INTEL_PM:
3097                 PMC_MDEP_INIT(p6);
3098                 pmc_class_table[n] = &p6_class_table_descr;
3099                 break;
3100 #endif
3101 #if defined(__amd64__) || defined(__i386__)
3102         case PMC_CPU_AMD_K8:
3103                 PMC_MDEP_INIT(k8);
3104                 pmc_class_table[n] = &k8_class_table_descr;
3105                 break;
3106         case PMC_CPU_INTEL_ATOM:
3107                 PMC_MDEP_INIT_INTEL_V2(atom);
3108                 break;
3109         case PMC_CPU_INTEL_ATOM_SILVERMONT:
3110                 PMC_MDEP_INIT_INTEL_V2(atom_silvermont);
3111                 break;
3112         case PMC_CPU_INTEL_CORE:
3113                 PMC_MDEP_INIT(core);
3114                 pmc_class_table[n] = &core_class_table_descr;
3115                 break;
3116         case PMC_CPU_INTEL_CORE2:
3117         case PMC_CPU_INTEL_CORE2EXTREME:
3118                 PMC_MDEP_INIT_INTEL_V2(core2);
3119                 break;
3120         case PMC_CPU_INTEL_COREI7:
3121                 pmc_class_table[n++] = &ucf_class_table_descr;
3122                 pmc_class_table[n++] = &corei7uc_class_table_descr;
3123                 PMC_MDEP_INIT_INTEL_V2(corei7);
3124                 break;
3125         case PMC_CPU_INTEL_NEHALEM_EX:
3126                 PMC_MDEP_INIT_INTEL_V2(nehalem_ex);
3127                 break;
3128         case PMC_CPU_INTEL_HASWELL:
3129                 pmc_class_table[n++] = &ucf_class_table_descr;
3130                 pmc_class_table[n++] = &haswelluc_class_table_descr;
3131                 PMC_MDEP_INIT_INTEL_V2(haswell);
3132                 break;
3133         case PMC_CPU_INTEL_HASWELL_XEON:
3134                 PMC_MDEP_INIT_INTEL_V2(haswell_xeon);
3135                 break;
3136         case PMC_CPU_INTEL_IVYBRIDGE:
3137                 PMC_MDEP_INIT_INTEL_V2(ivybridge);
3138                 break;
3139         case PMC_CPU_INTEL_IVYBRIDGE_XEON:
3140                 PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon);
3141                 break;
3142         case PMC_CPU_INTEL_SANDYBRIDGE:
3143                 pmc_class_table[n++] = &ucf_class_table_descr;
3144                 pmc_class_table[n++] = &sandybridgeuc_class_table_descr;
3145                 PMC_MDEP_INIT_INTEL_V2(sandybridge);
3146                 break;
3147         case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
3148                 PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon);
3149                 break;
3150         case PMC_CPU_INTEL_WESTMERE:
3151                 pmc_class_table[n++] = &ucf_class_table_descr;
3152                 pmc_class_table[n++] = &westmereuc_class_table_descr;
3153                 PMC_MDEP_INIT_INTEL_V2(westmere);
3154                 break;
3155         case PMC_CPU_INTEL_WESTMERE_EX:
3156                 PMC_MDEP_INIT_INTEL_V2(westmere_ex);
3157                 break;
3158         case PMC_CPU_INTEL_PIV:
3159                 PMC_MDEP_INIT(p4);
3160                 pmc_class_table[n] = &p4_class_table_descr;
3161                 break;
3162 #endif
3163         case PMC_CPU_GENERIC:
3164                 PMC_MDEP_INIT(generic);
3165                 break;
3166 #if defined(__XSCALE__)
3167         case PMC_CPU_INTEL_XSCALE:
3168                 PMC_MDEP_INIT(xscale);
3169                 pmc_class_table[n] = &xscale_class_table_descr;
3170                 break;
3171 #endif
3172 #if defined(__mips__)
3173         case PMC_CPU_MIPS_24K:
3174                 PMC_MDEP_INIT(mips24k);
3175                 pmc_class_table[n] = &mips24k_class_table_descr;
3176                 break;
3177         case PMC_CPU_MIPS_OCTEON:
3178                 PMC_MDEP_INIT(octeon);
3179                 pmc_class_table[n] = &octeon_class_table_descr;
3180                 break;
3181 #endif /* __mips__ */
3182 #if defined(__powerpc__)
3183         case PMC_CPU_PPC_7450:
3184                 PMC_MDEP_INIT(ppc7450);
3185                 pmc_class_table[n] = &ppc7450_class_table_descr;
3186                 break;
3187         case PMC_CPU_PPC_970:
3188                 PMC_MDEP_INIT(ppc970);
3189                 pmc_class_table[n] = &ppc970_class_table_descr;
3190                 break;
3191 #endif
3192         default:
3193                 /*
3194                  * Some kind of CPU this version of the library knows nothing
3195                  * about.  This shouldn't happen since the abi version check
3196                  * should have caught this.
3197                  */
3198                 errno = ENXIO;
3199                 return (pmc_syscall = -1);
3200         }
3201
3202         return (0);
3203 }
3204
3205 const char *
3206 pmc_name_of_capability(enum pmc_caps cap)
3207 {
3208         int i;
3209
3210         /*
3211          * 'cap' should have a single bit set and should be in
3212          * range.
3213          */
3214         if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST ||
3215             cap > PMC_CAP_LAST) {
3216                 errno = EINVAL;
3217                 return (NULL);
3218         }
3219
3220         i = ffs(cap);
3221         return (pmc_capability_names[i - 1]);
3222 }
3223
3224 const char *
3225 pmc_name_of_class(enum pmc_class pc)
3226 {
3227         if ((int) pc >= PMC_CLASS_FIRST &&
3228             pc <= PMC_CLASS_LAST)
3229                 return (pmc_class_names[pc]);
3230
3231         errno = EINVAL;
3232         return (NULL);
3233 }
3234
3235 const char *
3236 pmc_name_of_cputype(enum pmc_cputype cp)
3237 {
3238         size_t n;
3239
3240         for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++)
3241                 if (cp == pmc_cputype_names[n].pm_cputype)
3242                         return (pmc_cputype_names[n].pm_name);
3243
3244         errno = EINVAL;
3245         return (NULL);
3246 }
3247
3248 const char *
3249 pmc_name_of_disposition(enum pmc_disp pd)
3250 {
3251         if ((int) pd >= PMC_DISP_FIRST &&
3252             pd <= PMC_DISP_LAST)
3253                 return (pmc_disposition_names[pd]);
3254
3255         errno = EINVAL;
3256         return (NULL);
3257 }
3258
3259 const char *
3260 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
3261 {
3262         const struct pmc_event_descr *ev, *evfence;
3263
3264         ev = evfence = NULL;
3265         if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) {
3266                 ev = iaf_event_table;
3267                 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf);
3268         } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) {
3269                 switch (cpu) {
3270                 case PMC_CPU_INTEL_ATOM:
3271                         ev = atom_event_table;
3272                         evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom);
3273                         break;
3274                 case PMC_CPU_INTEL_ATOM_SILVERMONT:
3275                         ev = atom_silvermont_event_table;
3276                         evfence = atom_silvermont_event_table +
3277                             PMC_EVENT_TABLE_SIZE(atom_silvermont);
3278                         break;
3279                 case PMC_CPU_INTEL_CORE:
3280                         ev = core_event_table;
3281                         evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core);
3282                         break;
3283                 case PMC_CPU_INTEL_CORE2:
3284                 case PMC_CPU_INTEL_CORE2EXTREME:
3285                         ev = core2_event_table;
3286                         evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2);
3287                         break;
3288                 case PMC_CPU_INTEL_COREI7:
3289                         ev = corei7_event_table;
3290                         evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
3291                         break;
3292                 case PMC_CPU_INTEL_NEHALEM_EX:
3293                         ev = nehalem_ex_event_table;
3294                         evfence = nehalem_ex_event_table +
3295                             PMC_EVENT_TABLE_SIZE(nehalem_ex);
3296                         break;
3297                 case PMC_CPU_INTEL_HASWELL:
3298                         ev = haswell_event_table;
3299                         evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell);
3300                         break;
3301                 case PMC_CPU_INTEL_HASWELL_XEON:
3302                         ev = haswell_xeon_event_table;
3303                         evfence = haswell_xeon_event_table + PMC_EVENT_TABLE_SIZE(haswell_xeon);
3304                         break;
3305
3306                 case PMC_CPU_INTEL_IVYBRIDGE:
3307                         ev = ivybridge_event_table;
3308                         evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge);
3309                         break;
3310                 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
3311                         ev = ivybridge_xeon_event_table;
3312                         evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon);
3313                         break;
3314                 case PMC_CPU_INTEL_SANDYBRIDGE:
3315                         ev = sandybridge_event_table;
3316                         evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge);
3317                         break;
3318                 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
3319                         ev = sandybridge_xeon_event_table;
3320                         evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon);
3321                         break;
3322                 case PMC_CPU_INTEL_WESTMERE:
3323                         ev = westmere_event_table;
3324                         evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere);
3325                         break;
3326                 case PMC_CPU_INTEL_WESTMERE_EX:
3327                         ev = westmere_ex_event_table;
3328                         evfence = westmere_ex_event_table +
3329                             PMC_EVENT_TABLE_SIZE(westmere_ex);
3330                         break;
3331                 default:        /* Unknown CPU type. */
3332                         break;
3333                 }
3334         } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) {
3335                 ev = ucf_event_table;
3336                 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf);
3337         } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) {
3338                 switch (cpu) {
3339                 case PMC_CPU_INTEL_COREI7:
3340                         ev = corei7uc_event_table;
3341                         evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc);
3342                         break;
3343                 case PMC_CPU_INTEL_SANDYBRIDGE:
3344                         ev = sandybridgeuc_event_table;
3345                         evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc);
3346                         break;
3347                 case PMC_CPU_INTEL_WESTMERE:
3348                         ev = westmereuc_event_table;
3349                         evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc);
3350                         break;
3351                 default:        /* Unknown CPU type. */
3352                         break;
3353                 }
3354         } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) {
3355                 ev = k7_event_table;
3356                 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7);
3357         } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
3358                 ev = k8_event_table;
3359                 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
3360         } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) {
3361                 ev = p4_event_table;
3362                 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4);
3363         } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) {
3364                 ev = p5_event_table;
3365                 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5);
3366         } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) {
3367                 ev = p6_event_table;
3368                 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6);
3369         } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) {
3370                 ev = xscale_event_table;
3371                 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale);
3372         } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) {
3373                 ev = mips24k_event_table;
3374                 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k);
3375         } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) {
3376                 ev = octeon_event_table;
3377                 evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon);
3378         } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) {
3379                 ev = ppc7450_event_table;
3380                 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450);
3381         } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) {
3382                 ev = ppc970_event_table;
3383                 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970);
3384         } else if (pe == PMC_EV_TSC_TSC) {
3385                 ev = tsc_event_table;
3386                 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc);
3387         } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) {
3388                 ev = soft_event_table;
3389                 evfence = soft_event_table + soft_event_info.pm_nevent;
3390         }
3391
3392         for (; ev != evfence; ev++)
3393                 if (pe == ev->pm_ev_code)
3394                         return (ev->pm_ev_name);
3395
3396         return (NULL);
3397 }
3398
3399 const char *
3400 pmc_name_of_event(enum pmc_event pe)
3401 {
3402         const char *n;
3403
3404         if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL)
3405                 return (n);
3406
3407         errno = EINVAL;
3408         return (NULL);
3409 }
3410
3411 const char *
3412 pmc_name_of_mode(enum pmc_mode pm)
3413 {
3414         if ((int) pm >= PMC_MODE_FIRST &&
3415             pm <= PMC_MODE_LAST)
3416                 return (pmc_mode_names[pm]);
3417
3418         errno = EINVAL;
3419         return (NULL);
3420 }
3421
3422 const char *
3423 pmc_name_of_state(enum pmc_state ps)
3424 {
3425         if ((int) ps >= PMC_STATE_FIRST &&
3426             ps <= PMC_STATE_LAST)
3427                 return (pmc_state_names[ps]);
3428
3429         errno = EINVAL;
3430         return (NULL);
3431 }
3432
3433 int
3434 pmc_ncpu(void)
3435 {
3436         if (pmc_syscall == -1) {
3437                 errno = ENXIO;
3438                 return (-1);
3439         }
3440
3441         return (cpu_info.pm_ncpu);
3442 }
3443
3444 int
3445 pmc_npmc(int cpu)
3446 {
3447         if (pmc_syscall == -1) {
3448                 errno = ENXIO;
3449                 return (-1);
3450         }
3451
3452         if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) {
3453                 errno = EINVAL;
3454                 return (-1);
3455         }
3456
3457         return (cpu_info.pm_npmc);
3458 }
3459
3460 int
3461 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci)
3462 {
3463         int nbytes, npmc;
3464         struct pmc_op_getpmcinfo *pmci;
3465
3466         if ((npmc = pmc_npmc(cpu)) < 0)
3467                 return (-1);
3468
3469         nbytes = sizeof(struct pmc_op_getpmcinfo) +
3470             npmc * sizeof(struct pmc_info);
3471
3472         if ((pmci = calloc(1, nbytes)) == NULL)
3473                 return (-1);
3474
3475         pmci->pm_cpu  = cpu;
3476
3477         if (PMC_CALL(GETPMCINFO, pmci) < 0) {
3478                 free(pmci);
3479                 return (-1);
3480         }
3481
3482         /* kernel<->library, library<->userland interfaces are identical */
3483         *ppmci = (struct pmc_pmcinfo *) pmci;
3484         return (0);
3485 }
3486
3487 int
3488 pmc_read(pmc_id_t pmc, pmc_value_t *value)
3489 {
3490         struct pmc_op_pmcrw pmc_read_op;
3491
3492         pmc_read_op.pm_pmcid = pmc;
3493         pmc_read_op.pm_flags = PMC_F_OLDVALUE;
3494         pmc_read_op.pm_value = -1;
3495
3496         if (PMC_CALL(PMCRW, &pmc_read_op) < 0)
3497                 return (-1);
3498
3499         *value = pmc_read_op.pm_value;
3500         return (0);
3501 }
3502
3503 int
3504 pmc_release(pmc_id_t pmc)
3505 {
3506         struct pmc_op_simple    pmc_release_args;
3507
3508         pmc_release_args.pm_pmcid = pmc;
3509         return (PMC_CALL(PMCRELEASE, &pmc_release_args));
3510 }
3511
3512 int
3513 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep)
3514 {
3515         struct pmc_op_pmcrw pmc_rw_op;
3516
3517         pmc_rw_op.pm_pmcid = pmc;
3518         pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE;
3519         pmc_rw_op.pm_value = newvalue;
3520
3521         if (PMC_CALL(PMCRW, &pmc_rw_op) < 0)
3522                 return (-1);
3523
3524         *oldvaluep = pmc_rw_op.pm_value;
3525         return (0);
3526 }
3527
3528 int
3529 pmc_set(pmc_id_t pmc, pmc_value_t value)
3530 {
3531         struct pmc_op_pmcsetcount sc;
3532
3533         sc.pm_pmcid = pmc;
3534         sc.pm_count = value;
3535
3536         if (PMC_CALL(PMCSETCOUNT, &sc) < 0)
3537                 return (-1);
3538         return (0);
3539 }
3540
3541 int
3542 pmc_start(pmc_id_t pmc)
3543 {
3544         struct pmc_op_simple    pmc_start_args;
3545
3546         pmc_start_args.pm_pmcid = pmc;
3547         return (PMC_CALL(PMCSTART, &pmc_start_args));
3548 }
3549
3550 int
3551 pmc_stop(pmc_id_t pmc)
3552 {
3553         struct pmc_op_simple    pmc_stop_args;
3554
3555         pmc_stop_args.pm_pmcid = pmc;
3556         return (PMC_CALL(PMCSTOP, &pmc_stop_args));
3557 }
3558
3559 int
3560 pmc_width(pmc_id_t pmcid, uint32_t *width)
3561 {
3562         unsigned int i;
3563         enum pmc_class cl;
3564
3565         cl = PMC_ID_TO_CLASS(pmcid);
3566         for (i = 0; i < cpu_info.pm_nclass; i++)
3567                 if (cpu_info.pm_classes[i].pm_class == cl) {
3568                         *width = cpu_info.pm_classes[i].pm_width;
3569                         return (0);
3570                 }
3571         errno = EINVAL;
3572         return (-1);
3573 }
3574
3575 int
3576 pmc_write(pmc_id_t pmc, pmc_value_t value)
3577 {
3578         struct pmc_op_pmcrw pmc_write_op;
3579
3580         pmc_write_op.pm_pmcid = pmc;
3581         pmc_write_op.pm_flags = PMC_F_NEWVALUE;
3582         pmc_write_op.pm_value = value;
3583         return (PMC_CALL(PMCRW, &pmc_write_op));
3584 }
3585
3586 int
3587 pmc_writelog(uint32_t userdata)
3588 {
3589         struct pmc_op_writelog wl;
3590
3591         wl.pm_userdata = userdata;
3592         return (PMC_CALL(WRITELOG, &wl));
3593 }