2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
3 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (c) 2012 Luiz Otavio O Souza.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
40 #include <sys/mutex.h>
43 #include <machine/bus.h>
44 #include <machine/cpu.h>
45 #include <machine/cpufunc.h>
46 #include <machine/resource.h>
47 #include <machine/fdt.h>
48 #include <machine/intr.h>
50 #include <dev/fdt/fdt_common.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
58 * A10 have 9 banks of gpio.
60 * PA0 - PA17 | PB0 - PB23 | PC0 - PC24
61 * PD0 - PD27 | PE0 - PE31 | PF0 - PF5
62 * PG0 - PG9 | PH0 - PH27 | PI0 - PI12
65 #define A10_GPIO_PINS 288
66 #define A10_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
67 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
69 #define A10_GPIO_NONE 0
70 #define A10_GPIO_PULLUP 1
71 #define A10_GPIO_PULLDOWN 2
73 #define A10_GPIO_INPUT 0
74 #define A10_GPIO_OUTPUT 1
76 struct a10_gpio_softc {
79 struct resource * sc_mem_res;
80 struct resource * sc_irq_res;
81 bus_space_tag_t sc_bst;
82 bus_space_handle_t sc_bsh;
85 struct gpio_pin sc_gpio_pins[A10_GPIO_PINS];
88 #define A10_GPIO_LOCK(_sc) mtx_lock(&_sc->sc_mtx)
89 #define A10_GPIO_UNLOCK(_sc) mtx_unlock(&_sc->sc_mtx)
90 #define A10_GPIO_LOCK_ASSERT(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
92 #define A10_GPIO_GP_CFG(_bank, _pin) 0x00 + ((_bank) * 0x24) + ((_pin)<<2)
93 #define A10_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24)
94 #define A10_GPIO_GP_DRV(_bank, _pin) 0x14 + ((_bank) * 0x24) + ((_pin)<<2)
95 #define A10_GPIO_GP_PUL(_bank, _pin) 0x1c + ((_bank) * 0x24) + ((_pin)<<2)
97 #define A10_GPIO_GP_INT_CFG0 0x200
98 #define A10_GPIO_GP_INT_CFG1 0x204
99 #define A10_GPIO_GP_INT_CFG2 0x208
100 #define A10_GPIO_GP_INT_CFG3 0x20c
102 #define A10_GPIO_GP_INT_CTL 0x210
103 #define A10_GPIO_GP_INT_STA 0x214
104 #define A10_GPIO_GP_INT_DEB 0x218
106 static struct a10_gpio_softc *a10_gpio_sc;
108 #define A10_GPIO_WRITE(_sc, _off, _val) \
109 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
110 #define A10_GPIO_READ(_sc, _off) \
111 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
114 a10_gpio_get_function(struct a10_gpio_softc *sc, uint32_t pin)
116 uint32_t bank, func, offset;
119 pin = pin - 32 * bank;
121 offset = ((pin & 0x07) << 2);
124 func = (A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, func)) >> offset) & 7;
131 a10_gpio_func_flag(uint32_t nfunc)
136 return (GPIO_PIN_INPUT);
137 case A10_GPIO_OUTPUT:
138 return (GPIO_PIN_OUTPUT);
144 a10_gpio_set_function(struct a10_gpio_softc *sc, uint32_t pin, uint32_t f)
146 uint32_t bank, func, data, offset;
148 /* Must be called with lock held. */
149 A10_GPIO_LOCK_ASSERT(sc);
152 pin = pin - 32 * bank;
154 offset = ((pin & 0x07) << 2);
156 data = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, func));
157 data &= ~(7 << offset);
158 data |= (f << offset);
159 A10_GPIO_WRITE(sc, A10_GPIO_GP_CFG(bank, func), data);
163 a10_gpio_set_pud(struct a10_gpio_softc *sc, uint32_t pin, uint32_t state)
165 uint32_t bank, offset, pull, val;
167 /* Must be called with lock held. */
168 A10_GPIO_LOCK_ASSERT(sc);
171 pin = pin - 32 * bank;
173 offset = ((pin & 0x0f) << 1);
175 val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pull));
176 val &= ~(0x03 << offset);
177 val |= (state << offset);
178 A10_GPIO_WRITE(sc, A10_GPIO_GP_PUL(bank, pull), val);
182 a10_gpio_pin_configure(struct a10_gpio_softc *sc, struct gpio_pin *pin,
189 * Manage input/output.
191 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
192 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
193 if (flags & GPIO_PIN_OUTPUT) {
194 pin->gp_flags |= GPIO_PIN_OUTPUT;
195 a10_gpio_set_function(sc, pin->gp_pin,
198 pin->gp_flags |= GPIO_PIN_INPUT;
199 a10_gpio_set_function(sc, pin->gp_pin,
204 /* Manage Pull-up/pull-down. */
205 pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN);
206 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) {
207 if (flags & GPIO_PIN_PULLUP) {
208 pin->gp_flags |= GPIO_PIN_PULLUP;
209 a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_PULLUP);
211 pin->gp_flags |= GPIO_PIN_PULLDOWN;
212 a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_PULLDOWN);
215 a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_NONE);
221 a10_gpio_pin_max(device_t dev, int *maxpin)
224 *maxpin = A10_GPIO_PINS - 1;
229 a10_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
231 struct a10_gpio_softc *sc = device_get_softc(dev);
234 for (i = 0; i < sc->sc_gpio_npins; i++) {
235 if (sc->sc_gpio_pins[i].gp_pin == pin)
239 if (i >= sc->sc_gpio_npins)
243 *caps = sc->sc_gpio_pins[i].gp_caps;
250 a10_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
252 struct a10_gpio_softc *sc = device_get_softc(dev);
255 for (i = 0; i < sc->sc_gpio_npins; i++) {
256 if (sc->sc_gpio_pins[i].gp_pin == pin)
260 if (i >= sc->sc_gpio_npins)
264 *flags = sc->sc_gpio_pins[i].gp_flags;
271 a10_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
273 struct a10_gpio_softc *sc = device_get_softc(dev);
276 for (i = 0; i < sc->sc_gpio_npins; i++) {
277 if (sc->sc_gpio_pins[i].gp_pin == pin)
281 if (i >= sc->sc_gpio_npins)
285 memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME);
292 a10_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
294 struct a10_gpio_softc *sc = device_get_softc(dev);
297 for (i = 0; i < sc->sc_gpio_npins; i++) {
298 if (sc->sc_gpio_pins[i].gp_pin == pin)
302 if (i >= sc->sc_gpio_npins)
305 a10_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags);
311 a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
313 struct a10_gpio_softc *sc = device_get_softc(dev);
314 uint32_t bank, offset, data;
317 for (i = 0; i < sc->sc_gpio_npins; i++) {
318 if (sc->sc_gpio_pins[i].gp_pin == pin)
322 if (i >= sc->sc_gpio_npins)
326 pin = pin - 32 * bank;
330 data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
332 data |= (1 << offset);
334 data &= ~(1 << offset);
335 A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
342 a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
344 struct a10_gpio_softc *sc = device_get_softc(dev);
345 uint32_t bank, offset, reg_data;
348 for (i = 0; i < sc->sc_gpio_npins; i++) {
349 if (sc->sc_gpio_pins[i].gp_pin == pin)
353 if (i >= sc->sc_gpio_npins)
357 pin = pin - 32 * bank;
361 reg_data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
363 *val = (reg_data & (1 << offset)) ? 1 : 0;
369 a10_gpio_pin_toggle(device_t dev, uint32_t pin)
371 struct a10_gpio_softc *sc = device_get_softc(dev);
372 uint32_t bank, data, offset;
375 for (i = 0; i < sc->sc_gpio_npins; i++) {
376 if (sc->sc_gpio_pins[i].gp_pin == pin)
380 if (i >= sc->sc_gpio_npins)
384 pin = pin - 32 * bank;
388 data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
389 if (data & (1 << offset))
390 data &= ~(1 << offset);
392 data |= (1 << offset);
393 A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
400 a10_gpio_probe(device_t dev)
403 if (!ofw_bus_status_okay(dev))
406 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-gpio"))
409 device_set_desc(dev, "Allwinner GPIO controller");
410 return (BUS_PROBE_DEFAULT);
414 a10_gpio_attach(device_t dev)
416 struct a10_gpio_softc *sc = device_get_softc(dev);
423 mtx_init(&sc->sc_mtx, "a10 gpio", "gpio", MTX_DEF);
426 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
428 if (!sc->sc_mem_res) {
429 device_printf(dev, "cannot allocate memory window\n");
433 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
434 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
437 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
439 if (!sc->sc_irq_res) {
440 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
441 device_printf(dev, "cannot allocate interrupt\n");
446 gpio = ofw_bus_get_node(sc->sc_dev);
448 if (!OF_hasprop(gpio, "gpio-controller"))
449 /* Node is not a GPIO controller. */
452 /* Initialize the software controlled pins. */
453 for (i = 0; i < A10_GPIO_PINS; i++) {
454 snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME,
456 func = a10_gpio_get_function(sc, i);
457 sc->sc_gpio_pins[i].gp_pin = i;
458 sc->sc_gpio_pins[i].gp_caps = A10_GPIO_DEFAULT_CAPS;
459 sc->sc_gpio_pins[i].gp_flags = a10_gpio_func_flag(func);
461 sc->sc_gpio_npins = i;
463 device_add_child(dev, "gpioc", -1);
464 device_add_child(dev, "gpiobus", -1);
468 return (bus_generic_attach(dev));
472 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
474 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
479 a10_gpio_detach(device_t dev)
485 static device_method_t a10_gpio_methods[] = {
486 /* Device interface */
487 DEVMETHOD(device_probe, a10_gpio_probe),
488 DEVMETHOD(device_attach, a10_gpio_attach),
489 DEVMETHOD(device_detach, a10_gpio_detach),
492 DEVMETHOD(gpio_pin_max, a10_gpio_pin_max),
493 DEVMETHOD(gpio_pin_getname, a10_gpio_pin_getname),
494 DEVMETHOD(gpio_pin_getflags, a10_gpio_pin_getflags),
495 DEVMETHOD(gpio_pin_getcaps, a10_gpio_pin_getcaps),
496 DEVMETHOD(gpio_pin_setflags, a10_gpio_pin_setflags),
497 DEVMETHOD(gpio_pin_get, a10_gpio_pin_get),
498 DEVMETHOD(gpio_pin_set, a10_gpio_pin_set),
499 DEVMETHOD(gpio_pin_toggle, a10_gpio_pin_toggle),
504 static devclass_t a10_gpio_devclass;
506 static driver_t a10_gpio_driver = {
509 sizeof(struct a10_gpio_softc),
512 DRIVER_MODULE(a10_gpio, simplebus, a10_gpio_driver, a10_gpio_devclass, 0, 0);
515 a10_emac_gpio_config(uint32_t pin)
517 struct a10_gpio_softc *sc = a10_gpio_sc;
522 /* Configure pin mux settings for MII. */
524 a10_gpio_set_function(sc, pin, A10_GPIO_PULLDOWN);