1 /* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */
4 * Copyright 2011 Semihalf
5 * Copyright (C) 1994-1997 Mark Brinicombe
6 * Copyright (C) 1994 Brini
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Brini.
20 * 4. The name of Brini may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <sys/syscall.h>
38 #include <machine/asm.h>
39 #include <machine/armreg.h>
40 #include <machine/cpuconf.h>
41 #include <machine/pte.h>
43 __FBSDID("$FreeBSD$");
46 * Sanity check the configuration.
47 * FLASHADDR and LOADERRAMADDR depend on PHYSADDR in some cases.
48 * ARMv4 and ARMv5 make assumptions on where they are loaded.
50 * TODO: Fix the ARMv4/v5 case.
52 #if (defined(FLASHADDR) || defined(LOADERRAMADDR) || !defined(_ARM_ARCH_6)) && \
54 #error PHYSADDR must be defined for this configuration
57 /* What size should this really be ? It is only used by initarm() */
58 #define INIT_ARM_STACK_SIZE (2048 * 4)
60 #define CPWAIT_BRANCH \
64 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
65 mov tmp, tmp /* wait for it to complete */ ;\
66 CPWAIT_BRANCH /* branch to next insn */
69 * This is for libkvm, and should be the address of the beginning
70 * of the kernel text segment (not necessarily the same as kernbase).
72 * These are being phased out. Newer copies of libkvm don't need these
73 * values as the information is added to the core file by inspecting
80 .set kernbase,KERNBASE
82 .set physaddr,PHYSADDR
86 * On entry for FreeBSD boot ABI:
87 * r0 - metadata pointer or 0 (boothowto on AT91's boot2)
88 * r1 - if (r0 == 0) then metadata pointer
89 * On entry for Linux boot ABI:
91 * r1 - machine type (passed as arg2 to initarm)
92 * r2 - Pointer to a tagged list or dtb image (phys addr) (passed as arg1 initarm)
94 * For both types of boot we gather up the args, put them in a struct arm_boot_params
95 * structure and pass that to initarm.
100 STOP_UNWINDING /* Can't unwind into the bootloader! */
102 mov r9, r0 /* 0 or boot mode from boot2 */
103 mov r8, r1 /* Save Machine type */
104 mov ip, r2 /* Save meta data */
105 mov fp, r3 /* Future expansion */
107 /* Make sure interrupts are disabled. */
109 orr r7, r7, #(PSR_I | PSR_F)
112 #if defined (FLASHADDR) && defined(LOADERRAMADDR)
113 /* Check if we're running from flash. */
116 * If we're running with MMU disabled, test against the
117 * physical address instead.
119 mrc p15, 0, r2, c1, c0, 0
120 ands r2, r2, #CPU_CONTROL_MMU_ENABLE
122 ldrne r6, =LOADERRAMADDR
144 Lram_offset: .word from_ram-_C_LABEL(_start)
150 /* Disable MMU for a while */
151 mrc p15, 0, r2, c1, c0, 0
152 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
153 CPU_CONTROL_WBUF_ENABLE)
154 bic r2, r2, #(CPU_CONTROL_IC_ENABLE)
155 bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE)
156 mcr p15, 0, r2, c1, c0, 0
165 * Build page table from scratch.
168 /* Find the delta between VA and PA */
170 bl translate_va_to_pa
174 * Some of the older ports (the various XScale, mostly) assume
175 * that the memory before the kernel is mapped, and use it for
176 * the various stacks, page tables, etc. For those CPUs, map the
177 * 64 first MB of RAM, as it used to be.
185 /* Map 64MiB, preserved over calls to build_pagetables */
189 /* Create the kernel map to jump to */
193 ldr r5, =(KERNPHYSADDR)
198 /* Find the start kernels load address */
200 ldr r2, =(L1_S_OFFSET)
204 /* Map 64MiB, preserved over calls to build_pagetables */
208 /* Create the kernel map to jump to */
210 ldr r2, =(KERNVIRTADDR)
214 #if defined(SOCDEV_PA) && defined(SOCDEV_VA)
215 /* Create the custom map */
222 orr r0, r0, #2 /* Set TTB shared memory flag */
224 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
225 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
227 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
229 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
232 /* Set the Domain Access register. Very important! */
233 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
234 mcr p15, 0, r0, c3, c0, 0
237 * On armv6 enable extended page tables, and set alignment checking
238 * to modulo-4 (CPU_CONTROL_UNAL_ENABLE) for the ldrd/strd
239 * instructions emitted by clang.
241 mrc p15, 0, r0, c1, c0, 0
243 orr r0, r0, #(CPU_CONTROL_V6_EXTPAGE | CPU_CONTROL_UNAL_ENABLE)
244 orr r0, r0, #(CPU_CONTROL_AFLT_ENABLE)
245 orr r0, r0, #(CPU_CONTROL_AF_ENABLE)
247 orr r0, r0, #(CPU_CONTROL_MMU_ENABLE)
248 mcr p15, 0, r0, c1, c0, 0
257 ldmia r1, {r1, r2, sp} /* Set initial stack and */
258 sub r2, r2, r1 /* get zero init data */
261 str r3, [r1], #0x0004 /* get zero init data */
267 mov r1, #28 /* loader info size is 28 bytes also second arg */
268 subs sp, sp, r1 /* allocate arm_boot_params struct on stack */
269 mov r0, sp /* loader info pointer is first arg */
270 bic sp, sp, #7 /* align stack to 8 bytes */
271 str r1, [r0] /* Store length of loader info */
272 str r9, [r0, #4] /* Store r0 from boot loader */
273 str r8, [r0, #8] /* Store r1 from boot loader */
274 str ip, [r0, #12] /* store r2 from boot loader */
275 str fp, [r0, #16] /* store r3 from boot loader */
276 str r5, [r0, #20] /* store the physical address */
277 adr r4, Lpagetable /* load the pagetable address */
279 str r5, [r0, #24] /* store the pagetable address */
280 mov fp, #0 /* trace back starts here */
281 bl _C_LABEL(initarm) /* Off we go */
283 /* init arm will return the new stack pointer. */
286 bl _C_LABEL(mi_startup) /* call mi_startup()! */
288 adr r0, .Lmainreturned
293 #define VA_TO_PA_POINTER(name, table) \
299 * Returns the physical address of a magic va to pa pointer.
300 * r0 - The pagetable data pointer. This must be built using the
301 * VA_TO_PA_POINTER macro.
303 * VA_TO_PA_POINTER(Lpagetable, pagetable)
306 * bl translate_va_to_pa
307 * r0 will now contain the physical address of pagetable
313 /* At this point: r2 = VA - PA */
316 * Find the physical address of the table. After these two
320 * r0 = va(pagetable) - (VA - PA)
321 * = va(pagetable) - VA + PA
329 * Builds the page table
330 * r0 - The table base address
331 * r1 - The physical address (trashed)
332 * r2 - The virtual address (trashed)
333 * r3 - The number of 1MiB sections
336 * Addresses must be 1MiB aligned
339 /* Set the required page attributed */
340 ldr r4, =(L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
346 /* Move the virtual address to the correct bit location */
347 lsr r2, #(L1_S_SHIFT - 2)
353 add r1, r1, #(L1_S_SIZE)
359 VA_TO_PA_POINTER(Lpagetable, pagetable)
369 .word svcstk + INIT_ARM_STACK_SIZE
375 .asciz "main() returned"
380 .space INIT_ARM_STACK_SIZE
383 * Memory for the initial pagetable. We are unable to place this in
384 * the bss as this will be cleared after the table is loaded.
386 .section ".init_pagetable"
387 .align 14 /* 16KiB aligned */
395 .word _C_LABEL(cpufuncs)
401 VA_TO_PA_POINTER(Lstartup_pagetable_secondary, temp_pagetable)
405 /* Make sure interrupts are disabled. */
407 orr r7, r7, #(PSR_I | PSR_F)
410 /* Disable MMU. It should be disabled already, but make sure. */
411 mrc p15, 0, r2, c1, c0, 0
412 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
413 CPU_CONTROL_WBUF_ENABLE)
414 bic r2, r2, #(CPU_CONTROL_IC_ENABLE)
415 bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE)
416 mcr p15, 0, r2, c1, c0, 0
423 bl armv6_idcache_inv_all /* Modifies r0 only */
425 bl armv7_idcache_inv_all /* Modifies r0-r3, ip */
428 /* Load the page table physical address */
429 adr r0, Lstartup_pagetable_secondary
430 bl translate_va_to_pa
431 /* Load the address the secondary page table */
434 orr r0, r0, #2 /* Set TTB shared memory flag */
435 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
436 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
439 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
441 /* Set the Domain Access register. Very important! */
442 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
443 mcr p15, 0, r0, c3, c0, 0
445 mrc p15, 0, r0, c1, c0, 0
446 orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
447 orr r0, r0, #CPU_CONTROL_AF_ENABLE
448 orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
449 CPU_CONTROL_WBUF_ENABLE)
450 orr r0, r0, #(CPU_CONTROL_IC_ENABLE)
451 orr r0, r0, #(CPU_CONTROL_BPRD_ENABLE)
452 mcr p15, 0, r0, c1, c0, 0
459 ldmia r1, {r1, r2, sp} /* Set initial stack and */
460 mrc p15, 0, r0, c0, c0, 5
466 ldr pc, .Lmpvirt_done
470 mov fp, #0 /* trace back starts here */
471 bl _C_LABEL(init_secondary) /* Off we go */
478 .asciz "init_secondary() returned"
485 bic r2, r2, #(PSR_MODE)
486 orr r2, r2, #(PSR_SVC32_MODE)
487 orr r2, r2, #(PSR_I | PSR_F)
490 ldr r4, .Lcpu_reset_address
495 ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
497 ldr pc, [r0, #CF_L2CACHE_WBINV_ALL]
500 * Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's
504 ldr r1, .Lcpu_reset_needs_v4_MMU_disable
510 * MMU & IDC off, 32 bit program & data space
511 * Hurl ourselves into the ROM
513 mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE)
514 mcr p15, 0, r0, c1, c0, 0
515 mcrne p15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
519 * _cpu_reset_address contains the address to branch to, to complete
520 * the cpu reset after turning the MMU off
521 * This variable is provided by the hardware specific code
524 .word _C_LABEL(cpu_reset_address)
527 * cpu_reset_needs_v4_MMU_disable contains a flag that signals if the
528 * v4 MMU disable instruction needs executing... it is an illegal instruction
529 * on f.e. ARM6/7 that locks up the computer in an endless illegal
530 * instruction / data-abort / reset loop.
532 .Lcpu_reset_needs_v4_MMU_disable:
533 .word _C_LABEL(cpu_reset_needs_v4_MMU_disable)
553 .global _C_LABEL(esym)
554 _C_LABEL(esym): .word _C_LABEL(end)
565 * Call the sigreturn system call.
567 * We have to load r7 manually rather than using
568 * "ldr r7, =SYS_sigreturn" to ensure the value of szsigcode is
569 * correct. Using the alternative places esigcode at the address
570 * of the data rather than the address one past the data.
573 ldr r7, [pc, #12] /* Load SYS_sigreturn */
576 /* Well if that failed we better exit quick ! */
578 ldr r7, [pc, #8] /* Load SYS_exit */
581 /* Branch back to retry SYS_sigreturn */
588 .global _C_LABEL(esigcode)
594 .long esigcode-sigcode
596 /* End of locore.S */