2 * Copyright (c) 2011 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28 #include <sys/param.h>
29 #include <sys/systm.h>
31 #include <sys/kernel.h>
33 #include <sys/mutex.h>
36 #include <sys/sched.h>
39 #include <sys/malloc.h>
42 #include <vm/vm_extern.h>
43 #include <vm/vm_kern.h>
46 #include <machine/armreg.h>
47 #include <machine/cpu.h>
48 #include <machine/cpufunc.h>
49 #include <machine/smp.h>
50 #include <machine/pcb.h>
51 #include <machine/pte.h>
52 #include <machine/physmem.h>
53 #include <machine/intr.h>
54 #include <machine/vmparam.h>
56 #include <machine/vfp.h>
59 #include <arm/mv/mvwin.h>
60 #include <dev/fdt/fdt_common.h>
65 extern struct pcpu __pcpu[];
66 /* used to hold the AP's until we are ready to release them */
67 struct mtx ap_boot_mtx;
68 struct pcb stoppcbs[MAXCPU];
70 /* # of Applications processors */
73 /* Set to 1 once we're ready to let the APs out of the pen. */
74 volatile int aps_ready = 0;
76 static int ipi_handler(void *arg);
77 void set_stackptrs(int cpu);
79 /* Temporary variables for init_secondary() */
80 void *dpcpu[MAXCPU - 1];
82 /* Determine if we running MP machine */
86 CPU_SETOF(0, &all_cpus);
88 return (platform_mp_probe());
91 /* Start Application Processor via platform specific function */
97 for (ms = 0; ms < 2000; ++ms) {
98 if ((mp_naps + 1) == mp_ncpus)
99 return (0); /* success */
107 extern unsigned char _end[];
109 /* Initialize and fire up non-boot processors */
115 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
117 /* Reserve memory for application processors */
118 for(i = 0; i < (mp_ncpus - 1); i++)
119 dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
122 cpu_idcache_wbinv_all();
123 cpu_l2cache_wbinv_all();
124 cpu_idcache_wbinv_all();
126 /* Initialize boot code and start up processors */
127 platform_mp_start_ap();
129 /* Check if ap's started properly */
132 printf("WARNING: Some AP's failed to start\n");
134 for (i = 1; i < mp_ncpus; i++)
135 CPU_SET(i, &all_cpus);
139 /* Introduce rest of cores to the world */
141 cpu_mp_announce(void)
146 extern vm_paddr_t pmap_pa;
148 init_secondary(int cpu)
151 uint32_t loop_counter;
152 int start = 0, end = 0;
161 * pcpu_init() updates queue, so it should not be executed in parallel
164 while(mp_naps < (cpu - 1))
167 pcpu_init(pc, cpu, sizeof(struct pcpu));
168 dpcpu_init(dpcpu[cpu - 1], cpu);
170 /* Provide stack pointers for other processor modes. */
173 /* Signal our startup to BSP */
174 atomic_add_rel_32(&mp_naps, 1);
176 /* Spin until the BSP releases the APs */
180 /* Initialize curthread */
181 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
182 pc->pc_curthread = pc->pc_idlethread;
183 pc->pc_curpcb = pc->pc_idlethread->td_pcb;
184 set_curthread(pc->pc_idlethread);
191 mtx_lock_spin(&ap_boot_mtx);
193 atomic_add_rel_32(&smp_cpus, 1);
195 if (smp_cpus == mp_ncpus) {
196 /* enable IPI's, tlb shootdown, freezes etc */
197 atomic_store_rel_int(&smp_started, 1);
200 mtx_unlock_spin(&ap_boot_mtx);
204 start = IPI_IRQ_START;
212 for (int i = start; i <= end; i++)
214 enable_interrupts(PSR_I);
217 while (smp_started == 0) {
220 if (loop_counter == 1000)
221 CTR0(KTR_SMP, "AP still wait for smp_started");
223 /* Start per-CPU event timers. */
226 CTR0(KTR_SMP, "go into scheduler");
227 platform_mp_init_secondary();
229 /* Enter the scheduler */
232 panic("scheduler returned us to %s", __func__);
237 ipi_handler(void *arg)
241 cpu = PCPU_GET(cpuid);
243 ipi = pic_ipi_get((int)arg);
245 while ((ipi != 0x3ff)) {
248 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
249 smp_rendezvous_action();
253 CTR0(KTR_SMP, "IPI_AST");
258 * IPI_STOP_HARD is mapped to IPI_STOP so it is not
259 * necessary to add it in the switch.
261 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
263 savectx(&stoppcbs[cpu]);
266 * CPUs are stopped when entering the debugger and at
267 * system shutdown, both events which can precede a
268 * panic dump. For the dump to be correct, all caches
269 * must be flushed and invalidated, but on ARM there's
270 * no way to broadcast a wbinv_all to other cores.
271 * Instead, we have each core do the local wbinv_all as
272 * part of stopping the core. The core requesting the
273 * stop will do the l2 cache flush after all other cores
274 * have done their l1 flushes and stopped.
276 cpu_idcache_wbinv_all();
278 /* Indicate we are stopped */
279 CPU_SET_ATOMIC(cpu, &stopped_cpus);
281 /* Wait for restart */
282 while (!CPU_ISSET(cpu, &started_cpus))
285 CPU_CLR_ATOMIC(cpu, &started_cpus);
286 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
287 CTR0(KTR_SMP, "IPI_STOP (restart)");
290 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
291 sched_preempt(curthread);
294 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
298 CTR1(KTR_SMP, "%s: IPI_TLB", __func__);
299 cpufuncs.cf_tlb_flushID();
302 panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu);
306 ipi = pic_ipi_get(-1);
309 return (FILTER_HANDLED);
313 release_aps(void *dummy __unused)
315 uint32_t loop_counter;
316 int start = 0, end = 0;
321 start = IPI_IRQ_START;
329 for (int i = start; i <= end; i++) {
334 * Use 0xdeadbeef as the argument value for irq 0,
335 * if we used 0, the intr code will give the trap frame
338 arm_setup_irqhandler("ipi", ipi_handler, NULL, (void *)i, i,
339 INTR_TYPE_MISC | INTR_EXCL, NULL);
344 atomic_store_rel_int(&aps_ready, 1);
346 printf("Release APs\n");
348 for (loop_counter = 0; loop_counter < 2000; loop_counter++) {
353 printf("AP's not started\n");
356 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
362 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0));
366 cpu_mp_setmaxid(void)
369 platform_mp_setmaxid();
374 ipi_all_but_self(u_int ipi)
378 other_cpus = all_cpus;
379 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
380 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
381 platform_ipi_send(other_cpus, ipi);
385 ipi_cpu(int cpu, u_int ipi)
392 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
393 platform_ipi_send(cpus, ipi);
397 ipi_selected(cpuset_t cpus, u_int ipi)
400 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
401 platform_ipi_send(cpus, ipi);
405 tlb_broadcast(int ipi)
409 ipi_all_but_self(ipi);