1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2011 Semihalf
4 * Copyright 2004 Olivier Houchard.
5 * Copyright 2003 Wasabi Systems, Inc.
8 * Written by Steve C. Woodford for Wasabi Systems, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed for the NetBSD Project by
21 * Wasabi Systems, Inc.
22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23 * or promote products derived from this software without specific prior
26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
38 * From: FreeBSD: src/sys/arm/arm/pmap.c,v 1.113 2009/07/24 13:50:29
42 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
43 * Copyright (c) 2001 Richard Earnshaw
44 * Copyright (c) 2001-2002 Christopher Gilbert
45 * All rights reserved.
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 * 3. The name of the company nor the name of the author may be used to
53 * endorse or promote products derived from this software without specific
54 * prior written permission.
56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
57 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
58 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
59 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
60 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
61 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
63 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
64 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
65 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 * Copyright (c) 1999 The NetBSD Foundation, Inc.
70 * All rights reserved.
72 * This code is derived from software contributed to The NetBSD Foundation
73 * by Charles M. Hannum.
75 * Redistribution and use in source and binary forms, with or without
76 * modification, are permitted provided that the following conditions
78 * 1. Redistributions of source code must retain the above copyright
79 * notice, this list of conditions and the following disclaimer.
80 * 2. Redistributions in binary form must reproduce the above copyright
81 * notice, this list of conditions and the following disclaimer in the
82 * documentation and/or other materials provided with the distribution.
84 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
85 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
86 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
87 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
88 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
89 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
90 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
91 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
92 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
93 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
94 * POSSIBILITY OF SUCH DAMAGE.
98 * Copyright (c) 1994-1998 Mark Brinicombe.
99 * Copyright (c) 1994 Brini.
100 * All rights reserved.
102 * This code is derived from software written for Brini by Mark Brinicombe
104 * Redistribution and use in source and binary forms, with or without
105 * modification, are permitted provided that the following conditions
107 * 1. Redistributions of source code must retain the above copyright
108 * notice, this list of conditions and the following disclaimer.
109 * 2. Redistributions in binary form must reproduce the above copyright
110 * notice, this list of conditions and the following disclaimer in the
111 * documentation and/or other materials provided with the distribution.
112 * 3. All advertising materials mentioning features or use of this software
113 * must display the following acknowledgement:
114 * This product includes software developed by Mark Brinicombe.
115 * 4. The name of the author may not be used to endorse or promote products
116 * derived from this software without specific prior written permission.
118 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
119 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
120 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
121 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
122 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
123 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
124 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
125 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
126 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
128 * RiscBSD kernel project
132 * Machine dependant vm stuff
138 * Special compilation symbols
139 * PMAP_DEBUG - Build in pmap_debug_level code
141 * Note that pmap_mapdev() and pmap_unmapdev() are implemented in arm/devmap.c
143 /* Include header files */
146 #include "opt_pmap.h"
148 #include <sys/cdefs.h>
149 __FBSDID("$FreeBSD$");
150 #include <sys/param.h>
151 #include <sys/systm.h>
152 #include <sys/kernel.h>
154 #include <sys/lock.h>
155 #include <sys/proc.h>
156 #include <sys/malloc.h>
157 #include <sys/msgbuf.h>
158 #include <sys/mutex.h>
159 #include <sys/vmmeter.h>
160 #include <sys/mman.h>
161 #include <sys/rwlock.h>
163 #include <sys/sched.h>
164 #include <sys/sysctl.h>
167 #include <vm/vm_param.h>
170 #include <vm/vm_kern.h>
171 #include <vm/vm_object.h>
172 #include <vm/vm_map.h>
173 #include <vm/vm_page.h>
174 #include <vm/vm_pageout.h>
175 #include <vm/vm_phys.h>
176 #include <vm/vm_extern.h>
177 #include <vm/vm_reserv.h>
179 #include <machine/md_var.h>
180 #include <machine/cpu.h>
181 #include <machine/cpufunc.h>
182 #include <machine/pcb.h>
185 extern int last_fault_code;
189 #define PDEBUG(_lev_,_stat_) \
190 if (pmap_debug_level >= (_lev_)) \
192 #define dprintf printf
194 int pmap_debug_level = 0;
196 #else /* PMAP_DEBUG */
197 #define PDEBUG(_lev_,_stat_) /* Nothing */
198 #define dprintf(x, arg...)
199 #define PMAP_INLINE __inline
200 #endif /* PMAP_DEBUG */
203 #define PV_STAT(x) do { x ; } while (0)
205 #define PV_STAT(x) do { } while (0)
208 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
211 #define pmap_l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range((pa), (size))
212 #define pmap_l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range((pa), (size))
214 #define pmap_l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range((va), (size))
215 #define pmap_l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range((va), (size))
218 extern struct pv_addr systempage;
221 * Internal function prototypes
225 struct pv_entry *pmap_find_pv(struct md_page *, pmap_t, vm_offset_t);
226 static void pmap_free_pv_chunk(struct pv_chunk *pc);
227 static void pmap_free_pv_entry(pmap_t pmap, pv_entry_t pv);
228 static pv_entry_t pmap_get_pv_entry(pmap_t pmap, boolean_t try);
229 static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap);
230 static boolean_t pmap_pv_insert_section(pmap_t, vm_offset_t,
232 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vm_offset_t);
233 static int pmap_pvh_wired_mappings(struct md_page *, int);
235 static int pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
237 static vm_paddr_t pmap_extract_locked(pmap_t pmap, vm_offset_t va);
238 static void pmap_alloc_l1(pmap_t);
239 static void pmap_free_l1(pmap_t);
241 static void pmap_map_section(pmap_t, vm_offset_t, vm_offset_t,
242 vm_prot_t, boolean_t);
243 static void pmap_promote_section(pmap_t, vm_offset_t);
244 static boolean_t pmap_demote_section(pmap_t, vm_offset_t);
245 static boolean_t pmap_enter_section(pmap_t, vm_offset_t, vm_page_t,
247 static void pmap_remove_section(pmap_t, vm_offset_t);
249 static int pmap_clearbit(struct vm_page *, u_int);
251 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
252 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
253 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
254 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
256 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
258 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
259 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
260 vm_offset_t pmap_curmaxkvaddr;
261 vm_paddr_t kernel_l1pa;
263 vm_offset_t kernel_vm_end = 0;
265 vm_offset_t vm_max_kernel_address;
267 struct pmap kernel_pmap_store;
270 * Resources for quickly copying and zeroing pages using virtual address space
271 * and page table entries that are pre-allocated per-CPU by pmap_init().
280 static struct czpages cpu_czpages[MAXCPU];
282 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
284 * These routines are called when the CPU type is identified to set up
285 * the PTE prototypes, cache modes, etc.
287 * The variables are always here, just in case LKMs need to reference
288 * them (though, they shouldn't).
290 static void pmap_set_prot(pt_entry_t *pte, vm_prot_t prot, uint8_t user);
291 pt_entry_t pte_l1_s_cache_mode;
292 pt_entry_t pte_l1_s_cache_mode_pt;
294 pt_entry_t pte_l2_l_cache_mode;
295 pt_entry_t pte_l2_l_cache_mode_pt;
297 pt_entry_t pte_l2_s_cache_mode;
298 pt_entry_t pte_l2_s_cache_mode_pt;
300 struct msgbuf *msgbufp = 0;
305 static caddr_t crashdumpmap;
307 extern void bcopy_page(vm_offset_t, vm_offset_t);
308 extern void bzero_page(vm_offset_t);
313 * Metadata for L1 translation tables.
316 /* Entry on the L1 Table list */
317 SLIST_ENTRY(l1_ttable) l1_link;
319 /* Entry on the L1 Least Recently Used list */
320 TAILQ_ENTRY(l1_ttable) l1_lru;
322 /* Track how many domains are allocated from this L1 */
323 volatile u_int l1_domain_use_count;
326 * A free-list of domain numbers for this L1.
327 * We avoid using ffs() and a bitmap to track domains since ffs()
330 u_int8_t l1_domain_first;
331 u_int8_t l1_domain_free[PMAP_DOMAINS];
333 /* Physical address of this L1 page table */
334 vm_paddr_t l1_physaddr;
336 /* KVA of this L1 page table */
341 * Convert a virtual address into its L1 table index. That is, the
342 * index used to locate the L2 descriptor table pointer in an L1 table.
343 * This is basically used to index l1->l1_kva[].
345 * Each L2 descriptor table represents 1MB of VA space.
347 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
350 * L1 Page Tables are tracked using a Least Recently Used list.
351 * - New L1s are allocated from the HEAD.
352 * - Freed L1s are added to the TAIl.
353 * - Recently accessed L1s (where an 'access' is some change to one of
354 * the userland pmaps which owns this L1) are moved to the TAIL.
356 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
358 * A list of all L1 tables
360 static SLIST_HEAD(, l1_ttable) l1_list;
361 static struct mtx l1_lru_lock;
364 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
366 * This is normally 16MB worth L2 page descriptors for any given pmap.
367 * Reference counts are maintained for L2 descriptors so they can be
371 /* The number of L2 page descriptors allocated to this l2_dtable */
374 /* List of L2 page descriptors */
376 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
377 vm_paddr_t l2b_phys; /* Physical address of same */
378 u_short l2b_l1idx; /* This L2 table's L1 index */
379 u_short l2b_occupancy; /* How many active descriptors */
380 } l2_bucket[L2_BUCKET_SIZE];
383 /* pmap_kenter_internal flags */
384 #define KENTER_CACHE 0x1
385 #define KENTER_DEVICE 0x2
386 #define KENTER_USER 0x4
389 * Given an L1 table index, calculate the corresponding l2_dtable index
390 * and bucket index within the l2_dtable.
392 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
394 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
397 * Given a virtual address, this macro returns the
398 * virtual address required to drop into the next L2 bucket.
400 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
403 * We try to map the page tables write-through, if possible. However, not
404 * all CPUs have a write-through cache mode, so on those we have to sync
405 * the cache when we frob page tables.
407 * We try to evaluate this at compile time, if possible. However, it's
408 * not always possible to do that, hence this run-time var.
410 int pmap_needs_pte_sync;
413 * Macro to determine if a mapping might be resident in the
414 * instruction cache and/or TLB
416 #define PTE_BEEN_EXECD(pte) (L2_S_EXECUTABLE(pte) && L2_S_REFERENCED(pte))
419 * Macro to determine if a mapping might be resident in the
420 * data cache and/or TLB
422 #define PTE_BEEN_REFD(pte) (L2_S_REFERENCED(pte))
424 #ifndef PMAP_SHPGPERPROC
425 #define PMAP_SHPGPERPROC 200
428 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
429 curproc->p_vmspace->vm_map.pmap == (pm))
432 * Data for the pv entry allocation mechanism
434 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
435 static int pv_entry_count, pv_entry_max, pv_entry_high_water;
436 static struct md_page *pv_table;
437 static int shpgperproc = PMAP_SHPGPERPROC;
439 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
440 int pv_maxchunks; /* How many chunks we have KVA for */
441 vm_offset_t pv_vafree; /* Freelist stored in the PTE */
443 static __inline struct pv_chunk *
444 pv_to_chunk(pv_entry_t pv)
447 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
450 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
452 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
453 CTASSERT(_NPCM == 8);
454 CTASSERT(_NPCPV == 252);
456 #define PC_FREE0_6 0xfffffffful /* Free values for index 0 through 6 */
457 #define PC_FREE7 0x0ffffffful /* Free values for index 7 */
459 static const uint32_t pc_freemask[_NPCM] = {
460 PC_FREE0_6, PC_FREE0_6, PC_FREE0_6,
461 PC_FREE0_6, PC_FREE0_6, PC_FREE0_6,
465 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
467 /* Superpages utilization enabled = 1 / disabled = 0 */
468 static int sp_enabled = 0;
469 SYSCTL_INT(_vm_pmap, OID_AUTO, sp_enabled, CTLFLAG_RDTUN, &sp_enabled, 0,
470 "Are large page mappings enabled?");
472 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
473 "Current number of pv entries");
476 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
478 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
479 "Current number of pv entry chunks");
480 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
481 "Current number of pv entry chunks allocated");
482 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
483 "Current number of pv entry chunks frees");
484 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
485 "Number of times tried to get a chunk page but failed.");
487 static long pv_entry_frees, pv_entry_allocs;
488 static int pv_entry_spare;
490 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
491 "Current number of pv entry frees");
492 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
493 "Current number of pv entry allocs");
494 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
495 "Current number of spare pv entries");
499 static uma_zone_t l2table_zone;
500 static vm_offset_t pmap_kernel_l2dtable_kva;
501 static vm_offset_t pmap_kernel_l2ptp_kva;
502 static vm_paddr_t pmap_kernel_l2ptp_phys;
503 static struct rwlock pvh_global_lock;
505 int l1_mem_types[] = {
507 ARM_L1S_DEVICE_NOSHARE,
508 ARM_L1S_DEVICE_SHARE,
509 ARM_L1S_NRML_NOCACHE,
510 ARM_L1S_NRML_IWT_OWT,
511 ARM_L1S_NRML_IWB_OWB,
512 ARM_L1S_NRML_IWBA_OWBA
515 int l2l_mem_types[] = {
517 ARM_L2L_DEVICE_NOSHARE,
518 ARM_L2L_DEVICE_SHARE,
519 ARM_L2L_NRML_NOCACHE,
520 ARM_L2L_NRML_IWT_OWT,
521 ARM_L2L_NRML_IWB_OWB,
522 ARM_L2L_NRML_IWBA_OWBA
525 int l2s_mem_types[] = {
527 ARM_L2S_DEVICE_NOSHARE,
528 ARM_L2S_DEVICE_SHARE,
529 ARM_L2S_NRML_NOCACHE,
530 ARM_L2S_NRML_IWT_OWT,
531 ARM_L2S_NRML_IWB_OWB,
532 ARM_L2S_NRML_IWBA_OWBA
536 * This list exists for the benefit of pmap_map_chunk(). It keeps track
537 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
538 * find them as necessary.
540 * Note that the data on this list MUST remain valid after initarm() returns,
541 * as pmap_bootstrap() uses it to contruct L2 table metadata.
543 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
546 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
551 l1->l1_domain_use_count = 0;
552 l1->l1_domain_first = 0;
554 for (i = 0; i < PMAP_DOMAINS; i++)
555 l1->l1_domain_free[i] = i + 1;
558 * Copy the kernel's L1 entries to each new L1.
560 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
561 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
563 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
564 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
565 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
566 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
570 kernel_pt_lookup(vm_paddr_t pa)
574 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
582 pmap_pte_init_mmu_v6(void)
585 if (PTE_PAGETABLE >= 3)
586 pmap_needs_pte_sync = 1;
587 pte_l1_s_cache_mode = l1_mem_types[PTE_CACHE];
588 pte_l2_l_cache_mode = l2l_mem_types[PTE_CACHE];
589 pte_l2_s_cache_mode = l2s_mem_types[PTE_CACHE];
591 pte_l1_s_cache_mode_pt = l1_mem_types[PTE_PAGETABLE];
592 pte_l2_l_cache_mode_pt = l2l_mem_types[PTE_PAGETABLE];
593 pte_l2_s_cache_mode_pt = l2s_mem_types[PTE_PAGETABLE];
598 * Allocate an L1 translation table for the specified pmap.
599 * This is called at pmap creation time.
602 pmap_alloc_l1(pmap_t pmap)
604 struct l1_ttable *l1;
608 * Remove the L1 at the head of the LRU list
610 mtx_lock(&l1_lru_lock);
611 l1 = TAILQ_FIRST(&l1_lru_list);
612 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
615 * Pick the first available domain number, and update
616 * the link to the next number.
618 domain = l1->l1_domain_first;
619 l1->l1_domain_first = l1->l1_domain_free[domain];
622 * If there are still free domain numbers in this L1,
623 * put it back on the TAIL of the LRU list.
625 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
626 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
628 mtx_unlock(&l1_lru_lock);
631 * Fix up the relevant bits in the pmap structure
634 pmap->pm_domain = domain + 1;
638 * Free an L1 translation table.
639 * This is called at pmap destruction time.
642 pmap_free_l1(pmap_t pmap)
644 struct l1_ttable *l1 = pmap->pm_l1;
646 mtx_lock(&l1_lru_lock);
649 * If this L1 is currently on the LRU list, remove it.
651 if (l1->l1_domain_use_count < PMAP_DOMAINS)
652 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
655 * Free up the domain number which was allocated to the pmap
657 l1->l1_domain_free[pmap->pm_domain - 1] = l1->l1_domain_first;
658 l1->l1_domain_first = pmap->pm_domain - 1;
659 l1->l1_domain_use_count--;
662 * The L1 now must have at least 1 free domain, so add
663 * it back to the LRU list. If the use count is zero,
664 * put it at the head of the list, otherwise it goes
667 if (l1->l1_domain_use_count == 0) {
668 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
670 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
672 mtx_unlock(&l1_lru_lock);
676 * Returns a pointer to the L2 bucket associated with the specified pmap
677 * and VA, or NULL if no L2 bucket exists for the address.
679 static PMAP_INLINE struct l2_bucket *
680 pmap_get_l2_bucket(pmap_t pmap, vm_offset_t va)
682 struct l2_dtable *l2;
683 struct l2_bucket *l2b;
688 if ((l2 = pmap->pm_l2[L2_IDX(l1idx)]) == NULL ||
689 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
696 * Returns a pointer to the L2 bucket associated with the specified pmap
699 * If no L2 bucket exists, perform the necessary allocations to put an L2
700 * bucket/page table in place.
702 * Note that if a new L2 bucket/page was allocated, the caller *must*
703 * increment the bucket occupancy counter appropriately *before*
704 * releasing the pmap's lock to ensure no other thread or cpu deallocates
705 * the bucket/page in the meantime.
707 static struct l2_bucket *
708 pmap_alloc_l2_bucket(pmap_t pmap, vm_offset_t va)
710 struct l2_dtable *l2;
711 struct l2_bucket *l2b;
716 PMAP_ASSERT_LOCKED(pmap);
717 rw_assert(&pvh_global_lock, RA_WLOCKED);
718 if ((l2 = pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
720 * No mapping at this address, as there is
721 * no entry in the L1 table.
722 * Need to allocate a new l2_dtable.
725 rw_wunlock(&pvh_global_lock);
726 if ((l2 = uma_zalloc(l2table_zone, M_NOWAIT)) == NULL) {
727 rw_wlock(&pvh_global_lock);
731 rw_wlock(&pvh_global_lock);
733 if (pmap->pm_l2[L2_IDX(l1idx)] != NULL) {
735 * Someone already allocated the l2_dtable while
736 * we were doing the same.
738 uma_zfree(l2table_zone, l2);
739 l2 = pmap->pm_l2[L2_IDX(l1idx)];
741 bzero(l2, sizeof(*l2));
743 * Link it into the parent pmap
745 pmap->pm_l2[L2_IDX(l1idx)] = l2;
749 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
752 * Fetch pointer to the L2 page table associated with the address.
754 if (l2b->l2b_kva == NULL) {
758 * No L2 page table has been allocated. Chances are, this
759 * is because we just allocated the l2_dtable, above.
762 rw_wunlock(&pvh_global_lock);
763 ptep = uma_zalloc(l2zone, M_NOWAIT);
764 rw_wlock(&pvh_global_lock);
766 if (l2b->l2b_kva != 0) {
767 /* We lost the race. */
768 uma_zfree(l2zone, ptep);
771 l2b->l2b_phys = vtophys(ptep);
774 * Oops, no more L2 page tables available at this
775 * time. We may need to deallocate the l2_dtable
776 * if we allocated a new one above.
778 if (l2->l2_occupancy == 0) {
779 pmap->pm_l2[L2_IDX(l1idx)] = NULL;
780 uma_zfree(l2table_zone, l2);
787 l2b->l2b_l1idx = l1idx;
793 static PMAP_INLINE void
794 pmap_free_l2_ptp(pt_entry_t *l2)
796 uma_zfree(l2zone, l2);
799 * One or more mappings in the specified L2 descriptor table have just been
802 * Garbage collect the metadata and descriptor table itself if necessary.
804 * The pmap lock must be acquired when this is called (not necessary
805 * for the kernel pmap).
808 pmap_free_l2_bucket(pmap_t pmap, struct l2_bucket *l2b, u_int count)
810 struct l2_dtable *l2;
811 pd_entry_t *pl1pd, l1pd;
817 * Update the bucket's reference count according to how many
818 * PTEs the caller has just invalidated.
820 l2b->l2b_occupancy -= count;
825 * Level 2 page tables allocated to the kernel pmap are never freed
826 * as that would require checking all Level 1 page tables and
827 * removing any references to the Level 2 page table. See also the
828 * comment elsewhere about never freeing bootstrap L2 descriptors.
830 * We make do with just invalidating the mapping in the L2 table.
832 * This isn't really a big deal in practice and, in fact, leads
833 * to a performance win over time as we don't need to continually
836 if (l2b->l2b_occupancy > 0 || pmap == pmap_kernel())
840 * There are no more valid mappings in this level 2 page table.
841 * Go ahead and NULL-out the pointer in the bucket, then
842 * free the page table.
844 l1idx = l2b->l2b_l1idx;
848 pl1pd = &pmap->pm_l1->l1_kva[l1idx];
851 * If the L1 slot matches the pmap's domain
852 * number, then invalidate it.
854 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
855 if (l1pd == (L1_C_DOM(pmap->pm_domain) | L1_TYPE_C)) {
858 cpu_tlb_flushD_SE((vm_offset_t)ptep);
863 * Release the L2 descriptor table back to the pool cache.
865 pmap_free_l2_ptp(ptep);
868 * Update the reference count in the associated l2_dtable
870 l2 = pmap->pm_l2[L2_IDX(l1idx)];
871 if (--l2->l2_occupancy > 0)
875 * There are no more valid mappings in any of the Level 1
876 * slots managed by this l2_dtable. Go ahead and NULL-out
877 * the pointer in the parent pmap and free the l2_dtable.
879 pmap->pm_l2[L2_IDX(l1idx)] = NULL;
880 uma_zfree(l2table_zone, l2);
884 * Pool cache constructors for L2 descriptor tables, metadata and pmap
888 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
890 struct l2_bucket *l2b;
891 pt_entry_t *ptep, pte;
892 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
895 * The mappings for these page tables were initially made using
896 * pmap_kenter() by the pool subsystem. Therefore, the cache-
897 * mode will not be right for page table mappings. To avoid
898 * polluting the pmap_kenter() code with a special case for
899 * page tables, we simply fix up the cache-mode here if it's not
902 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
903 ptep = &l2b->l2b_kva[l2pte_index(va)];
906 cpu_idcache_wbinv_range(va, PAGE_SIZE);
907 pmap_l2cache_wbinv_range(va, pte & L2_S_FRAME, PAGE_SIZE);
908 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
910 * Page tables must have the cache-mode set to
913 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
915 cpu_tlb_flushD_SE(va);
919 memset(mem, 0, L2_TABLE_SIZE_REAL);
924 * Modify pte bits for all ptes corresponding to the given physical address.
925 * We use `maskbits' rather than `clearbits' because we're always passing
926 * constants and the latter would require an extra inversion at run-time.
929 pmap_clearbit(struct vm_page *m, u_int maskbits)
931 struct l2_bucket *l2b;
932 struct pv_entry *pv, *pve, *next_pv;
935 pt_entry_t *ptep, npte, opte;
941 rw_wlock(&pvh_global_lock);
942 if ((m->flags & PG_FICTITIOUS) != 0)
945 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
946 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
950 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
951 KASSERT((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO,
952 ("pmap_clearbit: valid section mapping expected"));
953 if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_WRITE))
954 (void)pmap_demote_section(pmap, va);
955 else if ((maskbits & PVF_REF) && L1_S_REFERENCED(*pl1pd)) {
956 if (pmap_demote_section(pmap, va)) {
957 if ((pv->pv_flags & PVF_WIRED) == 0) {
959 * Remove the mapping to a single page
960 * so that a subsequent access may
961 * repromote. Since the underlying
962 * l2_bucket is fully populated, this
963 * removal never frees an entire
966 va += (VM_PAGE_TO_PHYS(m) &
968 l2b = pmap_get_l2_bucket(pmap, va);
970 ("pmap_clearbit: no l2 bucket for "
971 "va 0x%#x, pmap 0x%p", va, pmap));
972 ptep = &l2b->l2b_kva[l2pte_index(va)];
975 pmap_free_l2_bucket(pmap, l2b, 1);
976 pve = pmap_remove_pv(m, pmap, va);
977 KASSERT(pve != NULL, ("pmap_clearbit: "
978 "no PV entry for managed mapping"));
979 pmap_free_pv_entry(pmap, pve);
983 } else if ((maskbits & PVF_MOD) && L1_S_WRITABLE(*pl1pd)) {
984 if (pmap_demote_section(pmap, va)) {
985 if ((pv->pv_flags & PVF_WIRED) == 0) {
987 * Write protect the mapping to a
988 * single page so that a subsequent
989 * write access may repromote.
991 va += (VM_PAGE_TO_PHYS(m) &
993 l2b = pmap_get_l2_bucket(pmap, va);
995 ("pmap_clearbit: no l2 bucket for "
996 "va 0x%#x, pmap 0x%p", va, pmap));
997 ptep = &l2b->l2b_kva[l2pte_index(va)];
998 if ((*ptep & L2_S_PROTO) != 0) {
999 pve = pmap_find_pv(&m->md,
1001 KASSERT(pve != NULL,
1002 ("pmap_clearbit: no PV "
1003 "entry for managed mapping"));
1004 pve->pv_flags &= ~PVF_WRITE;
1015 if (TAILQ_EMPTY(&m->md.pv_list)) {
1016 rw_wunlock(&pvh_global_lock);
1021 * Loop over all current mappings setting/clearing as appropos
1023 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
1026 oflags = pv->pv_flags;
1027 pv->pv_flags &= ~maskbits;
1031 l2b = pmap_get_l2_bucket(pmap, va);
1032 KASSERT(l2b != NULL, ("pmap_clearbit: no l2 bucket for "
1033 "va 0x%#x, pmap 0x%p", va, pmap));
1035 ptep = &l2b->l2b_kva[l2pte_index(va)];
1036 npte = opte = *ptep;
1038 if (maskbits & (PVF_WRITE | PVF_MOD)) {
1039 /* make the pte read only */
1043 if (maskbits & PVF_REF) {
1045 * Clear referenced flag in PTE so that we
1046 * will take a flag fault the next time the mapping
1052 CTR4(KTR_PMAP,"clearbit: pmap:%p bits:%x pte:%x->%x",
1053 pmap, maskbits, opte, npte);
1058 /* Flush the TLB entry if a current pmap. */
1059 if (PTE_BEEN_EXECD(opte))
1060 cpu_tlb_flushID_SE(pv->pv_va);
1061 else if (PTE_BEEN_REFD(opte))
1062 cpu_tlb_flushD_SE(pv->pv_va);
1070 if (maskbits & PVF_WRITE)
1071 vm_page_aflag_clear(m, PGA_WRITEABLE);
1072 rw_wunlock(&pvh_global_lock);
1077 * main pv_entry manipulation functions:
1078 * pmap_enter_pv: enter a mapping onto a vm_page list
1079 * pmap_remove_pv: remove a mappiing from a vm_page list
1081 * NOTE: pmap_enter_pv expects to lock the pvh itself
1082 * pmap_remove_pv expects the caller to lock the pvh before calling
1086 * pmap_enter_pv: enter a mapping onto a vm_page's PV list
1088 * => caller should hold the proper lock on pvh_global_lock
1089 * => caller should have pmap locked
1090 * => we will (someday) gain the lock on the vm_page's PV list
1091 * => caller should adjust ptp's wire_count before calling
1092 * => caller should not adjust pmap's wire_count
1095 pmap_enter_pv(struct vm_page *m, struct pv_entry *pve, pmap_t pmap,
1096 vm_offset_t va, u_int flags)
1099 rw_assert(&pvh_global_lock, RA_WLOCKED);
1101 PMAP_ASSERT_LOCKED(pmap);
1103 pve->pv_flags = flags;
1105 TAILQ_INSERT_HEAD(&m->md.pv_list, pve, pv_list);
1106 if (pve->pv_flags & PVF_WIRED)
1107 ++pmap->pm_stats.wired_count;
1112 * pmap_find_pv: Find a pv entry
1114 * => caller should hold lock on vm_page
1116 static PMAP_INLINE struct pv_entry *
1117 pmap_find_pv(struct md_page *md, pmap_t pmap, vm_offset_t va)
1119 struct pv_entry *pv;
1121 rw_assert(&pvh_global_lock, RA_WLOCKED);
1122 TAILQ_FOREACH(pv, &md->pv_list, pv_list)
1123 if (pmap == PV_PMAP(pv) && va == pv->pv_va)
1130 * vector_page_setprot:
1132 * Manipulate the protection of the vector page.
1135 vector_page_setprot(int prot)
1137 struct l2_bucket *l2b;
1140 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
1142 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1144 * Set referenced flag.
1145 * Vectors' page is always desired
1146 * to be allowed to reside in TLB.
1150 pmap_set_prot(ptep, prot|VM_PROT_EXECUTE, 0);
1152 cpu_tlb_flushID_SE(vector_page);
1157 pmap_set_prot(pt_entry_t *ptep, vm_prot_t prot, uint8_t user)
1160 *ptep &= ~(L2_S_PROT_MASK | L2_XN);
1162 if (!(prot & VM_PROT_EXECUTE))
1165 /* Set defaults first - kernel read access */
1167 *ptep |= L2_S_PROT_R;
1168 /* Now tune APs as desired */
1170 *ptep |= L2_S_PROT_U;
1172 if (prot & VM_PROT_WRITE)
1177 * pmap_remove_pv: try to remove a mapping from a pv_list
1179 * => caller should hold proper lock on pmap_main_lock
1180 * => pmap should be locked
1181 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1182 * => caller should adjust ptp's wire_count and free PTP if needed
1183 * => caller should NOT adjust pmap's wire_count
1184 * => we return the removed pve
1186 static struct pv_entry *
1187 pmap_remove_pv(struct vm_page *m, pmap_t pmap, vm_offset_t va)
1189 struct pv_entry *pve;
1191 rw_assert(&pvh_global_lock, RA_WLOCKED);
1192 PMAP_ASSERT_LOCKED(pmap);
1194 pve = pmap_find_pv(&m->md, pmap, va); /* find corresponding pve */
1196 TAILQ_REMOVE(&m->md.pv_list, pve, pv_list);
1197 if (pve->pv_flags & PVF_WIRED)
1198 --pmap->pm_stats.wired_count;
1200 if (TAILQ_EMPTY(&m->md.pv_list))
1201 vm_page_aflag_clear(m, PGA_WRITEABLE);
1203 return(pve); /* return removed pve */
1208 * pmap_modify_pv: Update pv flags
1210 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1211 * => caller should NOT adjust pmap's wire_count
1212 * => we return the old flags
1214 * Modify a physical-virtual mapping in the pv table
1217 pmap_modify_pv(struct vm_page *m, pmap_t pmap, vm_offset_t va,
1218 u_int clr_mask, u_int set_mask)
1220 struct pv_entry *npv;
1221 u_int flags, oflags;
1223 PMAP_ASSERT_LOCKED(pmap);
1224 rw_assert(&pvh_global_lock, RA_WLOCKED);
1225 if ((npv = pmap_find_pv(&m->md, pmap, va)) == NULL)
1229 * There is at least one VA mapping this page.
1231 oflags = npv->pv_flags;
1232 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1234 if ((flags ^ oflags) & PVF_WIRED) {
1235 if (flags & PVF_WIRED)
1236 ++pmap->pm_stats.wired_count;
1238 --pmap->pm_stats.wired_count;
1244 /* Function to set the debug level of the pmap code */
1247 pmap_debug(int level)
1249 pmap_debug_level = level;
1250 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1252 #endif /* PMAP_DEBUG */
1255 pmap_pinit0(struct pmap *pmap)
1257 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1259 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1260 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1261 PMAP_LOCK_INIT(pmap);
1262 TAILQ_INIT(&pmap->pm_pvchunk);
1266 * Initialize a vm_page's machine-dependent fields.
1269 pmap_page_init(vm_page_t m)
1272 TAILQ_INIT(&m->md.pv_list);
1273 m->md.pv_memattr = VM_MEMATTR_DEFAULT;
1277 pmap_ptelist_alloc(vm_offset_t *head)
1284 return (va); /* Out of memory */
1287 if ((*head & L2_TYPE_MASK) != L2_TYPE_INV)
1288 panic("%s: va is not L2_TYPE_INV!", __func__);
1294 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
1298 if ((va & L2_TYPE_MASK) != L2_TYPE_INV)
1299 panic("%s: freeing va that is not L2_TYPE INV!", __func__);
1301 *pte = *head; /* virtual! L2_TYPE is L2_TYPE_INV though */
1306 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
1312 for (i = npages - 1; i >= 0; i--) {
1313 va = (vm_offset_t)base + i * PAGE_SIZE;
1314 pmap_ptelist_free(head, va);
1319 * Initialize the pmap module.
1320 * Called by vm_init, to initialize any structures that the pmap
1321 * system needs to map virtual memory.
1329 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1330 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1331 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), NULL,
1332 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1335 * Are large page mappings supported and enabled?
1337 TUNABLE_INT_FETCH("vm.pmap.sp_enabled", &sp_enabled);
1339 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1340 ("pmap_init: can't assign to pagesizes[1]"));
1341 pagesizes[1] = NBPDR;
1345 * Calculate the size of the pv head table for superpages.
1346 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1348 pv_npg = trunc_1mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
1349 PAGE_SIZE) / NBPDR + 1;
1352 * Allocate memory for the pv head table for superpages.
1354 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1356 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1358 for (i = 0; i < pv_npg; i++)
1359 TAILQ_INIT(&pv_table[i].pv_list);
1362 * Initialize the address space for the pv chunks.
1365 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1366 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1367 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1368 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1369 pv_entry_high_water = 9 * (pv_entry_max / 10);
1371 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1372 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1374 if (pv_chunkbase == NULL)
1375 panic("pmap_init: not enough kvm for pv chunks");
1377 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1380 * Now it is safe to enable pv_table recording.
1382 PDEBUG(1, printf("pmap_init: done!\n"));
1385 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1386 "Max number of PV entries");
1387 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1388 "Page share factor per proc");
1390 static SYSCTL_NODE(_vm_pmap, OID_AUTO, section, CTLFLAG_RD, 0,
1391 "1MB page mapping counters");
1393 static u_long pmap_section_demotions;
1394 SYSCTL_ULONG(_vm_pmap_section, OID_AUTO, demotions, CTLFLAG_RD,
1395 &pmap_section_demotions, 0, "1MB page demotions");
1397 static u_long pmap_section_mappings;
1398 SYSCTL_ULONG(_vm_pmap_section, OID_AUTO, mappings, CTLFLAG_RD,
1399 &pmap_section_mappings, 0, "1MB page mappings");
1401 static u_long pmap_section_p_failures;
1402 SYSCTL_ULONG(_vm_pmap_section, OID_AUTO, p_failures, CTLFLAG_RD,
1403 &pmap_section_p_failures, 0, "1MB page promotion failures");
1405 static u_long pmap_section_promotions;
1406 SYSCTL_ULONG(_vm_pmap_section, OID_AUTO, promotions, CTLFLAG_RD,
1407 &pmap_section_promotions, 0, "1MB page promotions");
1410 pmap_fault_fixup(pmap_t pmap, vm_offset_t va, vm_prot_t ftype, int user)
1412 struct l2_dtable *l2;
1413 struct l2_bucket *l2b;
1414 pd_entry_t *pl1pd, l1pd;
1415 pt_entry_t *ptep, pte;
1421 rw_wlock(&pvh_global_lock);
1424 * Check and possibly fix-up L1 section mapping
1425 * only when superpage mappings are enabled to speed up.
1428 pl1pd = &pmap->pm_l1->l1_kva[l1idx];
1430 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) {
1431 /* Catch an access to the vectors section */
1432 if (l1idx == L1_IDX(vector_page))
1435 * Stay away from the kernel mappings.
1436 * None of them should fault from L1 entry.
1438 if (pmap == pmap_kernel())
1441 * Catch a forbidden userland access
1443 if (user && !(l1pd & L1_S_PROT_U))
1446 * Superpage is always either mapped read only
1447 * or it is modified and permitted to be written
1448 * by default. Therefore, process only reference
1449 * flag fault and demote page in case of write fault.
1451 if ((ftype & VM_PROT_WRITE) && !L1_S_WRITABLE(l1pd) &&
1452 L1_S_REFERENCED(l1pd)) {
1453 (void)pmap_demote_section(pmap, va);
1455 } else if (!L1_S_REFERENCED(l1pd)) {
1456 /* Mark the page "referenced" */
1457 *pl1pd = l1pd | L1_S_REF;
1459 goto l1_section_out;
1465 * If there is no l2_dtable for this address, then the process
1466 * has no business accessing it.
1468 * Note: This will catch userland processes trying to access
1471 l2 = pmap->pm_l2[L2_IDX(l1idx)];
1476 * Likewise if there is no L2 descriptor table
1478 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1479 if (l2b->l2b_kva == NULL)
1483 * Check the PTE itself.
1485 ptep = &l2b->l2b_kva[l2pte_index(va)];
1491 * Catch a userland access to the vector page mapped at 0x0
1493 if (user && !(pte & L2_S_PROT_U))
1495 if (va == vector_page)
1499 CTR5(KTR_PMAP, "pmap_fault_fix: pmap:%p va:%x pte:0x%x ftype:%x user:%x",
1500 pmap, va, pte, ftype, user);
1501 if ((ftype & VM_PROT_WRITE) && !(L2_S_WRITABLE(pte)) &&
1502 L2_S_REFERENCED(pte)) {
1504 * This looks like a good candidate for "page modified"
1507 struct pv_entry *pv;
1510 /* Extract the physical address of the page */
1511 if ((m = PHYS_TO_VM_PAGE(pa)) == NULL) {
1514 /* Get the current flags for this page. */
1516 pv = pmap_find_pv(&m->md, pmap, va);
1522 * Do the flags say this page is writable? If not then it
1523 * is a genuine write fault. If yes then the write fault is
1524 * our fault as we did not reflect the write access in the
1525 * PTE. Now we know a write has occurred we can correct this
1526 * and also set the modified bit
1528 if ((pv->pv_flags & PVF_WRITE) == 0) {
1534 /* Re-enable write permissions for the page */
1535 *ptep = (pte & ~L2_APX);
1538 CTR1(KTR_PMAP, "pmap_fault_fix: new pte:0x%x", *ptep);
1539 } else if (!L2_S_REFERENCED(pte)) {
1541 * This looks like a good candidate for "page referenced"
1544 struct pv_entry *pv;
1547 /* Extract the physical address of the page */
1548 if ((m = PHYS_TO_VM_PAGE(pa)) == NULL)
1550 /* Get the current flags for this page. */
1551 pv = pmap_find_pv(&m->md, pmap, va);
1555 vm_page_aflag_set(m, PGA_REFERENCED);
1557 /* Mark the page "referenced" */
1558 *ptep = pte | L2_S_REF;
1561 CTR1(KTR_PMAP, "pmap_fault_fix: new pte:0x%x", *ptep);
1565 * We know there is a valid mapping here, so simply
1566 * fix up the L1 if necessary.
1568 pl1pd = &pmap->pm_l1->l1_kva[l1idx];
1569 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | L1_C_PROTO;
1570 if (*pl1pd != l1pd) {
1578 * If 'rv == 0' at this point, it generally indicates that there is a
1579 * stale TLB entry for the faulting address. This happens when two or
1580 * more processes are sharing an L1. Since we don't flush the TLB on
1581 * a context switch between such processes, we can take domain faults
1582 * for mappings which exist at the same VA in both processes. EVEN IF
1583 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
1586 * This is extremely likely to happen if pmap_enter() updated the L1
1587 * entry for a recently entered mapping. In this case, the TLB is
1588 * flushed for the new mapping, but there may still be TLB entries for
1589 * other mappings belonging to other processes in the 1MB range
1590 * covered by the L1 entry.
1592 * Since 'rv == 0', we know that the L1 already contains the correct
1593 * value, so the fault must be due to a stale TLB entry.
1595 * Since we always need to flush the TLB anyway in the case where we
1596 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
1597 * stale TLB entries dynamically.
1599 * However, the above condition can ONLY happen if the current L1 is
1600 * being shared. If it happens when the L1 is unshared, it indicates
1601 * that other parts of the pmap are not doing their job WRT managing
1604 if (rv == 0 && pmap->pm_l1->l1_domain_use_count == 1) {
1605 printf("fixup: pmap %p, va 0x%08x, ftype %d - nothing to do!\n",
1607 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
1608 l2, l2b, ptep, pl1pd);
1609 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
1610 pte, l1pd, last_fault_code);
1618 cpu_tlb_flushID_SE(va);
1624 rw_wunlock(&pvh_global_lock);
1632 struct l2_bucket *l2b;
1633 struct l1_ttable *l1;
1635 pt_entry_t *ptep, pte;
1636 vm_offset_t va, eva;
1639 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
1641 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
1643 for (loop = 0; loop < needed; loop++, l1++) {
1644 /* Allocate a L1 page table */
1645 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
1646 0xffffffff, L1_TABLE_SIZE, 0);
1649 panic("Cannot allocate L1 KVM");
1651 eva = va + L1_TABLE_SIZE;
1652 pl1pt = (pd_entry_t *)va;
1655 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1656 ptep = &l2b->l2b_kva[l2pte_index(va)];
1658 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1661 cpu_tlb_flushID_SE(va);
1665 pmap_init_l1(l1, pl1pt);
1668 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
1674 * This is used to stuff certain critical values into the PCB where they
1675 * can be accessed quickly from cpu_switch() et al.
1678 pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb)
1680 struct l2_bucket *l2b;
1682 pcb->pcb_pagedir = pmap->pm_l1->l1_physaddr;
1683 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
1684 (DOMAIN_CLIENT << (pmap->pm_domain * 2));
1686 if (vector_page < KERNBASE) {
1687 pcb->pcb_pl1vec = &pmap->pm_l1->l1_kva[L1_IDX(vector_page)];
1688 l2b = pmap_get_l2_bucket(pmap, vector_page);
1689 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
1690 L1_C_DOM(pmap->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
1692 pcb->pcb_pl1vec = NULL;
1696 pmap_activate(struct thread *td)
1701 pmap = vmspace_pmap(td->td_proc->p_vmspace);
1705 pmap_set_pcb_pagedir(pmap, pcb);
1707 if (td == curthread) {
1708 u_int cur_dacr, cur_ttb;
1710 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
1711 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
1713 cur_ttb &= ~(L1_TABLE_SIZE - 1);
1715 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
1716 cur_dacr == pcb->pcb_dacr) {
1718 * No need to switch address spaces.
1726 * We MUST, I repeat, MUST fix up the L1 entry corresponding
1727 * to 'vector_page' in the incoming L1 table before switching
1728 * to it otherwise subsequent interrupts/exceptions (including
1729 * domain faults!) will jump into hyperspace.
1731 if (pcb->pcb_pl1vec) {
1732 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
1735 cpu_domains(pcb->pcb_dacr);
1736 cpu_setttb(pcb->pcb_pagedir);
1742 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
1744 pd_entry_t *pdep, pde;
1745 pt_entry_t *ptep, pte;
1750 * Make sure the descriptor itself has the correct cache mode
1752 pdep = &kl1[L1_IDX(va)];
1755 if (l1pte_section_p(pde)) {
1756 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
1757 *pdep = (pde & ~L1_S_CACHE_MASK) |
1758 pte_l1_s_cache_mode_pt;
1763 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
1764 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
1766 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
1768 ptep = &ptep[l2pte_index(va)];
1770 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1771 *ptep = (pte & ~L2_S_CACHE_MASK) |
1772 pte_l2_s_cache_mode_pt;
1782 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
1785 vm_offset_t va = *availp;
1786 struct l2_bucket *l2b;
1789 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1791 panic("pmap_alloc_specials: no l2b for 0x%x", va);
1793 *ptep = &l2b->l2b_kva[l2pte_index(va)];
1797 *availp = va + (PAGE_SIZE * pages);
1801 * Bootstrap the system enough to run with virtual memory.
1803 * On the arm this is called after mapping has already been enabled
1804 * and just syncs the pmap module with what has already been done.
1805 * [We can't call it easily with mapping off since the kernel is not
1806 * mapped with PA == VA, hence we would have to relocate every address
1807 * from the linked base (virtual) address "KERNBASE" to the actual
1808 * (physical) address starting relative to 0]
1810 #define PMAP_STATIC_L2_SIZE 16
1813 pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt)
1815 static struct l1_ttable static_l1;
1816 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
1817 struct l1_ttable *l1 = &static_l1;
1818 struct l2_dtable *l2;
1819 struct l2_bucket *l2b;
1820 struct czpages *czp;
1822 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
1827 int i, l1idx, l2idx, l2next = 0;
1829 PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n",
1830 firstaddr, vm_max_kernel_address));
1832 virtual_avail = firstaddr;
1833 kernel_pmap->pm_l1 = l1;
1834 kernel_l1pa = l1pt->pv_pa;
1837 * Scan the L1 translation table created by initarm() and create
1838 * the required metadata for all valid mappings found in it.
1840 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
1841 pde = kernel_l1pt[l1idx];
1844 * We're only interested in Coarse mappings.
1845 * pmap_extract() can deal with section mappings without
1846 * recourse to checking L2 metadata.
1848 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
1852 * Lookup the KVA of this L2 descriptor table
1854 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
1855 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
1858 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
1859 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
1863 * Fetch the associated L2 metadata structure.
1864 * Allocate a new one if necessary.
1866 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
1867 if (l2next == PMAP_STATIC_L2_SIZE)
1868 panic("pmap_bootstrap: out of static L2s");
1869 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
1870 &static_l2[l2next++];
1874 * One more L1 slot tracked...
1879 * Fill in the details of the L2 descriptor in the
1880 * appropriate bucket.
1882 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1883 l2b->l2b_kva = ptep;
1885 l2b->l2b_l1idx = l1idx;
1888 * Establish an initial occupancy count for this descriptor
1891 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1893 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
1894 l2b->l2b_occupancy++;
1899 * Make sure the descriptor itself has the correct cache mode.
1900 * If not, fix it, but whine about the problem. Port-meisters
1901 * should consider this a clue to fix up their initarm()
1904 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
1905 printf("pmap_bootstrap: WARNING! wrong cache mode for "
1906 "L2 pte @ %p\n", ptep);
1912 * Ensure the primary (kernel) L1 has the correct cache mode for
1913 * a page table. Bitch if it is not correctly set.
1915 for (va = (vm_offset_t)kernel_l1pt;
1916 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
1917 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
1918 printf("pmap_bootstrap: WARNING! wrong cache mode for "
1919 "primary L1 @ 0x%x\n", va);
1922 cpu_dcache_wbinv_all();
1923 cpu_l2cache_wbinv_all();
1927 PMAP_LOCK_INIT(kernel_pmap);
1928 CPU_FILL(&kernel_pmap->pm_active);
1929 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
1930 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1933 * Initialize the global pv list lock.
1935 rw_init(&pvh_global_lock, "pmap pv global");
1938 * Reserve some special page table entries/VA space for temporary
1939 * mapping of pages that are being copied or zeroed.
1941 for (czp = cpu_czpages, i = 0; i < MAXCPU; ++i, ++czp) {
1942 mtx_init(&czp->lock, "czpages", NULL, MTX_DEF);
1943 pmap_alloc_specials(&virtual_avail, 1, &czp->srcva, &czp->srcptep);
1944 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)czp->srcptep);
1945 pmap_alloc_specials(&virtual_avail, 1, &czp->dstva, &czp->dstptep);
1946 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)czp->dstptep);
1949 size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) /
1951 pmap_alloc_specials(&virtual_avail,
1952 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
1953 &pmap_kernel_l2ptp_kva, NULL);
1955 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
1956 pmap_alloc_specials(&virtual_avail,
1957 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
1958 &pmap_kernel_l2dtable_kva, NULL);
1960 pmap_alloc_specials(&virtual_avail,
1961 1, (vm_offset_t*)&_tmppt, NULL);
1962 pmap_alloc_specials(&virtual_avail,
1963 MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL);
1964 SLIST_INIT(&l1_list);
1965 TAILQ_INIT(&l1_lru_list);
1966 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
1967 pmap_init_l1(l1, kernel_l1pt);
1968 cpu_dcache_wbinv_all();
1969 cpu_l2cache_wbinv_all();
1973 virtual_avail = round_page(virtual_avail);
1974 virtual_end = vm_max_kernel_address;
1975 kernel_vm_end = pmap_curmaxkvaddr;
1977 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
1980 /***************************************************
1981 * Pmap allocation/deallocation routines.
1982 ***************************************************/
1985 * Release any resources held by the given physical map.
1986 * Called when a pmap initialized by pmap_pinit is being released.
1987 * Should only be called if the map contains no valid mappings.
1990 pmap_release(pmap_t pmap)
1996 if (vector_page < KERNBASE) {
1997 struct pcb *curpcb = PCPU_GET(curpcb);
1998 pcb = thread0.td_pcb;
1999 if (pmap_is_current(pmap)) {
2001 * Frob the L1 entry corresponding to the vector
2002 * page so that it contains the kernel pmap's domain
2003 * number. This will ensure pmap_remove() does not
2004 * pull the current vector page out from under us.
2007 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2008 cpu_domains(pcb->pcb_dacr);
2009 cpu_setttb(pcb->pcb_pagedir);
2012 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2014 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2015 * since this process has no remaining mappings of its own.
2017 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2018 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2019 curpcb->pcb_dacr = pcb->pcb_dacr;
2020 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2025 dprintf("pmap_release()\n");
2031 * Helper function for pmap_grow_l2_bucket()
2034 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2036 struct l2_bucket *l2b;
2041 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2044 pa = VM_PAGE_TO_PHYS(m);
2049 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2051 ptep = &l2b->l2b_kva[l2pte_index(va)];
2052 *ptep = L2_S_PROTO | pa | cache_mode | L2_S_REF;
2053 pmap_set_prot(ptep, VM_PROT_READ | VM_PROT_WRITE, 0);
2055 cpu_tlb_flushD_SE(va);
2062 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2063 * used by pmap_growkernel().
2065 static __inline struct l2_bucket *
2066 pmap_grow_l2_bucket(pmap_t pmap, vm_offset_t va)
2068 struct l2_dtable *l2;
2069 struct l2_bucket *l2b;
2070 struct l1_ttable *l1;
2077 if ((l2 = pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2079 * No mapping at this address, as there is
2080 * no entry in the L1 table.
2081 * Need to allocate a new l2_dtable.
2083 nva = pmap_kernel_l2dtable_kva;
2084 if ((nva & PAGE_MASK) == 0) {
2086 * Need to allocate a backing page
2088 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2092 l2 = (struct l2_dtable *)nva;
2093 nva += sizeof(struct l2_dtable);
2095 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2098 * The new l2_dtable straddles a page boundary.
2099 * Map in another page to cover it.
2101 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2105 pmap_kernel_l2dtable_kva = nva;
2108 * Link it into the parent pmap
2110 pmap->pm_l2[L2_IDX(l1idx)] = l2;
2111 memset(l2, 0, sizeof(*l2));
2114 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2117 * Fetch pointer to the L2 page table associated with the address.
2119 if (l2b->l2b_kva == NULL) {
2123 * No L2 page table has been allocated. Chances are, this
2124 * is because we just allocated the l2_dtable, above.
2126 nva = pmap_kernel_l2ptp_kva;
2127 ptep = (pt_entry_t *)nva;
2128 if ((nva & PAGE_MASK) == 0) {
2130 * Need to allocate a backing page
2132 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2133 &pmap_kernel_l2ptp_phys))
2136 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2138 l2b->l2b_kva = ptep;
2139 l2b->l2b_l1idx = l1idx;
2140 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2142 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2143 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2146 /* Distribute new L1 entry to all other L1s */
2147 SLIST_FOREACH(l1, &l1_list, l1_link) {
2148 pl1pd = &l1->l1_kva[L1_IDX(va)];
2149 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2153 cpu_tlb_flushID_SE(va);
2161 * grow the number of kernel page table entries, if needed
2164 pmap_growkernel(vm_offset_t addr)
2166 pmap_t kpmap = pmap_kernel();
2168 if (addr <= pmap_curmaxkvaddr)
2169 return; /* we are OK */
2172 * whoops! we need to add kernel PTPs
2175 /* Map 1MB at a time */
2176 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2177 pmap_grow_l2_bucket(kpmap, pmap_curmaxkvaddr);
2179 kernel_vm_end = pmap_curmaxkvaddr;
2183 * Returns TRUE if the given page is mapped individually or as part of
2184 * a 1MB section. Otherwise, returns FALSE.
2187 pmap_page_is_mapped(vm_page_t m)
2191 if ((m->oflags & VPO_UNMANAGED) != 0)
2193 rw_wlock(&pvh_global_lock);
2194 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
2195 ((m->flags & PG_FICTITIOUS) == 0 &&
2196 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
2197 rw_wunlock(&pvh_global_lock);
2202 * Remove all pages from specified address space
2203 * this aids process exit speeds. Also, this code
2204 * is special cased for current process only, but
2205 * can have the more generic (and slightly slower)
2206 * mode enabled. This is much faster than pmap_remove
2207 * in the case of running down an entire address space.
2210 pmap_remove_pages(pmap_t pmap)
2212 struct pv_entry *pv;
2213 struct l2_bucket *l2b = NULL;
2214 struct pv_chunk *pc, *npc;
2215 struct md_page *pvh;
2216 pd_entry_t *pl1pd, l1pd;
2220 uint32_t inuse, bitmask;
2221 int allfree, bit, field, idx;
2223 rw_wlock(&pvh_global_lock);
2226 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
2228 for (field = 0; field < _NPCM; field++) {
2229 inuse = ~pc->pc_map[field] & pc_freemask[field];
2230 while (inuse != 0) {
2231 bit = ffs(inuse) - 1;
2232 bitmask = 1ul << bit;
2233 idx = field * sizeof(inuse) * NBBY + bit;
2234 pv = &pc->pc_pventry[idx];
2237 if (pv->pv_flags & PVF_WIRED) {
2238 /* Cannot remove wired pages now. */
2242 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
2244 l2b = pmap_get_l2_bucket(pmap, va);
2245 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) {
2246 pvh = pa_to_pvh(l1pd & L1_S_FRAME);
2247 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
2248 if (TAILQ_EMPTY(&pvh->pv_list)) {
2249 m = PHYS_TO_VM_PAGE(l1pd & L1_S_FRAME);
2250 KASSERT((vm_offset_t)m >= KERNBASE,
2251 ("Trying to access non-existent page "
2252 "va %x l1pd %x", trunc_1mpage(va), l1pd));
2253 for (mt = m; mt < &m[L2_PTE_NUM_TOTAL]; mt++) {
2254 if (TAILQ_EMPTY(&mt->md.pv_list))
2255 vm_page_aflag_clear(mt, PGA_WRITEABLE);
2259 KASSERT(l2b->l2b_occupancy == L2_PTE_NUM_TOTAL,
2260 ("pmap_remove_pages: l2_bucket occupancy error"));
2261 pmap_free_l2_bucket(pmap, l2b, L2_PTE_NUM_TOTAL);
2263 pmap->pm_stats.resident_count -= L2_PTE_NUM_TOTAL;
2267 KASSERT(l2b != NULL,
2268 ("No L2 bucket in pmap_remove_pages"));
2269 ptep = &l2b->l2b_kva[l2pte_index(va)];
2270 m = PHYS_TO_VM_PAGE(l2pte_pa(*ptep));
2271 KASSERT((vm_offset_t)m >= KERNBASE,
2272 ("Trying to access non-existent page "
2273 "va %x pte %x", va, *ptep));
2274 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2275 if (TAILQ_EMPTY(&m->md.pv_list) &&
2276 (m->flags & PG_FICTITIOUS) == 0) {
2277 pvh = pa_to_pvh(l2pte_pa(*ptep));
2278 if (TAILQ_EMPTY(&pvh->pv_list))
2279 vm_page_aflag_clear(m, PGA_WRITEABLE);
2283 pmap_free_l2_bucket(pmap, l2b, 1);
2284 pmap->pm_stats.resident_count--;
2288 PV_STAT(pv_entry_frees++);
2289 PV_STAT(pv_entry_spare++);
2291 pc->pc_map[field] |= bitmask;
2295 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2296 pmap_free_pv_chunk(pc);
2301 rw_wunlock(&pvh_global_lock);
2308 /***************************************************
2309 * Low level mapping routines.....
2310 ***************************************************/
2312 #ifdef ARM_HAVE_SUPERSECTIONS
2313 /* Map a super section into the KVA. */
2316 pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
2318 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) |
2319 (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL,
2320 VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE) |
2321 L1_S_DOM(PMAP_DOMAIN_KERNEL);
2322 struct l1_ttable *l1;
2323 vm_offset_t va0, va_end;
2325 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
2326 ("Not a valid super section mapping"));
2327 if (flags & SECTION_CACHE)
2328 pd |= pte_l1_s_cache_mode;
2329 else if (flags & SECTION_PT)
2330 pd |= pte_l1_s_cache_mode_pt;
2332 va0 = va & L1_SUP_FRAME;
2333 va_end = va + L1_SUP_SIZE;
2334 SLIST_FOREACH(l1, &l1_list, l1_link) {
2336 for (; va < va_end; va += L1_S_SIZE) {
2337 l1->l1_kva[L1_IDX(va)] = pd;
2338 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2344 /* Map a section into the KVA. */
2347 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2349 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2350 VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE) | L1_S_REF |
2351 L1_S_DOM(PMAP_DOMAIN_KERNEL);
2352 struct l1_ttable *l1;
2354 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2355 ("Not a valid section mapping"));
2356 if (flags & SECTION_CACHE)
2357 pd |= pte_l1_s_cache_mode;
2358 else if (flags & SECTION_PT)
2359 pd |= pte_l1_s_cache_mode_pt;
2361 SLIST_FOREACH(l1, &l1_list, l1_link) {
2362 l1->l1_kva[L1_IDX(va)] = pd;
2363 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2365 cpu_tlb_flushID_SE(va);
2370 * Make a temporary mapping for a physical address. This is only intended
2371 * to be used for panic dumps.
2374 pmap_kenter_temporary(vm_paddr_t pa, int i)
2378 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
2379 pmap_kenter(va, pa);
2380 return ((void *)crashdumpmap);
2384 * add a wired page to the kva
2385 * note that in order for the mapping to take effect -- you
2386 * should do a invltlb after doing the pmap_kenter...
2388 static PMAP_INLINE void
2389 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2391 struct l2_bucket *l2b;
2395 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2396 (uint32_t) va, (uint32_t) pa));
2399 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2401 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2402 KASSERT(l2b != NULL, ("No L2 Bucket"));
2404 ptep = &l2b->l2b_kva[l2pte_index(va)];
2407 if (flags & KENTER_CACHE)
2408 *ptep = L2_S_PROTO | l2s_mem_types[PTE_CACHE] | pa | L2_S_REF;
2409 else if (flags & KENTER_DEVICE)
2410 *ptep = L2_S_PROTO | l2s_mem_types[PTE_DEVICE] | pa | L2_S_REF;
2412 *ptep = L2_S_PROTO | l2s_mem_types[PTE_NOCACHE] | pa | L2_S_REF;
2414 if (flags & KENTER_CACHE) {
2415 pmap_set_prot(ptep, VM_PROT_READ | VM_PROT_WRITE,
2416 flags & KENTER_USER);
2418 pmap_set_prot(ptep, VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE,
2423 if (l2pte_valid(opte)) {
2424 if (L2_S_EXECUTABLE(opte) || L2_S_EXECUTABLE(*ptep))
2425 cpu_tlb_flushID_SE(va);
2427 cpu_tlb_flushD_SE(va);
2430 l2b->l2b_occupancy++;
2434 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2435 (uint32_t) ptep, opte, *ptep));
2439 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2441 pmap_kenter_internal(va, pa, KENTER_CACHE);
2445 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2448 pmap_kenter_internal(va, pa, 0);
2452 pmap_kenter_device(vm_offset_t va, vm_paddr_t pa)
2455 pmap_kenter_internal(va, pa, KENTER_DEVICE);
2459 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2462 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2464 * Call pmap_fault_fixup now, to make sure we'll have no exception
2465 * at the first use of the new address, or bad things will happen,
2466 * as we use one of these addresses in the exception handlers.
2468 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2472 pmap_kextract(vm_offset_t va)
2475 if (kernel_vm_end == 0)
2477 return (pmap_extract_locked(kernel_pmap, va));
2481 * remove a page from the kernel pagetables
2484 pmap_kremove(vm_offset_t va)
2486 struct l2_bucket *l2b;
2487 pt_entry_t *ptep, opte;
2489 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2492 KASSERT(l2b != NULL, ("No L2 Bucket"));
2493 ptep = &l2b->l2b_kva[l2pte_index(va)];
2495 if (l2pte_valid(opte)) {
2496 va = va & ~PAGE_MASK;
2499 if (L2_S_EXECUTABLE(opte))
2500 cpu_tlb_flushID_SE(va);
2502 cpu_tlb_flushD_SE(va);
2509 * Used to map a range of physical addresses into kernel
2510 * virtual address space.
2512 * The value passed in '*virt' is a suggested virtual address for
2513 * the mapping. Architectures which can support a direct-mapped
2514 * physical to virtual region can return the appropriate address
2515 * within that region, leaving '*virt' unchanged. Other
2516 * architectures should map the pages starting at '*virt' and
2517 * update '*virt' with the first usable address after the mapped
2521 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2523 vm_offset_t sva = *virt;
2524 vm_offset_t va = sva;
2526 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2527 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2530 while (start < end) {
2531 pmap_kenter(va, start);
2540 * Add a list of wired pages to the kva
2541 * this routine is only used for temporary
2542 * kernel mappings that do not need to have
2543 * page modification or references recorded.
2544 * Note that old mappings are simply written
2545 * over. The page *must* be wired.
2548 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
2552 for (i = 0; i < count; i++) {
2553 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
2561 * this routine jerks page mappings from the
2562 * kernel -- it is meant only for temporary mappings.
2565 pmap_qremove(vm_offset_t va, int count)
2569 for (i = 0; i < count; i++) {
2579 * pmap_object_init_pt preloads the ptes for a given object
2580 * into the specified pmap. This eliminates the blast of soft
2581 * faults on process startup and immediately after an mmap.
2584 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
2585 vm_pindex_t pindex, vm_size_t size)
2588 VM_OBJECT_ASSERT_WLOCKED(object);
2589 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2590 ("pmap_object_init_pt: non-device object"));
2595 * pmap_is_prefaultable:
2597 * Return whether or not the specified virtual address is elgible
2601 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2606 if (!pmap_get_pde_pte(pmap, addr, &pdep, &ptep))
2608 KASSERT((pdep != NULL && (l1pte_section_p(*pdep) || ptep != NULL)),
2609 ("Valid mapping but no pte ?"));
2610 if (*pdep != 0 && !l1pte_section_p(*pdep))
2617 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
2618 * Returns TRUE if the mapping exists, else FALSE.
2620 * NOTE: This function is only used by a couple of arm-specific modules.
2621 * It is not safe to take any pmap locks here, since we could be right
2622 * in the middle of debugging the pmap anyway...
2624 * It is possible for this routine to return FALSE even though a valid
2625 * mapping does exist. This is because we don't lock, so the metadata
2626 * state may be inconsistent.
2628 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
2629 * a "section" mapping.
2632 pmap_get_pde_pte(pmap_t pmap, vm_offset_t va, pd_entry_t **pdp,
2635 struct l2_dtable *l2;
2636 pd_entry_t *pl1pd, l1pd;
2640 if (pmap->pm_l1 == NULL)
2644 *pdp = pl1pd = &pmap->pm_l1->l1_kva[l1idx];
2647 if (l1pte_section_p(l1pd)) {
2652 if (pmap->pm_l2 == NULL)
2655 l2 = pmap->pm_l2[L2_IDX(l1idx)];
2658 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
2662 *ptp = &ptep[l2pte_index(va)];
2667 * Routine: pmap_remove_all
2669 * Removes this physical page from
2670 * all physical maps in which it resides.
2671 * Reflects back modify bits to the pager.
2674 * Original versions of this routine were very
2675 * inefficient because they iteratively called
2676 * pmap_remove (slow...)
2679 pmap_remove_all(vm_page_t m)
2681 struct md_page *pvh;
2685 struct l2_bucket *l2b;
2686 boolean_t flush = FALSE;
2690 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2691 ("pmap_remove_all: page %p is not managed", m));
2692 rw_wlock(&pvh_global_lock);
2693 if ((m->flags & PG_FICTITIOUS) != 0)
2694 goto small_mappings;
2695 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2696 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2700 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(pv->pv_va)];
2701 KASSERT((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO,
2702 ("pmap_remove_all: valid section mapping expected"));
2703 (void)pmap_demote_section(pmap, pv->pv_va);
2707 curpmap = vmspace_pmap(curproc->p_vmspace);
2708 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2710 if (flush == FALSE && (pmap == curpmap ||
2711 pmap == pmap_kernel()))
2715 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2716 KASSERT(l2b != NULL, ("No l2 bucket"));
2717 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2718 is_exec |= PTE_BEEN_EXECD(*ptep);
2720 if (pmap_is_current(pmap))
2722 pmap_free_l2_bucket(pmap, l2b, 1);
2723 pmap->pm_stats.resident_count--;
2724 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2725 if (pv->pv_flags & PVF_WIRED)
2726 pmap->pm_stats.wired_count--;
2727 pmap_free_pv_entry(pmap, pv);
2738 vm_page_aflag_clear(m, PGA_WRITEABLE);
2739 rw_wunlock(&pvh_global_lock);
2743 pmap_change_attr(vm_offset_t sva, vm_size_t len, int mode)
2745 vm_offset_t base, offset, tmpva;
2747 struct l2_bucket *l2b;
2748 pt_entry_t *ptep, pte;
2749 vm_offset_t next_bucket;
2751 PMAP_LOCK(kernel_pmap);
2753 base = trunc_page(sva);
2754 offset = sva & PAGE_MASK;
2755 size = roundup(offset + len, PAGE_SIZE);
2759 * Only supported on kernel virtual addresses, including the direct
2760 * map but excluding the recursive map.
2762 if (base < DMAP_MIN_ADDRESS) {
2763 PMAP_UNLOCK(kernel_pmap);
2767 for (tmpva = base; tmpva < base + size; ) {
2768 next_bucket = L2_NEXT_BUCKET(tmpva);
2769 if (next_bucket > base + size)
2770 next_bucket = base + size;
2772 l2b = pmap_get_l2_bucket(kernel_pmap, tmpva);
2774 tmpva = next_bucket;
2778 ptep = &l2b->l2b_kva[l2pte_index(tmpva)];
2781 PMAP_UNLOCK(kernel_pmap);
2785 pte = *ptep &~ L2_S_CACHE_MASK;
2786 cpu_idcache_wbinv_range(tmpva, PAGE_SIZE);
2787 pmap_l2cache_wbinv_range(tmpva, pte & L2_S_FRAME, PAGE_SIZE);
2789 cpu_tlb_flushID_SE(tmpva);
2792 dprintf("%s: for va:%x ptep:%x pte:%x\n",
2793 __func__, tmpva, (uint32_t)ptep, pte);
2797 PMAP_UNLOCK(kernel_pmap);
2803 * Set the physical protection on the
2804 * specified range of this map as requested.
2807 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2809 struct l2_bucket *l2b;
2810 struct md_page *pvh;
2811 struct pv_entry *pve;
2812 pd_entry_t *pl1pd, l1pd;
2813 pt_entry_t *ptep, pte;
2814 vm_offset_t next_bucket;
2815 u_int is_exec, is_refd;
2818 if ((prot & VM_PROT_READ) == 0) {
2819 pmap_remove(pmap, sva, eva);
2823 if (prot & VM_PROT_WRITE) {
2825 * If this is a read->write transition, just ignore it and let
2826 * vm_fault() take care of it later.
2831 rw_wlock(&pvh_global_lock);
2835 * OK, at this point, we know we're doing write-protect operation.
2836 * If the pmap is active, write-back the range.
2839 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
2840 is_exec = is_refd = 0;
2843 next_bucket = L2_NEXT_BUCKET(sva);
2845 * Check for large page.
2847 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(sva)];
2849 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) {
2850 KASSERT(pmap != pmap_kernel(),
2851 ("pmap_protect: trying to modify "
2852 "kernel section protections"));
2854 * Are we protecting the entire large page? If not,
2855 * demote the mapping and fall through.
2857 if (sva + L1_S_SIZE == L2_NEXT_BUCKET(sva) &&
2858 eva >= L2_NEXT_BUCKET(sva)) {
2859 l1pd &= ~(L1_S_PROT_MASK | L1_S_XN);
2860 if (!(prot & VM_PROT_EXECUTE))
2863 * At this point we are always setting
2864 * write-protect bit.
2867 /* All managed superpages are user pages. */
2868 l1pd |= L1_S_PROT_U;
2871 pvh = pa_to_pvh(l1pd & L1_S_FRAME);
2872 pve = pmap_find_pv(pvh, pmap,
2874 pve->pv_flags &= ~PVF_WRITE;
2877 } else if (!pmap_demote_section(pmap, sva)) {
2878 /* The large page mapping was destroyed. */
2883 if (next_bucket > eva)
2885 l2b = pmap_get_l2_bucket(pmap, sva);
2891 ptep = &l2b->l2b_kva[l2pte_index(sva)];
2893 while (sva < next_bucket) {
2894 if ((pte = *ptep) != 0 && L2_S_WRITABLE(pte)) {
2897 m = PHYS_TO_VM_PAGE(l2pte_pa(pte));
2898 pmap_set_prot(ptep, prot,
2899 !(pmap == pmap_kernel()));
2902 pmap_modify_pv(m, pmap, sva, PVF_WRITE, 0);
2906 is_exec |= PTE_BEEN_EXECD(pte);
2907 is_refd |= PTE_BEEN_REFD(pte);
2909 if (PTE_BEEN_EXECD(pte))
2910 cpu_tlb_flushID_SE(sva);
2911 else if (PTE_BEEN_REFD(pte))
2912 cpu_tlb_flushD_SE(sva);
2930 rw_wunlock(&pvh_global_lock);
2937 * Insert the given physical page (p) at
2938 * the specified virtual address (v) in the
2939 * target physical map with the protection requested.
2941 * If specified, the page will be wired down, meaning
2942 * that the related pte can not be reclaimed.
2944 * NB: This is the only routine which MAY NOT lazy-evaluate
2945 * or lose information. That is, this routine must actually
2946 * insert this page into the given map NOW.
2950 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2951 u_int flags, int8_t psind __unused)
2953 struct l2_bucket *l2b;
2956 rw_wlock(&pvh_global_lock);
2958 rv = pmap_enter_locked(pmap, va, m, prot, flags);
2959 if (rv == KERN_SUCCESS) {
2961 * If both the l2b_occupancy and the reservation are fully
2962 * populated, then attempt promotion.
2964 l2b = pmap_get_l2_bucket(pmap, va);
2965 if (l2b != NULL && l2b->l2b_occupancy == L2_PTE_NUM_TOTAL &&
2966 sp_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
2967 vm_reserv_level_iffullpop(m) == 0)
2968 pmap_promote_section(pmap, va);
2971 rw_wunlock(&pvh_global_lock);
2976 * The pvh global and pmap locks must be held.
2979 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2982 struct l2_bucket *l2b = NULL;
2984 struct pv_entry *pve = NULL;
2985 pd_entry_t *pl1pd, l1pd;
2986 pt_entry_t *ptep, npte, opte;
2988 u_int is_exec, is_refd;
2992 PMAP_ASSERT_LOCKED(pmap);
2993 rw_assert(&pvh_global_lock, RA_WLOCKED);
2994 if (va == vector_page) {
2995 pa = systempage.pv_pa;
2998 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2999 VM_OBJECT_ASSERT_LOCKED(m->object);
3000 pa = VM_PAGE_TO_PHYS(m);
3003 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3004 if ((va < VM_MAXUSER_ADDRESS) &&
3005 (*pl1pd & L1_TYPE_MASK) == L1_S_PROTO) {
3006 (void)pmap_demote_section(pmap, va);
3011 * Make sure userland mappings get the right permissions
3013 if (pmap != pmap_kernel() && va != vector_page)
3018 if (prot & VM_PROT_WRITE)
3019 nflags |= PVF_WRITE;
3020 if ((flags & PMAP_ENTER_WIRED) != 0)
3021 nflags |= PVF_WIRED;
3023 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, "
3024 "prot = %x, flags = %x\n", (uint32_t) pmap, va, (uint32_t) m,
3027 if (pmap == pmap_kernel()) {
3028 l2b = pmap_get_l2_bucket(pmap, va);
3030 l2b = pmap_grow_l2_bucket(pmap, va);
3033 l2b = pmap_alloc_l2_bucket(pmap, va);
3035 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
3037 rw_wunlock(&pvh_global_lock);
3039 rw_wlock(&pvh_global_lock);
3043 return (KERN_RESOURCE_SHORTAGE);
3047 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3048 if ((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO)
3049 panic("pmap_enter: attempt to enter on 1MB page, va: %#x", va);
3051 ptep = &l2b->l2b_kva[l2pte_index(va)];
3055 is_exec = is_refd = 0;
3058 if (l2pte_pa(opte) == pa) {
3060 * We're changing the attrs of an existing mapping.
3063 pmap_modify_pv(m, pmap, va,
3064 PVF_WRITE | PVF_WIRED, nflags);
3065 is_exec |= PTE_BEEN_EXECD(opte);
3066 is_refd |= PTE_BEEN_REFD(opte);
3069 if ((om = PHYS_TO_VM_PAGE(l2pte_pa(opte)))) {
3071 * Replacing an existing mapping with a new one.
3072 * It is part of our managed memory so we
3073 * must remove it from the PV list
3075 if ((pve = pmap_remove_pv(om, pmap, va))) {
3076 is_exec |= PTE_BEEN_EXECD(opte);
3077 is_refd |= PTE_BEEN_REFD(opte);
3079 if (m && ((m->oflags & VPO_UNMANAGED)))
3080 pmap_free_pv_entry(pmap, pve);
3086 * Keep the stats up to date
3088 l2b->l2b_occupancy++;
3089 pmap->pm_stats.resident_count++;
3093 * Enter on the PV list if part of our managed memory.
3095 if ((m && !(m->oflags & VPO_UNMANAGED))) {
3096 if ((!pve) && (pve = pmap_get_pv_entry(pmap, FALSE)) == NULL)
3097 panic("pmap_enter: no pv entries");
3099 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3100 ("pmap_enter: managed mapping within the clean submap"));
3101 KASSERT(pve != NULL, ("No pv"));
3102 pmap_enter_pv(m, pve, pmap, va, nflags);
3106 /* Make the new PTE valid */
3111 /* Set defaults first - kernel read access */
3113 npte |= L2_S_PROT_R;
3114 /* Set "referenced" flag */
3117 /* Now tune APs as desired */
3119 npte |= L2_S_PROT_U;
3121 * If this is not a vector_page
3122 * then continue setting mapping parameters
3125 if ((m->oflags & VPO_UNMANAGED) == 0) {
3126 if (prot & (VM_PROT_ALL)) {
3127 vm_page_aflag_set(m, PGA_REFERENCED);
3130 * Need to do page referenced emulation.
3136 if (prot & VM_PROT_WRITE) {
3137 if ((m->oflags & VPO_UNMANAGED) == 0) {
3138 vm_page_aflag_set(m, PGA_WRITEABLE);
3140 * XXX: Skip modified bit emulation for now.
3141 * The emulation reveals problems
3142 * that result in random failures
3143 * during memory allocation on some
3145 * Therefore, the page is marked RW
3153 if (!(prot & VM_PROT_EXECUTE))
3156 if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
3157 npte |= pte_l2_s_cache_mode;
3160 CTR5(KTR_PMAP,"enter: pmap:%p va:%x prot:%x pte:%x->%x",
3161 pmap, va, prot, opte, npte);
3163 * If this is just a wiring change, the two PTEs will be
3164 * identical, so there's no need to update the page table.
3167 boolean_t is_cached = pmap_is_current(pmap);
3173 * We only need to frob the cache/tlb if this pmap
3176 if (L1_IDX(va) != L1_IDX(vector_page) &&
3177 l2pte_valid(npte)) {
3179 * This mapping is likely to be accessed as
3180 * soon as we return to userland. Fix up the
3181 * L1 entry to avoid taking another
3182 * page/domain fault.
3184 l1pd = l2b->l2b_phys |
3185 L1_C_DOM(pmap->pm_domain) | L1_C_PROTO;
3186 if (*pl1pd != l1pd) {
3194 cpu_tlb_flushID_SE(va);
3196 cpu_tlb_flushD_SE(va);
3200 if ((pmap != pmap_kernel()) && (pmap == &curproc->p_vmspace->vm_pmap))
3201 cpu_icache_sync_range(va, PAGE_SIZE);
3202 return (KERN_SUCCESS);
3206 * Maps a sequence of resident pages belonging to the same object.
3207 * The sequence begins with the given page m_start. This page is
3208 * mapped at the given virtual address start. Each subsequent page is
3209 * mapped at a virtual address that is offset from start by the same
3210 * amount as the page is offset from m_start within the object. The
3211 * last page in the sequence is the page with the largest offset from
3212 * m_start that can be mapped at a virtual address less than the given
3213 * virtual address end. Not every virtual page between start and end
3214 * is mapped; only those for which a resident page exists with the
3215 * corresponding offset from m_start are mapped.
3218 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3219 vm_page_t m_start, vm_prot_t prot)
3223 vm_pindex_t diff, psize;
3225 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3227 psize = atop(end - start);
3229 prot &= VM_PROT_READ | VM_PROT_EXECUTE;
3230 rw_wlock(&pvh_global_lock);
3232 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3233 va = start + ptoa(diff);
3234 if ((va & L1_S_OFFSET) == 0 && L2_NEXT_BUCKET(va) <= end &&
3235 m->psind == 1 && sp_enabled &&
3236 pmap_enter_section(pmap, va, m, prot))
3237 m = &m[L1_S_SIZE / PAGE_SIZE - 1];
3239 pmap_enter_locked(pmap, va, m, prot,
3240 PMAP_ENTER_NOSLEEP);
3241 m = TAILQ_NEXT(m, listq);
3244 rw_wunlock(&pvh_global_lock);
3248 * this code makes some *MAJOR* assumptions:
3249 * 1. Current pmap & pmap exists.
3252 * 4. No page table pages.
3253 * but is *MUCH* faster than pmap_enter...
3257 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3260 prot &= VM_PROT_READ | VM_PROT_EXECUTE;
3261 rw_wlock(&pvh_global_lock);
3263 pmap_enter_locked(pmap, va, m, prot, PMAP_ENTER_NOSLEEP);
3265 rw_wunlock(&pvh_global_lock);
3269 * Clear the wired attribute from the mappings for the specified range of
3270 * addresses in the given pmap. Every valid mapping within that range
3271 * must have the wired attribute set. In contrast, invalid mappings
3272 * cannot have the wired attribute set, so they are ignored.
3274 * XXX Wired mappings of unmanaged pages cannot be counted by this pmap
3278 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3280 struct l2_bucket *l2b;
3281 struct md_page *pvh;
3283 pt_entry_t *ptep, pte;
3285 vm_offset_t next_bucket;
3289 rw_wlock(&pvh_global_lock);
3292 next_bucket = L2_NEXT_BUCKET(sva);
3293 l1pd = pmap->pm_l1->l1_kva[L1_IDX(sva)];
3294 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) {
3295 pa = l1pd & L1_S_FRAME;
3296 m = PHYS_TO_VM_PAGE(pa);
3297 KASSERT(m != NULL && (m->oflags & VPO_UNMANAGED) == 0,
3298 ("pmap_unwire: unmanaged 1mpage %p", m));
3299 pvh = pa_to_pvh(pa);
3300 pv = pmap_find_pv(pvh, pmap, trunc_1mpage(sva));
3301 if ((pv->pv_flags & PVF_WIRED) == 0)
3302 panic("pmap_unwire: pv %p isn't wired", pv);
3305 * Are we unwiring the entire large page? If not,
3306 * demote the mapping and fall through.
3308 if (sva + L1_S_SIZE == next_bucket &&
3309 eva >= next_bucket) {
3310 pv->pv_flags &= ~PVF_WIRED;
3311 pmap->pm_stats.wired_count -= L2_PTE_NUM_TOTAL;
3314 } else if (!pmap_demote_section(pmap, sva))
3315 panic("pmap_unwire: demotion failed");
3317 if (next_bucket > eva)
3319 l2b = pmap_get_l2_bucket(pmap, sva);
3324 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; sva < next_bucket;
3325 sva += PAGE_SIZE, ptep++) {
3326 if ((pte = *ptep) == 0 ||
3327 (m = PHYS_TO_VM_PAGE(l2pte_pa(pte))) == NULL ||
3328 (m->oflags & VPO_UNMANAGED) != 0)
3330 pv = pmap_find_pv(&m->md, pmap, sva);
3331 if ((pv->pv_flags & PVF_WIRED) == 0)
3332 panic("pmap_unwire: pv %p isn't wired", pv);
3333 pv->pv_flags &= ~PVF_WIRED;
3334 pmap->pm_stats.wired_count--;
3337 rw_wunlock(&pvh_global_lock);
3343 * Copy the range specified by src_addr/len
3344 * from the source map to the range dst_addr/len
3345 * in the destination map.
3347 * This routine is only advisory and need not do anything.
3350 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3351 vm_size_t len, vm_offset_t src_addr)
3357 * Routine: pmap_extract
3359 * Extract the physical page address associated
3360 * with the given map/virtual_address pair.
3363 pmap_extract(pmap_t pmap, vm_offset_t va)
3367 if (kernel_vm_end != 0)
3369 pa = pmap_extract_locked(pmap, va);
3370 if (kernel_vm_end != 0)
3376 pmap_extract_locked(pmap_t pmap, vm_offset_t va)
3378 struct l2_dtable *l2;
3380 pt_entry_t *ptep, pte;
3384 if (kernel_vm_end != 0 && pmap != kernel_pmap)
3385 PMAP_ASSERT_LOCKED(pmap);
3387 l1pd = pmap->pm_l1->l1_kva[l1idx];
3388 if (l1pte_section_p(l1pd)) {
3389 /* XXX: what to do about the bits > 32 ? */
3390 if (l1pd & L1_S_SUPERSEC)
3391 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3393 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3396 * Note that we can't rely on the validity of the L1
3397 * descriptor as an indication that a mapping exists.
3398 * We have to look it up in the L2 dtable.
3400 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3402 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL)
3404 pte = ptep[l2pte_index(va)];
3407 switch (pte & L2_TYPE_MASK) {
3409 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3412 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3420 * Atomically extract and hold the physical page with the given
3421 * pmap and virtual address pair if that mapping permits the given
3426 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3428 struct l2_dtable *l2;
3430 pt_entry_t *ptep, pte;
3431 vm_paddr_t pa, paddr;
3439 l1pd = pmap->pm_l1->l1_kva[l1idx];
3440 if (l1pte_section_p(l1pd)) {
3441 /* XXX: what to do about the bits > 32 ? */
3442 if (l1pd & L1_S_SUPERSEC)
3443 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3445 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3446 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3448 if (L1_S_WRITABLE(l1pd) || (prot & VM_PROT_WRITE) == 0) {
3449 m = PHYS_TO_VM_PAGE(pa);
3454 * Note that we can't rely on the validity of the L1
3455 * descriptor as an indication that a mapping exists.
3456 * We have to look it up in the L2 dtable.
3458 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3461 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3466 ptep = &ptep[l2pte_index(va)];
3472 } else if ((prot & VM_PROT_WRITE) && (pte & L2_APX)) {
3476 switch (pte & L2_TYPE_MASK) {
3478 panic("extract and hold section mapping");
3481 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3484 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3486 m = PHYS_TO_VM_PAGE(pa);
3493 PA_UNLOCK_COND(paddr);
3498 * Initialize a preallocated and zeroed pmap structure,
3499 * such as one in a vmspace structure.
3503 pmap_pinit(pmap_t pmap)
3505 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3507 pmap_alloc_l1(pmap);
3508 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3510 CPU_ZERO(&pmap->pm_active);
3512 TAILQ_INIT(&pmap->pm_pvchunk);
3513 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3514 pmap->pm_stats.resident_count = 1;
3515 if (vector_page < KERNBASE) {
3516 pmap_enter(pmap, vector_page,
3517 PHYS_TO_VM_PAGE(systempage.pv_pa), VM_PROT_READ,
3518 PMAP_ENTER_WIRED, 0);
3524 /***************************************************
3525 * Superpage management routines.
3526 ***************************************************/
3528 static PMAP_INLINE struct pv_entry *
3529 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3533 rw_assert(&pvh_global_lock, RA_WLOCKED);
3535 pv = pmap_find_pv(pvh, pmap, va);
3537 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
3543 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3547 pv = pmap_pvh_remove(pvh, pmap, va);
3548 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3549 pmap_free_pv_entry(pmap, pv);
3553 pmap_pv_insert_section(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3555 struct md_page *pvh;
3558 rw_assert(&pvh_global_lock, RA_WLOCKED);
3559 if (pv_entry_count < pv_entry_high_water &&
3560 (pv = pmap_get_pv_entry(pmap, TRUE)) != NULL) {
3562 pvh = pa_to_pvh(pa);
3563 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
3570 * Create the pv entries for each of the pages within a superpage.
3573 pmap_pv_demote_section(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3575 struct md_page *pvh;
3577 vm_offset_t va_last;
3580 rw_assert(&pvh_global_lock, RA_WLOCKED);
3581 KASSERT((pa & L1_S_OFFSET) == 0,
3582 ("pmap_pv_demote_section: pa is not 1mpage aligned"));
3585 * Transfer the 1mpage's pv entry for this mapping to the first
3588 pvh = pa_to_pvh(pa);
3589 va = trunc_1mpage(va);
3590 pv = pmap_pvh_remove(pvh, pmap, va);
3591 KASSERT(pv != NULL, ("pmap_pv_demote_section: pv not found"));
3592 m = PHYS_TO_VM_PAGE(pa);
3593 TAILQ_INSERT_HEAD(&m->md.pv_list, pv, pv_list);
3594 /* Instantiate the remaining pv entries. */
3595 va_last = L2_NEXT_BUCKET(va) - PAGE_SIZE;
3598 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3599 ("pmap_pv_demote_section: page %p is not managed", m));
3601 pve = pmap_get_pv_entry(pmap, FALSE);
3602 pmap_enter_pv(m, pve, pmap, va, pv->pv_flags);
3603 } while (va < va_last);
3607 pmap_pv_promote_section(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3609 struct md_page *pvh;
3611 vm_offset_t va_last;
3614 rw_assert(&pvh_global_lock, RA_WLOCKED);
3615 KASSERT((pa & L1_S_OFFSET) == 0,
3616 ("pmap_pv_promote_section: pa is not 1mpage aligned"));
3619 * Transfer the first page's pv entry for this mapping to the
3620 * 1mpage's pv list. Aside from avoiding the cost of a call
3621 * to get_pv_entry(), a transfer avoids the possibility that
3622 * get_pv_entry() calls pmap_pv_reclaim() and that pmap_pv_reclaim()
3623 * removes one of the mappings that is being promoted.
3625 m = PHYS_TO_VM_PAGE(pa);
3626 va = trunc_1mpage(va);
3627 pv = pmap_pvh_remove(&m->md, pmap, va);
3628 KASSERT(pv != NULL, ("pmap_pv_promote_section: pv not found"));
3629 pvh = pa_to_pvh(pa);
3630 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
3631 /* Free the remaining pv entries in the newly mapped section pages */
3632 va_last = L2_NEXT_BUCKET(va) - PAGE_SIZE;
3637 * Don't care the flags, first pv contains sufficient
3638 * information for all of the pages so nothing is really lost.
3640 pmap_pvh_free(&m->md, pmap, va);
3641 } while (va < va_last);
3645 * Tries to create a 1MB page mapping. Returns TRUE if successful and
3646 * FALSE otherwise. Fails if (1) page is unmanageg, kernel pmap or vectors
3647 * page, (2) a mapping already exists at the specified virtual address, or
3648 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3651 pmap_enter_section(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3655 struct l2_bucket *l2b;
3657 rw_assert(&pvh_global_lock, RA_WLOCKED);
3658 PMAP_ASSERT_LOCKED(pmap);
3660 /* Skip kernel, vectors page and unmanaged mappings */
3661 if ((pmap == pmap_kernel()) || (L1_IDX(va) == L1_IDX(vector_page)) ||
3662 ((m->oflags & VPO_UNMANAGED) != 0)) {
3663 CTR2(KTR_PMAP, "pmap_enter_section: failure for va %#lx"
3664 " in pmap %p", va, pmap);
3668 * Check whether this is a valid section superpage entry or
3669 * there is a l2_bucket associated with that L1 page directory.
3671 va = trunc_1mpage(va);
3672 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3673 l2b = pmap_get_l2_bucket(pmap, va);
3674 if ((*pl1pd & L1_S_PROTO) || (l2b != NULL)) {
3675 CTR2(KTR_PMAP, "pmap_enter_section: failure for va %#lx"
3676 " in pmap %p", va, pmap);
3679 pa = VM_PAGE_TO_PHYS(m);
3681 * Abort this mapping if its PV entry could not be created.
3683 if (!pmap_pv_insert_section(pmap, va, VM_PAGE_TO_PHYS(m))) {
3684 CTR2(KTR_PMAP, "pmap_enter_section: failure for va %#lx"
3685 " in pmap %p", va, pmap);
3689 * Increment counters.
3691 pmap->pm_stats.resident_count += L2_PTE_NUM_TOTAL;
3693 * Despite permissions, mark the superpage read-only.
3695 prot &= ~VM_PROT_WRITE;
3697 * Map the superpage.
3699 pmap_map_section(pmap, va, pa, prot, FALSE);
3701 pmap_section_mappings++;
3702 CTR2(KTR_PMAP, "pmap_enter_section: success for va %#lx"
3703 " in pmap %p", va, pmap);
3708 * pmap_remove_section: do the things to unmap a superpage in a process
3711 pmap_remove_section(pmap_t pmap, vm_offset_t sva)
3713 struct md_page *pvh;
3714 struct l2_bucket *l2b;
3715 pd_entry_t *pl1pd, l1pd;
3716 vm_offset_t eva, va;
3719 PMAP_ASSERT_LOCKED(pmap);
3720 if ((pmap == pmap_kernel()) || (L1_IDX(sva) == L1_IDX(vector_page)))
3723 KASSERT((sva & L1_S_OFFSET) == 0,
3724 ("pmap_remove_section: sva is not 1mpage aligned"));
3726 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(sva)];
3729 m = PHYS_TO_VM_PAGE(l1pd & L1_S_FRAME);
3730 KASSERT((m != NULL && ((m->oflags & VPO_UNMANAGED) == 0)),
3731 ("pmap_remove_section: no corresponding vm_page or "
3734 pmap->pm_stats.resident_count -= L2_PTE_NUM_TOTAL;
3735 pvh = pa_to_pvh(l1pd & L1_S_FRAME);
3736 pmap_pvh_free(pvh, pmap, sva);
3737 eva = L2_NEXT_BUCKET(sva);
3738 for (va = sva, m = PHYS_TO_VM_PAGE(l1pd & L1_S_FRAME);
3739 va < eva; va += PAGE_SIZE, m++) {
3741 * Mark base pages referenced but skip marking them dirty.
3742 * If the superpage is writeable, hence all base pages were
3743 * already marked as dirty in pmap_fault_fixup() before
3744 * promotion. Reference bit however, might not have been set
3745 * for each base page when the superpage was created at once,
3746 * not as a result of promotion.
3748 if (L1_S_REFERENCED(l1pd))
3749 vm_page_aflag_set(m, PGA_REFERENCED);
3750 if (TAILQ_EMPTY(&m->md.pv_list) &&
3751 TAILQ_EMPTY(&pvh->pv_list))
3752 vm_page_aflag_clear(m, PGA_WRITEABLE);
3755 l2b = pmap_get_l2_bucket(pmap, sva);
3757 KASSERT(l2b->l2b_occupancy == L2_PTE_NUM_TOTAL,
3758 ("pmap_remove_section: l2_bucket occupancy error"));
3759 pmap_free_l2_bucket(pmap, l2b, L2_PTE_NUM_TOTAL);
3761 /* Now invalidate L1 slot */
3764 if (L1_S_EXECUTABLE(l1pd))
3765 cpu_tlb_flushID_SE(sva);
3767 cpu_tlb_flushD_SE(sva);
3772 * Tries to promote the 256, contiguous 4KB page mappings that are
3773 * within a single l2_bucket to a single 1MB section mapping.
3774 * For promotion to occur, two conditions must be met: (1) the 4KB page
3775 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3776 * mappings must have identical characteristics.
3779 pmap_promote_section(pmap_t pmap, vm_offset_t va)
3781 pt_entry_t *firstptep, firstpte, oldpte, pa, *pte;
3783 vm_offset_t first_va, old_va;
3784 struct l2_bucket *l2b = NULL;
3786 struct pv_entry *pve, *first_pve;
3788 PMAP_ASSERT_LOCKED(pmap);
3792 * Skip promoting kernel pages. This is justified by following:
3793 * 1. Kernel is already mapped using section mappings in each pmap
3794 * 2. Managed mappings within the kernel are not to be promoted anyway
3796 if (pmap == pmap_kernel()) {
3797 pmap_section_p_failures++;
3798 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x"
3799 " in pmap %p", va, pmap);
3802 /* Do not attemp to promote vectors pages */
3803 if (L1_IDX(va) == L1_IDX(vector_page)) {
3804 pmap_section_p_failures++;
3805 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x"
3806 " in pmap %p", va, pmap);
3810 * Examine the first PTE in the specified l2_bucket. Abort if this PTE
3811 * is either invalid, unused, or does not map the first 4KB physical
3812 * page within 1MB page.
3814 first_va = trunc_1mpage(va);
3815 l2b = pmap_get_l2_bucket(pmap, first_va);
3816 KASSERT(l2b != NULL, ("pmap_promote_section: trying to promote "
3817 "not existing l2 bucket"));
3818 firstptep = &l2b->l2b_kva[0];
3820 firstpte = *firstptep;
3821 if ((l2pte_pa(firstpte) & L1_S_OFFSET) != 0) {
3822 pmap_section_p_failures++;
3823 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x"
3824 " in pmap %p", va, pmap);
3828 if ((firstpte & (L2_S_PROTO | L2_S_REF)) != (L2_S_PROTO | L2_S_REF)) {
3829 pmap_section_p_failures++;
3830 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x"
3831 " in pmap %p", va, pmap);
3835 * ARM uses pv_entry to mark particular mapping WIRED so don't promote
3836 * unmanaged pages since it is impossible to determine, whether the
3837 * page is wired or not if there is no corresponding pv_entry.
3839 m = PHYS_TO_VM_PAGE(l2pte_pa(firstpte));
3840 if (m && ((m->oflags & VPO_UNMANAGED) != 0)) {
3841 pmap_section_p_failures++;
3842 CTR2(KTR_PMAP, "pmap_promote_section: failure for va %#x"
3843 " in pmap %p", va, pmap);
3846 first_pve = pmap_find_pv(&m->md, pmap, first_va);
3848 * PTE is modified only on write due to modified bit
3849 * emulation. If the entry is referenced and writable
3850 * then it is modified and we don't clear write enable.
3851 * Otherwise, writing is disabled in PTE anyway and
3852 * we just configure protections for the section mapping
3853 * that is going to be created.
3855 if ((first_pve->pv_flags & PVF_WRITE) != 0) {
3856 if (!L2_S_WRITABLE(firstpte)) {
3857 first_pve->pv_flags &= ~PVF_WRITE;
3858 prot &= ~VM_PROT_WRITE;
3861 prot &= ~VM_PROT_WRITE;
3863 if (!L2_S_EXECUTABLE(firstpte))
3864 prot &= ~VM_PROT_EXECUTE;
3867 * Examine each of the other PTEs in the specified l2_bucket.
3868 * Abort if this PTE maps an unexpected 4KB physical page or
3869 * does not have identical characteristics to the first PTE.
3871 pa = l2pte_pa(firstpte) + ((L2_PTE_NUM_TOTAL - 1) * PAGE_SIZE);
3872 old_va = L2_NEXT_BUCKET(first_va) - PAGE_SIZE;
3874 for (pte = (firstptep + L2_PTE_NUM_TOTAL - 1); pte > firstptep; pte--) {
3876 if (l2pte_pa(oldpte) != pa) {
3877 pmap_section_p_failures++;
3878 CTR2(KTR_PMAP, "pmap_promote_section: failure for "
3879 "va %#x in pmap %p", va, pmap);
3882 if ((oldpte & L2_S_PROMOTE) != (firstpte & L2_S_PROMOTE)) {
3883 pmap_section_p_failures++;
3884 CTR2(KTR_PMAP, "pmap_promote_section: failure for "
3885 "va %#x in pmap %p", va, pmap);
3888 oldm = PHYS_TO_VM_PAGE(l2pte_pa(oldpte));
3889 if (oldm && ((oldm->oflags & VPO_UNMANAGED) != 0)) {
3890 pmap_section_p_failures++;
3891 CTR2(KTR_PMAP, "pmap_promote_section: failure for "
3892 "va %#x in pmap %p", va, pmap);
3896 pve = pmap_find_pv(&oldm->md, pmap, old_va);
3898 pmap_section_p_failures++;
3899 CTR2(KTR_PMAP, "pmap_promote_section: failure for "
3900 "va %#x old_va %x - no pve", va, old_va);
3904 if (!L2_S_WRITABLE(oldpte) && (pve->pv_flags & PVF_WRITE))
3905 pve->pv_flags &= ~PVF_WRITE;
3906 if (pve->pv_flags != first_pve->pv_flags) {
3907 pmap_section_p_failures++;
3908 CTR2(KTR_PMAP, "pmap_promote_section: failure for "
3909 "va %#x in pmap %p", va, pmap);
3913 old_va -= PAGE_SIZE;
3917 * Promote the pv entries.
3919 pmap_pv_promote_section(pmap, first_va, l2pte_pa(firstpte));
3921 * Map the superpage.
3923 pmap_map_section(pmap, first_va, l2pte_pa(firstpte), prot, TRUE);
3925 * Invalidate all possible TLB mappings for small
3926 * pages within the newly created superpage.
3927 * Rely on the first PTE's attributes since they
3928 * have to be consistent across all of the base pages
3929 * within the superpage. If page is not executable it
3930 * is at least referenced.
3931 * The fastest way to do that is to invalidate whole
3932 * TLB at once instead of executing 256 CP15 TLB
3933 * invalidations by single entry. TLBs usually maintain
3934 * several dozen entries so loss of unrelated entries is
3935 * still a less agresive approach.
3937 if (L2_S_EXECUTABLE(firstpte))
3943 pmap_section_promotions++;
3944 CTR2(KTR_PMAP, "pmap_promote_section: success for va %#x"
3945 " in pmap %p", first_va, pmap);
3949 * Fills a l2_bucket with mappings to consecutive physical pages.
3952 pmap_fill_l2b(struct l2_bucket *l2b, pt_entry_t newpte)
3957 for (i = 0; i < L2_PTE_NUM_TOTAL; i++) {
3958 ptep = &l2b->l2b_kva[i];
3962 newpte += PAGE_SIZE;
3965 l2b->l2b_occupancy = L2_PTE_NUM_TOTAL;
3969 * Tries to demote a 1MB section mapping. If demotion fails, the
3970 * 1MB section mapping is invalidated.
3973 pmap_demote_section(pmap_t pmap, vm_offset_t va)
3975 struct l2_bucket *l2b;
3976 struct pv_entry *l1pdpve;
3977 struct md_page *pvh;
3978 pd_entry_t *pl1pd, l1pd, newl1pd;
3979 pt_entry_t *firstptep, newpte;
3983 PMAP_ASSERT_LOCKED(pmap);
3985 * According to assumptions described in pmap_promote_section,
3986 * kernel is and always should be mapped using 1MB section mappings.
3987 * What more, managed kernel pages were not to be promoted.
3989 KASSERT(pmap != pmap_kernel() && L1_IDX(va) != L1_IDX(vector_page),
3990 ("pmap_demote_section: forbidden section mapping"));
3992 va = trunc_1mpage(va);
3993 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3995 KASSERT((l1pd & L1_TYPE_MASK) == L1_S_PROTO,
3996 ("pmap_demote_section: not section or invalid section"));
3998 pa = l1pd & L1_S_FRAME;
3999 m = PHYS_TO_VM_PAGE(pa);
4000 KASSERT((m != NULL && (m->oflags & VPO_UNMANAGED) == 0),
4001 ("pmap_demote_section: no vm_page for selected superpage or"
4004 pvh = pa_to_pvh(pa);
4005 l1pdpve = pmap_find_pv(pvh, pmap, va);
4006 KASSERT(l1pdpve != NULL, ("pmap_demote_section: no pv entry for "
4009 l2b = pmap_get_l2_bucket(pmap, va);
4011 KASSERT((l1pdpve->pv_flags & PVF_WIRED) == 0,
4012 ("pmap_demote_section: No l2_bucket for wired mapping"));
4014 * Invalidate the 1MB section mapping and return
4015 * "failure" if the mapping was never accessed or the
4016 * allocation of the new l2_bucket fails.
4018 if (!L1_S_REFERENCED(l1pd) ||
4019 (l2b = pmap_alloc_l2_bucket(pmap, va)) == NULL) {
4020 /* Unmap and invalidate superpage. */
4021 pmap_remove_section(pmap, trunc_1mpage(va));
4022 CTR2(KTR_PMAP, "pmap_demote_section: failure for "
4023 "va %#x in pmap %p", va, pmap);
4029 * Now we should have corresponding l2_bucket available.
4030 * Let's process it to recreate 256 PTEs for each base page
4033 newpte = pa | L1_S_DEMOTE(l1pd);
4034 if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
4035 newpte |= pte_l2_s_cache_mode;
4038 * If the l2_bucket is new, initialize it.
4040 if (l2b->l2b_occupancy == 0)
4041 pmap_fill_l2b(l2b, newpte);
4043 firstptep = &l2b->l2b_kva[0];
4044 KASSERT(l2pte_pa(*firstptep) == (pa),
4045 ("pmap_demote_section: firstpte and newpte map different "
4046 "physical addresses"));
4048 * If the mapping has changed attributes, update the page table
4051 if ((*firstptep & L2_S_PROMOTE) != (L1_S_DEMOTE(l1pd)))
4052 pmap_fill_l2b(l2b, newpte);
4054 /* Demote PV entry */
4055 pmap_pv_demote_section(pmap, va, pa);
4058 newl1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | L1_C_PROTO;
4061 /* Invalidate old TLB mapping */
4062 if (L1_S_EXECUTABLE(l1pd))
4063 cpu_tlb_flushID_SE(va);
4064 else if (L1_S_REFERENCED(l1pd))
4065 cpu_tlb_flushD_SE(va);
4068 pmap_section_demotions++;
4069 CTR2(KTR_PMAP, "pmap_demote_section: success for va %#x"
4070 " in pmap %p", va, pmap);
4074 /***************************************************
4075 * page management routines.
4076 ***************************************************/
4079 * We are in a serious low memory condition. Resort to
4080 * drastic measures to free some pages so we can allocate
4081 * another pv entry chunk.
4084 pmap_pv_reclaim(pmap_t locked_pmap)
4087 struct pv_chunk *pc;
4088 struct l2_bucket *l2b = NULL;
4094 vm_page_t free, m, m_pc;
4096 int bit, field, freed, idx;
4098 PMAP_ASSERT_LOCKED(locked_pmap);
4101 TAILQ_INIT(&newtail);
4102 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
4104 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4105 if (pmap != pc->pc_pmap) {
4109 if (pmap != locked_pmap)
4113 /* Avoid deadlock and lock recursion. */
4114 if (pmap > locked_pmap)
4116 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
4118 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
4124 * Destroy every non-wired, 4 KB page mapping in the chunk.
4127 for (field = 0; field < _NPCM; field++) {
4128 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4129 inuse != 0; inuse &= ~(1UL << bit)) {
4130 bit = ffs(inuse) - 1;
4131 idx = field * sizeof(inuse) * NBBY + bit;
4132 pv = &pc->pc_pventry[idx];
4135 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
4136 if ((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO)
4138 if (pv->pv_flags & PVF_WIRED)
4141 l2b = pmap_get_l2_bucket(pmap, va);
4142 KASSERT(l2b != NULL, ("No l2 bucket"));
4143 ptep = &l2b->l2b_kva[l2pte_index(va)];
4144 m = PHYS_TO_VM_PAGE(l2pte_pa(*ptep));
4145 KASSERT((vm_offset_t)m >= KERNBASE,
4146 ("Trying to access non-existent page "
4147 "va %x pte %x", va, *ptep));
4150 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4151 if (TAILQ_EMPTY(&m->md.pv_list))
4152 vm_page_aflag_clear(m, PGA_WRITEABLE);
4153 pc->pc_map[field] |= 1UL << bit;
4159 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
4162 /* Every freed mapping is for a 4 KB page. */
4163 pmap->pm_stats.resident_count -= freed;
4164 PV_STAT(pv_entry_frees += freed);
4165 PV_STAT(pv_entry_spare += freed);
4166 pv_entry_count -= freed;
4167 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4168 for (field = 0; field < _NPCM; field++)
4169 if (pc->pc_map[field] != pc_freemask[field]) {
4170 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
4172 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
4175 * One freed pv entry in locked_pmap is
4178 if (pmap == locked_pmap)
4182 if (field == _NPCM) {
4183 PV_STAT(pv_entry_spare -= _NPCPV);
4184 PV_STAT(pc_chunk_count--);
4185 PV_STAT(pc_chunk_frees++);
4186 /* Entire chunk is free; return it. */
4187 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
4188 pmap_qremove((vm_offset_t)pc, 1);
4189 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
4194 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
4198 if (pmap != locked_pmap)
4205 * free the pv_entry back to the free list
4208 pmap_free_pv_entry(pmap_t pmap, pv_entry_t pv)
4210 struct pv_chunk *pc;
4211 int bit, field, idx;
4213 rw_assert(&pvh_global_lock, RA_WLOCKED);
4214 PMAP_ASSERT_LOCKED(pmap);
4215 PV_STAT(pv_entry_frees++);
4216 PV_STAT(pv_entry_spare++);
4218 pc = pv_to_chunk(pv);
4219 idx = pv - &pc->pc_pventry[0];
4220 field = idx / (sizeof(u_long) * NBBY);
4221 bit = idx % (sizeof(u_long) * NBBY);
4222 pc->pc_map[field] |= 1ul << bit;
4223 for (idx = 0; idx < _NPCM; idx++)
4224 if (pc->pc_map[idx] != pc_freemask[idx]) {
4226 * 98% of the time, pc is already at the head of the
4227 * list. If it isn't already, move it to the head.
4229 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
4231 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4232 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
4237 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4238 pmap_free_pv_chunk(pc);
4242 pmap_free_pv_chunk(struct pv_chunk *pc)
4246 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4247 PV_STAT(pv_entry_spare -= _NPCPV);
4248 PV_STAT(pc_chunk_count--);
4249 PV_STAT(pc_chunk_frees++);
4250 /* entire chunk is free, return it */
4251 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
4252 pmap_qremove((vm_offset_t)pc, 1);
4253 vm_page_unwire(m, 0);
4255 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
4260 pmap_get_pv_entry(pmap_t pmap, boolean_t try)
4262 static const struct timeval printinterval = { 60, 0 };
4263 static struct timeval lastprint;
4264 struct pv_chunk *pc;
4267 int bit, field, idx;
4269 rw_assert(&pvh_global_lock, RA_WLOCKED);
4270 PMAP_ASSERT_LOCKED(pmap);
4271 PV_STAT(pv_entry_allocs++);
4274 if (pv_entry_count > pv_entry_high_water)
4275 if (ratecheck(&lastprint, &printinterval))
4276 printf("%s: Approaching the limit on PV entries.\n",
4279 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4281 for (field = 0; field < _NPCM; field++) {
4282 if (pc->pc_map[field]) {
4283 bit = ffs(pc->pc_map[field]) - 1;
4287 if (field < _NPCM) {
4288 idx = field * sizeof(pc->pc_map[field]) * NBBY + bit;
4289 pv = &pc->pc_pventry[idx];
4290 pc->pc_map[field] &= ~(1ul << bit);
4291 /* If this was the last item, move it to tail */
4292 for (field = 0; field < _NPCM; field++)
4293 if (pc->pc_map[field] != 0) {
4294 PV_STAT(pv_entry_spare--);
4295 return (pv); /* not full, return */
4297 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4298 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4299 PV_STAT(pv_entry_spare--);
4304 * Access to the ptelist "pv_vafree" is synchronized by the pvh
4305 * global lock. If "pv_vafree" is currently non-empty, it will
4306 * remain non-empty until pmap_ptelist_alloc() completes.
4308 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
4309 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4312 PV_STAT(pc_chunk_tryfail++);
4315 m = pmap_pv_reclaim(pmap);
4319 PV_STAT(pc_chunk_count++);
4320 PV_STAT(pc_chunk_allocs++);
4321 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
4322 pmap_qenter((vm_offset_t)pc, &m, 1);
4324 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
4325 for (field = 1; field < _NPCM; field++)
4326 pc->pc_map[field] = pc_freemask[field];
4327 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4328 pv = &pc->pc_pventry[0];
4329 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4330 PV_STAT(pv_entry_spare += _NPCPV - 1);
4335 * Remove the given range of addresses from the specified map.
4337 * It is assumed that the start and end are properly
4338 * rounded to the page size.
4340 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
4342 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4344 struct l2_bucket *l2b;
4345 vm_offset_t next_bucket;
4346 pd_entry_t *pl1pd, l1pd;
4349 u_int mappings, is_exec, is_refd;
4354 * we lock in the pmap => pv_head direction
4357 rw_wlock(&pvh_global_lock);
4362 * Check for large page.
4364 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(sva)];
4366 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) {
4367 KASSERT((l1pd & L1_S_DOM_MASK) !=
4368 L1_S_DOM(PMAP_DOMAIN_KERNEL), ("pmap_remove: "
4369 "Trying to remove kernel section mapping"));
4371 * Are we removing the entire large page? If not,
4372 * demote the mapping and fall through.
4374 if (sva + L1_S_SIZE == L2_NEXT_BUCKET(sva) &&
4375 eva >= L2_NEXT_BUCKET(sva)) {
4376 pmap_remove_section(pmap, sva);
4377 sva = L2_NEXT_BUCKET(sva);
4379 } else if (!pmap_demote_section(pmap, sva)) {
4380 /* The large page mapping was destroyed. */
4381 sva = L2_NEXT_BUCKET(sva);
4386 * Do one L2 bucket's worth at a time.
4388 next_bucket = L2_NEXT_BUCKET(sva);
4389 if (next_bucket > eva)
4392 l2b = pmap_get_l2_bucket(pmap, sva);
4398 ptep = &l2b->l2b_kva[l2pte_index(sva)];
4401 while (sva < next_bucket) {
4410 * Nothing here, move along
4417 pmap->pm_stats.resident_count--;
4423 * Update flags. In a number of circumstances,
4424 * we could cluster a lot of these and do a
4425 * number of sequential pages in one go.
4427 if ((m = PHYS_TO_VM_PAGE(pa)) != NULL) {
4428 struct pv_entry *pve;
4430 pve = pmap_remove_pv(m, pmap, sva);
4432 is_exec = PTE_BEEN_EXECD(pte);
4433 is_refd = PTE_BEEN_REFD(pte);
4434 pmap_free_pv_entry(pmap, pve);
4440 if (pmap_is_current(pmap)) {
4442 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) {
4444 cpu_tlb_flushID_SE(sva);
4446 cpu_tlb_flushD_SE(sva);
4447 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE)
4456 pmap_free_l2_bucket(pmap, l2b, mappings);
4459 rw_wunlock(&pvh_global_lock);
4470 * Zero a given physical page by mapping it at a page hook point.
4471 * In doing the zero page op, the page we zero is mapped cachable, as with
4472 * StrongARM accesses to non-cached pages are non-burst making writing
4473 * _any_ bulk data very slow.
4476 pmap_zero_page_gen(vm_page_t m, int off, int size)
4478 struct czpages *czp;
4480 KASSERT(TAILQ_EMPTY(&m->md.pv_list),
4481 ("pmap_zero_page_gen: page has mappings"));
4483 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
4486 czp = &cpu_czpages[PCPU_GET(cpuid)];
4487 mtx_lock(&czp->lock);
4490 * Hook in the page, zero it.
4492 *czp->dstptep = L2_S_PROTO | phys | pte_l2_s_cache_mode | L2_S_REF;
4493 pmap_set_prot(czp->dstptep, VM_PROT_WRITE, 0);
4494 PTE_SYNC(czp->dstptep);
4495 cpu_tlb_flushD_SE(czp->dstva);
4498 if (off || size != PAGE_SIZE)
4499 bzero((void *)(czp->dstva + off), size);
4501 bzero_page(czp->dstva);
4504 * Although aliasing is not possible, if we use temporary mappings with
4505 * memory that will be mapped later as non-cached or with write-through
4506 * caches, we might end up overwriting it when calling wbinv_all. So
4507 * make sure caches are clean after the operation.
4509 cpu_idcache_wbinv_range(czp->dstva, size);
4510 pmap_l2cache_wbinv_range(czp->dstva, phys, size);
4512 mtx_unlock(&czp->lock);
4517 * pmap_zero_page zeros the specified hardware page by mapping
4518 * the page into KVM and using bzero to clear its contents.
4521 pmap_zero_page(vm_page_t m)
4523 pmap_zero_page_gen(m, 0, PAGE_SIZE);
4528 * pmap_zero_page_area zeros the specified hardware page by mapping
4529 * the page into KVM and using bzero to clear its contents.
4531 * off and size may not cover an area beyond a single hardware page.
4534 pmap_zero_page_area(vm_page_t m, int off, int size)
4537 pmap_zero_page_gen(m, off, size);
4542 * pmap_zero_page_idle zeros the specified hardware page by mapping
4543 * the page into KVM and using bzero to clear its contents. This
4544 * is intended to be called from the vm_pagezero process only and
4548 pmap_zero_page_idle(vm_page_t m)
4555 * pmap_copy_page copies the specified (machine independent)
4556 * page by mapping the page into virtual memory and using
4557 * bcopy to copy the page, one machine dependent page at a
4564 * Copy one physical page into another, by mapping the pages into
4565 * hook points. The same comment regarding cachability as in
4566 * pmap_zero_page also applies here.
4569 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4571 struct czpages *czp;
4574 czp = &cpu_czpages[PCPU_GET(cpuid)];
4575 mtx_lock(&czp->lock);
4578 * Map the pages into the page hook points, copy them, and purge the
4579 * cache for the appropriate page.
4581 *czp->srcptep = L2_S_PROTO | src | pte_l2_s_cache_mode | L2_S_REF;
4582 pmap_set_prot(czp->srcptep, VM_PROT_READ, 0);
4583 PTE_SYNC(czp->srcptep);
4584 cpu_tlb_flushD_SE(czp->srcva);
4585 *czp->dstptep = L2_S_PROTO | dst | pte_l2_s_cache_mode | L2_S_REF;
4586 pmap_set_prot(czp->dstptep, VM_PROT_READ | VM_PROT_WRITE, 0);
4587 PTE_SYNC(czp->dstptep);
4588 cpu_tlb_flushD_SE(czp->dstva);
4591 bcopy_page(czp->srcva, czp->dstva);
4594 * Although aliasing is not possible, if we use temporary mappings with
4595 * memory that will be mapped later as non-cached or with write-through
4596 * caches, we might end up overwriting it when calling wbinv_all. So
4597 * make sure caches are clean after the operation.
4599 cpu_idcache_wbinv_range(czp->dstva, PAGE_SIZE);
4600 pmap_l2cache_wbinv_range(czp->dstva, dst, PAGE_SIZE);
4602 mtx_unlock(&czp->lock);
4606 int unmapped_buf_allowed = 1;
4609 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4610 vm_offset_t b_offset, int xfersize)
4612 vm_page_t a_pg, b_pg;
4613 vm_offset_t a_pg_offset, b_pg_offset;
4615 struct czpages *czp;
4618 czp = &cpu_czpages[PCPU_GET(cpuid)];
4619 mtx_lock(&czp->lock);
4621 while (xfersize > 0) {
4622 a_pg = ma[a_offset >> PAGE_SHIFT];
4623 a_pg_offset = a_offset & PAGE_MASK;
4624 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4625 b_pg = mb[b_offset >> PAGE_SHIFT];
4626 b_pg_offset = b_offset & PAGE_MASK;
4627 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4628 *czp->srcptep = L2_S_PROTO | VM_PAGE_TO_PHYS(a_pg) |
4629 pte_l2_s_cache_mode | L2_S_REF;
4630 pmap_set_prot(czp->srcptep, VM_PROT_READ, 0);
4631 PTE_SYNC(czp->srcptep);
4632 cpu_tlb_flushD_SE(czp->srcva);
4633 *czp->dstptep = L2_S_PROTO | VM_PAGE_TO_PHYS(b_pg) |
4634 pte_l2_s_cache_mode | L2_S_REF;
4635 pmap_set_prot(czp->dstptep, VM_PROT_READ | VM_PROT_WRITE, 0);
4636 PTE_SYNC(czp->dstptep);
4637 cpu_tlb_flushD_SE(czp->dstva);
4639 bcopy((char *)czp->srcva + a_pg_offset, (char *)czp->dstva + b_pg_offset,
4641 cpu_idcache_wbinv_range(czp->dstva + b_pg_offset, cnt);
4642 pmap_l2cache_wbinv_range(czp->dstva + b_pg_offset,
4643 VM_PAGE_TO_PHYS(b_pg) + b_pg_offset, cnt);
4649 mtx_unlock(&czp->lock);
4654 pmap_copy_page(vm_page_t src, vm_page_t dst)
4657 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size &&
4658 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
4659 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
4662 pmap_copy_page_generic(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4666 * this routine returns true if a physical page resides
4667 * in the given pmap.
4670 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4672 struct md_page *pvh;
4677 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4678 ("pmap_page_exists_quick: page %p is not managed", m));
4680 rw_wlock(&pvh_global_lock);
4681 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4682 if (PV_PMAP(pv) == pmap) {
4690 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4691 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4692 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4693 if (PV_PMAP(pv) == pmap) {
4702 rw_wunlock(&pvh_global_lock);
4707 * pmap_page_wired_mappings:
4709 * Return the number of managed mappings to the given physical page
4713 pmap_page_wired_mappings(vm_page_t m)
4718 if ((m->oflags & VPO_UNMANAGED) != 0)
4720 rw_wlock(&pvh_global_lock);
4721 count = pmap_pvh_wired_mappings(&m->md, count);
4722 if ((m->flags & PG_FICTITIOUS) == 0) {
4723 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4726 rw_wunlock(&pvh_global_lock);
4731 * pmap_pvh_wired_mappings:
4733 * Return the updated number "count" of managed mappings that are wired.
4736 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4740 rw_assert(&pvh_global_lock, RA_WLOCKED);
4741 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4742 if ((pv->pv_flags & PVF_WIRED) != 0)
4749 * Returns TRUE if any of the given mappings were referenced and FALSE
4750 * otherwise. Both page and section mappings are supported.
4753 pmap_is_referenced_pvh(struct md_page *pvh)
4755 struct l2_bucket *l2b;
4762 rw_assert(&pvh_global_lock, RA_WLOCKED);
4764 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4767 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(pv->pv_va)];
4768 if ((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO)
4769 rv = L1_S_REFERENCED(*pl1pd);
4771 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
4772 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
4773 rv = L2_S_REFERENCED(*ptep);
4783 * pmap_is_referenced:
4785 * Return whether or not the specified physical page was referenced
4786 * in any physical maps.
4789 pmap_is_referenced(vm_page_t m)
4793 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4794 ("pmap_is_referenced: page %p is not managed", m));
4795 rw_wlock(&pvh_global_lock);
4796 rv = pmap_is_referenced_pvh(&m->md) ||
4797 ((m->flags & PG_FICTITIOUS) == 0 &&
4798 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4799 rw_wunlock(&pvh_global_lock);
4804 * pmap_ts_referenced:
4806 * Return the count of reference bits for a page, clearing all of them.
4809 pmap_ts_referenced(vm_page_t m)
4812 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4813 ("pmap_ts_referenced: page %p is not managed", m));
4814 return (pmap_clearbit(m, PVF_REF));
4818 * Returns TRUE if any of the given mappings were used to modify
4819 * physical memory. Otherwise, returns FALSE. Both page and 1MB section
4820 * mappings are supported.
4823 pmap_is_modified_pvh(struct md_page *pvh)
4826 struct l2_bucket *l2b;
4832 rw_assert(&pvh_global_lock, RA_WLOCKED);
4835 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4838 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(pv->pv_va)];
4839 if ((*pl1pd & L1_TYPE_MASK) == L1_S_PROTO)
4840 rv = L1_S_WRITABLE(*pl1pd);
4842 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
4843 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
4844 rv = L2_S_WRITABLE(*ptep);
4855 pmap_is_modified(vm_page_t m)
4859 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4860 ("pmap_is_modified: page %p is not managed", m));
4862 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4863 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4864 * is clear, no PTEs can have APX cleared.
4866 VM_OBJECT_ASSERT_WLOCKED(m->object);
4867 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4869 rw_wlock(&pvh_global_lock);
4870 rv = pmap_is_modified_pvh(&m->md) ||
4871 ((m->flags & PG_FICTITIOUS) == 0 &&
4872 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4873 rw_wunlock(&pvh_global_lock);
4878 * Apply the given advice to the specified range of addresses within the
4879 * given pmap. Depending on the advice, clear the referenced and/or
4880 * modified flags in each mapping.
4883 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4885 struct l2_bucket *l2b;
4886 struct pv_entry *pve;
4887 pd_entry_t *pl1pd, l1pd;
4888 pt_entry_t *ptep, opte, pte;
4889 vm_offset_t next_bucket;
4892 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4894 rw_wlock(&pvh_global_lock);
4896 for (; sva < eva; sva = next_bucket) {
4897 next_bucket = L2_NEXT_BUCKET(sva);
4898 if (next_bucket < sva)
4900 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(sva)];
4902 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) {
4903 if (pmap == pmap_kernel())
4905 if (!pmap_demote_section(pmap, sva)) {
4907 * The large page mapping was destroyed.
4912 * Unless the page mappings are wired, remove the
4913 * mapping to a single page so that a subsequent
4914 * access may repromote. Since the underlying
4915 * l2_bucket is fully populated, this removal
4916 * never frees an entire l2_bucket.
4918 l2b = pmap_get_l2_bucket(pmap, sva);
4919 KASSERT(l2b != NULL,
4920 ("pmap_advise: no l2 bucket for "
4921 "va 0x%#x, pmap 0x%p", sva, pmap));
4922 ptep = &l2b->l2b_kva[l2pte_index(sva)];
4924 m = PHYS_TO_VM_PAGE(l2pte_pa(*ptep));
4926 ("pmap_advise: no vm_page for demoted superpage"));
4927 pve = pmap_find_pv(&m->md, pmap, sva);
4928 KASSERT(pve != NULL,
4929 ("pmap_advise: no PV entry for managed mapping"));
4930 if ((pve->pv_flags & PVF_WIRED) == 0) {
4931 pmap_free_l2_bucket(pmap, l2b, 1);
4932 pve = pmap_remove_pv(m, pmap, sva);
4933 pmap_free_pv_entry(pmap, pve);
4936 if (pmap_is_current(pmap)) {
4937 if (PTE_BEEN_EXECD(opte))
4938 cpu_tlb_flushID_SE(sva);
4939 else if (PTE_BEEN_REFD(opte))
4940 cpu_tlb_flushD_SE(sva);
4944 if (next_bucket > eva)
4946 l2b = pmap_get_l2_bucket(pmap, sva);
4949 for (ptep = &l2b->l2b_kva[l2pte_index(sva)];
4950 sva != next_bucket; ptep++, sva += PAGE_SIZE) {
4952 if ((opte & L2_S_PROTO) == 0)
4954 m = PHYS_TO_VM_PAGE(l2pte_pa(opte));
4955 if (m == NULL || (m->oflags & VPO_UNMANAGED) != 0)
4957 else if (L2_S_WRITABLE(opte)) {
4958 if (advice == MADV_DONTNEED) {
4960 * Don't need to mark the page
4961 * dirty as it was already marked as
4962 * such in pmap_fault_fixup() or
4963 * pmap_enter_locked().
4964 * Just clear the state.
4972 } else if (L2_S_REFERENCED(opte)) {
4978 if (pmap_is_current(pmap)) {
4979 if (PTE_BEEN_EXECD(opte))
4980 cpu_tlb_flushID_SE(sva);
4981 else if (PTE_BEEN_REFD(opte))
4982 cpu_tlb_flushD_SE(sva);
4987 rw_wunlock(&pvh_global_lock);
4992 * Clear the modify bits on the specified physical page.
4995 pmap_clear_modify(vm_page_t m)
4998 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4999 ("pmap_clear_modify: page %p is not managed", m));
5000 VM_OBJECT_ASSERT_WLOCKED(m->object);
5001 KASSERT(!vm_page_xbusied(m),
5002 ("pmap_clear_modify: page %p is exclusive busied", m));
5005 * If the page is not PGA_WRITEABLE, then no mappings can be modified.
5006 * If the object containing the page is locked and the page is not
5007 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5009 if ((m->aflags & PGA_WRITEABLE) == 0)
5011 if (pmap_is_modified(m))
5012 pmap_clearbit(m, PVF_MOD);
5017 * Clear the write and modified bits in each of the given page's mappings.
5020 pmap_remove_write(vm_page_t m)
5022 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5023 ("pmap_remove_write: page %p is not managed", m));
5026 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5027 * set by another thread while the object is locked. Thus,
5028 * if PGA_WRITEABLE is clear, no page table entries need updating.
5030 VM_OBJECT_ASSERT_WLOCKED(m->object);
5031 if (vm_page_xbusied(m) || (m->aflags & PGA_WRITEABLE) != 0)
5032 pmap_clearbit(m, PVF_WRITE);
5037 * perform the pmap work for mincore
5040 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5042 struct l2_bucket *l2b;
5043 pd_entry_t *pl1pd, l1pd;
5044 pt_entry_t *ptep, pte;
5052 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(addr)];
5054 if ((l1pd & L1_TYPE_MASK) == L1_S_PROTO) {
5055 pa = (l1pd & L1_S_FRAME);
5056 val = MINCORE_SUPER | MINCORE_INCORE;
5057 if (L1_S_WRITABLE(l1pd))
5058 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5060 m = PHYS_TO_VM_PAGE(pa);
5061 if (m != NULL && (m->oflags & VPO_UNMANAGED) == 0)
5064 if (L1_S_REFERENCED(l1pd))
5065 val |= MINCORE_REFERENCED |
5066 MINCORE_REFERENCED_OTHER;
5069 l2b = pmap_get_l2_bucket(pmap, addr);
5074 ptep = &l2b->l2b_kva[l2pte_index(addr)];
5076 if (!l2pte_valid(pte)) {
5080 val = MINCORE_INCORE;
5081 if (L2_S_WRITABLE(pte))
5082 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5085 m = PHYS_TO_VM_PAGE(pa);
5086 if (m != NULL && (m->oflags & VPO_UNMANAGED) == 0)
5089 if (L2_S_REFERENCED(pte))
5090 val |= MINCORE_REFERENCED |
5091 MINCORE_REFERENCED_OTHER;
5094 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5095 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5096 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5097 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5101 PA_UNLOCK_COND(*locked_pa);
5107 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
5112 * Increase the starting virtual address of the given mapping if a
5113 * different alignment might result in more superpage mappings.
5116 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5117 vm_offset_t *addr, vm_size_t size)
5119 vm_offset_t superpage_offset;
5123 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5124 offset += ptoa(object->pg_color);
5125 superpage_offset = offset & PDRMASK;
5126 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5127 (*addr & PDRMASK) == superpage_offset)
5129 if ((*addr & PDRMASK) < superpage_offset)
5130 *addr = (*addr & ~PDRMASK) + superpage_offset;
5132 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5138 * Create a single section mapping.
5141 pmap_map_section(pmap_t pmap, vm_offset_t va, vm_offset_t pa, vm_prot_t prot,
5144 pd_entry_t *pl1pd, l1pd;
5147 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
5148 ("Not a valid section mapping"));
5150 fl = pte_l1_s_cache_mode;
5152 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
5153 l1pd = L1_S_PROTO | pa | L1_S_PROT(PTE_USER, prot) | fl |
5154 L1_S_DOM(pmap->pm_domain);
5156 /* Mark page referenced if this section is a result of a promotion. */
5169 * Link the L2 page table specified by l2pv.pv_pa into the L1
5170 * page table at the slot for "va".
5173 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
5175 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
5176 u_int slot = va >> L1_S_SHIFT;
5178 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
5180 #ifdef VERBOSE_INIT_ARM
5181 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
5184 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
5185 PTE_SYNC(&pde[slot]);
5187 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
5194 * Create a single page mapping.
5197 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
5200 pd_entry_t *pde = (pd_entry_t *) l1pt;
5204 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
5206 fl = l2s_mem_types[cache];
5208 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
5209 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
5211 ptep = (pt_entry_t *)kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
5214 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
5216 ptep[l2pte_index(va)] = L2_S_PROTO | pa | fl | L2_S_REF;
5217 pmap_set_prot(&ptep[l2pte_index(va)], prot, 0);
5218 PTE_SYNC(&ptep[l2pte_index(va)]);
5224 * Map a chunk of memory using the most efficient mappings
5225 * possible (section. large page, small page) into the
5226 * provided L1 and L2 tables at the specified virtual address.
5229 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
5230 vm_size_t size, int prot, int type)
5232 pd_entry_t *pde = (pd_entry_t *) l1pt;
5233 pt_entry_t *ptep, f1, f2s, f2l;
5237 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
5240 panic("pmap_map_chunk: no L1 table provided");
5242 #ifdef VERBOSE_INIT_ARM
5243 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
5244 "prot=0x%x type=%d\n", pa, va, size, resid, prot, type);
5247 f1 = l1_mem_types[type];
5248 f2l = l2l_mem_types[type];
5249 f2s = l2s_mem_types[type];
5254 /* See if we can use a section mapping. */
5255 if (L1_S_MAPPABLE_P(va, pa, resid)) {
5256 #ifdef VERBOSE_INIT_ARM
5259 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
5260 L1_S_PROT(PTE_KERNEL, prot | VM_PROT_EXECUTE) |
5261 f1 | L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_S_REF;
5262 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
5270 * Ok, we're going to use an L2 table. Make sure
5271 * one is actually in the corresponding L1 slot
5272 * for the current VA.
5274 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
5275 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
5277 ptep = (pt_entry_t *) kernel_pt_lookup(
5278 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
5280 panic("pmap_map_chunk: can't find L2 table for VA"
5282 /* See if we can use a L2 large page mapping. */
5283 if (L2_L_MAPPABLE_P(va, pa, resid)) {
5284 #ifdef VERBOSE_INIT_ARM
5287 for (i = 0; i < 16; i++) {
5288 ptep[l2pte_index(va) + i] =
5290 L2_L_PROT(PTE_KERNEL, prot) | f2l;
5291 PTE_SYNC(&ptep[l2pte_index(va) + i]);
5299 /* Use a small page mapping. */
5300 #ifdef VERBOSE_INIT_ARM
5303 ptep[l2pte_index(va)] = L2_S_PROTO | pa | f2s | L2_S_REF;
5304 pmap_set_prot(&ptep[l2pte_index(va)], prot, 0);
5305 PTE_SYNC(&ptep[l2pte_index(va)]);
5310 #ifdef VERBOSE_INIT_ARM
5318 pmap_dmap_iscurrent(pmap_t pmap)
5320 return(pmap_is_current(pmap));
5324 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5327 * Remember the memattr in a field that gets used to set the appropriate
5328 * bits in the PTEs as mappings are established.
5330 m->md.pv_memattr = ma;
5333 * It appears that this function can only be called before any mappings
5334 * for the page are established on ARM. If this ever changes, this code
5335 * will need to walk the pv_list and make each of the existing mappings
5336 * uncacheable, being careful to sync caches and PTEs (and maybe
5337 * invalidate TLB?) for any current mapping it modifies.
5339 if (TAILQ_FIRST(&m->md.pv_list) != NULL)
5340 panic("Can't change memattr on page with existing mappings");