2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/mutex.h>
40 #include <sys/sysctl.h>
42 #include <machine/bus.h>
43 #include <machine/cpu.h>
44 #include <machine/cpufunc.h>
45 #include <machine/resource.h>
46 #include <machine/fdt.h>
47 #include <machine/intr.h>
49 #include <dev/fdt/fdt_common.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
53 #include <dev/spibus/spi.h>
54 #include <dev/spibus/spibusvar.h>
56 #include <arm/broadcom/bcm2835/bcm2835_gpio.h>
57 #include <arm/broadcom/bcm2835/bcm2835_spireg.h>
58 #include <arm/broadcom/bcm2835/bcm2835_spivar.h>
60 #include "spibus_if.h"
62 static void bcm_spi_intr(void *);
66 bcm_spi_printr(device_t dev)
68 struct bcm_spi_softc *sc;
71 sc = device_get_softc(dev);
72 reg = BCM_SPI_READ(sc, SPI_CS);
73 device_printf(dev, "CS=%b\n", reg,
74 "\20\1CS0\2CS1\3CPHA\4CPOL\7CSPOL"
75 "\10TA\11DMAEN\12INTD\13INTR\14ADCS\15REN\16LEN"
76 "\21DONE\22RXD\23TXD\24RXR\25RXF\26CSPOL0\27CSPOL1"
77 "\30CSPOL2\31DMA_LEN\32LEN_LONG");
78 reg = BCM_SPI_READ(sc, SPI_CLK) & SPI_CLK_MASK;
83 device_printf(dev, "CLK=%uMhz/%d=%luhz\n",
84 SPI_CORE_CLK / 1000000, reg, SPI_CORE_CLK / reg);
85 reg = BCM_SPI_READ(sc, SPI_DLEN) & SPI_DLEN_MASK;
86 device_printf(dev, "DLEN=%d\n", reg);
87 reg = BCM_SPI_READ(sc, SPI_LTOH) & SPI_LTOH_MASK;
88 device_printf(dev, "LTOH=%d\n", reg);
89 reg = BCM_SPI_READ(sc, SPI_DC);
90 device_printf(dev, "DC=RPANIC=%#x RDREQ=%#x TPANIC=%#x TDREQ=%#x\n",
91 (reg & SPI_DC_RPANIC_MASK) >> SPI_DC_RPANIC_SHIFT,
92 (reg & SPI_DC_RDREQ_MASK) >> SPI_DC_RDREQ_SHIFT,
93 (reg & SPI_DC_TPANIC_MASK) >> SPI_DC_TPANIC_SHIFT,
94 (reg & SPI_DC_TDREQ_MASK) >> SPI_DC_TDREQ_SHIFT);
99 bcm_spi_modifyreg(struct bcm_spi_softc *sc, uint32_t off, uint32_t mask,
104 mtx_assert(&sc->sc_mtx, MA_OWNED);
105 reg = BCM_SPI_READ(sc, off);
108 BCM_SPI_WRITE(sc, off, reg);
112 bcm_spi_clock_proc(SYSCTL_HANDLER_ARGS)
114 struct bcm_spi_softc *sc;
118 sc = (struct bcm_spi_softc *)arg1;
121 clk = BCM_SPI_READ(sc, SPI_CLK);
126 clk = SPI_CORE_CLK / clk;
128 error = sysctl_handle_int(oidp, &clk, sizeof(clk), req);
129 if (error != 0 || req->newptr == NULL)
132 clk = SPI_CORE_CLK / clk;
140 BCM_SPI_WRITE(sc, SPI_CLK, clk);
147 bcm_spi_cs_bit_proc(SYSCTL_HANDLER_ARGS, uint32_t bit)
149 struct bcm_spi_softc *sc;
153 sc = (struct bcm_spi_softc *)arg1;
155 reg = BCM_SPI_READ(sc, SPI_CS);
157 reg = (reg & bit) ? 1 : 0;
159 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
160 if (error != 0 || req->newptr == NULL)
166 bcm_spi_modifyreg(sc, SPI_CS, bit, reg);
173 bcm_spi_cpol_proc(SYSCTL_HANDLER_ARGS)
176 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPOL));
180 bcm_spi_cpha_proc(SYSCTL_HANDLER_ARGS)
183 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPHA));
187 bcm_spi_cspol0_proc(SYSCTL_HANDLER_ARGS)
190 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL0));
194 bcm_spi_cspol1_proc(SYSCTL_HANDLER_ARGS)
197 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL1));
201 bcm_spi_sysctl_init(struct bcm_spi_softc *sc)
203 struct sysctl_ctx_list *ctx;
204 struct sysctl_oid *tree_node;
205 struct sysctl_oid_list *tree;
208 * Add system sysctl tree/handlers.
210 ctx = device_get_sysctl_ctx(sc->sc_dev);
211 tree_node = device_get_sysctl_tree(sc->sc_dev);
212 tree = SYSCTL_CHILDREN(tree_node);
213 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock",
214 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
215 bcm_spi_clock_proc, "IU", "SPI BUS clock frequency");
216 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpol",
217 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
218 bcm_spi_cpol_proc, "IU", "SPI BUS clock polarity");
219 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpha",
220 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
221 bcm_spi_cpha_proc, "IU", "SPI BUS clock phase");
222 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol0",
223 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
224 bcm_spi_cspol0_proc, "IU", "SPI BUS chip select 0 polarity");
225 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol1",
226 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
227 bcm_spi_cspol1_proc, "IU", "SPI BUS chip select 1 polarity");
231 bcm_spi_probe(device_t dev)
234 if (!ofw_bus_status_okay(dev))
237 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-spi"))
240 device_set_desc(dev, "BCM2708/2835 SPI controller");
242 return (BUS_PROBE_DEFAULT);
246 bcm_spi_attach(device_t dev)
248 struct bcm_spi_softc *sc;
252 if (device_get_unit(dev) != 0) {
253 device_printf(dev, "only one SPI controller supported\n");
257 sc = device_get_softc(dev);
260 /* Configure the GPIO pins to ALT0 function to enable SPI the pins. */
261 gpio = devclass_get_device(devclass_find("gpio"), 0);
263 device_printf(dev, "cannot find gpio0\n");
266 for (i = 0; i < nitems(bcm_spi_pins); i++)
267 bcm_gpio_set_alternate(gpio, bcm_spi_pins[i], BCM_GPIO_ALT0);
270 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
272 if (!sc->sc_mem_res) {
273 device_printf(dev, "cannot allocate memory window\n");
277 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
278 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
281 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
283 if (!sc->sc_irq_res) {
284 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
285 device_printf(dev, "cannot allocate interrupt\n");
289 /* Hook up our interrupt handler. */
290 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
291 NULL, bcm_spi_intr, sc, &sc->sc_intrhand)) {
292 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
293 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
294 device_printf(dev, "cannot setup the interrupt handler\n");
298 mtx_init(&sc->sc_mtx, "bcm_spi", NULL, MTX_DEF);
300 /* Add sysctl nodes. */
301 bcm_spi_sysctl_init(sc);
308 * Enable the SPI controller. Clear the rx and tx FIFO.
309 * Defaults to SPI mode 0.
311 BCM_SPI_WRITE(sc, SPI_CS, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO);
313 /* Set the SPI clock to 500Khz. */
314 BCM_SPI_WRITE(sc, SPI_CLK, SPI_CORE_CLK / 500000);
320 device_add_child(dev, "spibus", -1);
322 return (bus_generic_attach(dev));
326 bcm_spi_detach(device_t dev)
328 struct bcm_spi_softc *sc;
330 bus_generic_detach(dev);
332 sc = device_get_softc(dev);
333 mtx_destroy(&sc->sc_mtx);
335 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
337 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
339 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
345 bcm_spi_fill_fifo(struct bcm_spi_softc *sc)
347 struct spi_command *cmd;
348 uint32_t cs, written;
352 cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD);
353 while (sc->sc_written < sc->sc_len &&
354 cs == (SPI_CS_TA | SPI_CS_TXD)) {
355 data = (uint8_t *)cmd->tx_cmd;
356 written = sc->sc_written++;
357 if (written >= cmd->tx_cmd_sz) {
358 data = (uint8_t *)cmd->tx_data;
359 written -= cmd->tx_cmd_sz;
361 BCM_SPI_WRITE(sc, SPI_FIFO, data[written]);
362 cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD);
367 bcm_spi_drain_fifo(struct bcm_spi_softc *sc)
369 struct spi_command *cmd;
374 cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD;
375 while (sc->sc_read < sc->sc_len && cs == SPI_CS_RXD) {
376 data = (uint8_t *)cmd->rx_cmd;
377 read = sc->sc_read++;
378 if (read >= cmd->rx_cmd_sz) {
379 data = (uint8_t *)cmd->rx_data;
380 read -= cmd->rx_cmd_sz;
382 data[read] = BCM_SPI_READ(sc, SPI_FIFO) & 0xff;
383 cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD;
388 bcm_spi_intr(void *arg)
390 struct bcm_spi_softc *sc;
392 sc = (struct bcm_spi_softc *)arg;
395 /* Filter stray interrupts. */
396 if ((sc->sc_flags & BCM_SPI_BUSY) == 0) {
401 /* TX - Fill up the FIFO. */
402 bcm_spi_fill_fifo(sc);
404 /* RX - Drain the FIFO. */
405 bcm_spi_drain_fifo(sc);
407 /* Check for end of transfer. */
408 if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) {
409 /* Disable interrupts and the SPI engine. */
410 bcm_spi_modifyreg(sc, SPI_CS,
411 SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0);
419 bcm_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
421 struct bcm_spi_softc *sc;
424 sc = device_get_softc(dev);
426 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
427 ("TX/RX command sizes should be equal"));
428 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
429 ("TX/RX data sizes should be equal"));
433 /* If the controller is in use wait until it is available. */
434 while (sc->sc_flags & BCM_SPI_BUSY)
435 mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", 0);
437 /* Now we have control over SPI controller. */
438 sc->sc_flags = BCM_SPI_BUSY;
440 /* Clear the FIFO. */
441 bcm_spi_modifyreg(sc, SPI_CS,
442 SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO,
443 SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO);
445 /* Get the proper chip select for this child. */
446 spibus_get_cs(child, &cs);
447 if (cs < 0 || cs > 2) {
449 "Invalid chip select %d requested by %s\n", cs,
450 device_get_nameunit(child));
455 /* Save a pointer to the SPI command. */
459 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz;
462 * Set the CS for this transaction, enable interrupts and announce
463 * we're ready to tx. This will kick off the first interrupt.
465 bcm_spi_modifyreg(sc, SPI_CS,
466 SPI_CS_MASK | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD,
467 cs | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD);
469 /* Wait for the transaction to complete. */
470 err = mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", hz * 2);
472 /* Make sure the SPI engine and interrupts are disabled. */
473 bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0);
475 /* Clear the controller flags. */
479 * Check for transfer timeout. The SPI controller doesn't
482 if (err == EWOULDBLOCK) {
483 device_printf(sc->sc_dev, "SPI error\n");
493 bcm_spi_get_node(device_t bus, device_t dev)
496 /* We only have one child, the SPI bus, which needs our own node. */
497 return (ofw_bus_get_node(bus));
500 static device_method_t bcm_spi_methods[] = {
501 /* Device interface */
502 DEVMETHOD(device_probe, bcm_spi_probe),
503 DEVMETHOD(device_attach, bcm_spi_attach),
504 DEVMETHOD(device_detach, bcm_spi_detach),
507 DEVMETHOD(spibus_transfer, bcm_spi_transfer),
509 /* ofw_bus interface */
510 DEVMETHOD(ofw_bus_get_node, bcm_spi_get_node),
515 static devclass_t bcm_spi_devclass;
517 static driver_t bcm_spi_driver = {
520 sizeof(struct bcm_spi_softc),
523 DRIVER_MODULE(bcm2835_spi, simplebus, bcm_spi_driver, bcm_spi_devclass, 0, 0);