2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3 * Copyright (c) 2014 Steven Lawrance <stl@koffein.net>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 * Analog PLL and power regulator driver for Freescale i.MX6 family of SoCs.
33 * Also, temperature montoring and cpu frequency control. It was Freescale who
34 * kitchen-sinked this device, not us. :)
36 * We don't really do anything with analog PLLs, but the registers for
37 * controlling them belong to the same block as the power regulator registers.
38 * Since the newbus hierarchy makes it hard for anyone other than us to get at
39 * them, we just export a couple public functions to allow the imx6 CCM clock
40 * driver to read and write those registers.
42 * We also don't do anything about power regulation yet, but when the need
43 * arises, this would be the place for that code to live.
45 * I have no idea where the "anatop" name comes from. It's in the standard DTS
46 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes
47 * from Freescale, but it's not in the SoC manual.
49 * Note that temperature values throughout this code are handled in two types of
50 * units. Items with '_cnt' in the name use the hardware temperature count
51 * units (higher counts are lower temperatures). Items with '_val' in the name
52 * are deci-Celcius, which are converted to/from deci-Kelvins in the sysctl
53 * handlers (dK is the standard unit for temperature in sysctl).
56 #include <sys/param.h>
57 #include <sys/systm.h>
58 #include <sys/callout.h>
59 #include <sys/kernel.h>
60 #include <sys/limits.h>
61 #include <sys/sysctl.h>
62 #include <sys/module.h>
66 #include <dev/ofw/ofw_bus.h>
67 #include <dev/ofw/ofw_bus_subr.h>
69 #include <machine/bus.h>
70 #include <machine/fdt.h>
72 #include <arm/arm/mpcore_timervar.h>
73 #include <arm/freescale/fsl_ocotpreg.h>
74 #include <arm/freescale/fsl_ocotpvar.h>
75 #include <arm/freescale/imx/imx_ccmvar.h>
76 #include <arm/freescale/imx/imx6_anatopreg.h>
77 #include <arm/freescale/imx/imx6_anatopvar.h>
79 static SYSCTL_NODE(_hw, OID_AUTO, imx6, CTLFLAG_RW, NULL, "i.MX6 container");
81 static struct resource_spec imx6_anatop_spec[] = {
82 { SYS_RES_MEMORY, 0, RF_ACTIVE },
83 { SYS_RES_IRQ, 0, RF_ACTIVE },
89 struct imx6_anatop_softc {
91 struct resource *res[2];
92 struct intr_config_hook
100 uint32_t cpu_maxmhz_hw;
101 boolean_t cpu_overclock_enable;
102 boolean_t cpu_init_done;
105 uint32_t temp_high_val;
106 uint32_t temp_high_cnt;
107 uint32_t temp_last_cnt;
108 uint32_t temp_room_cnt;
109 struct callout temp_throttle_callout;
110 sbintime_t temp_throttle_delay;
111 uint32_t temp_throttle_reset_cnt;
112 uint32_t temp_throttle_trigger_cnt;
113 uint32_t temp_throttle_val;
116 static struct imx6_anatop_softc *imx6_anatop_sc;
119 * Table of "operating points".
120 * These are combinations of frequency and voltage blessed by Freescale.
121 * While the datasheet says the ARM voltage can be as low as 925mV at
122 * 396MHz, it also says that the ARM and SOC voltages can't differ by
123 * more than 200mV, and the minimum SOC voltage is 1150mV, so that
124 * dictates the 950mV entry in this table.
129 } imx6_oppt_table[] = {
138 * Table of CPU max frequencies. This is used to translate the max frequency
139 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked
140 * up in the operating points table.
142 static uint32_t imx6_ocotp_mhz_tab[] = {792, 852, 996, 1200};
144 #define TZ_ZEROC 2732 /* deci-Kelvin <-> deci-Celcius offset. */
147 imx6_anatop_read_4(bus_size_t offset)
150 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_read_4 sc NULL"));
152 return (bus_read_4(imx6_anatop_sc->res[MEMRES], offset));
156 imx6_anatop_write_4(bus_size_t offset, uint32_t value)
159 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_write_4 sc NULL"));
161 bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value);
165 vdd_set(struct imx6_anatop_softc *sc, int mv)
167 int newtarg, newtargSoc, oldtarg;
168 uint32_t delay, pmureg;
169 static boolean_t init_done = false;
172 * The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM
173 * can't be more than 50mV above or 200mV below them. We keep them the
174 * same except in the case of the lowest operating point, which is
175 * handled as a special case below.
178 pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE);
179 oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK;
181 /* Convert mV to target value. Clamp target to valid range. */
187 newtarg = (mv - 700) / 25;
190 * The SOC voltage can't go below 1150mV, and thus because of the 200mV
191 * rule, the ARM voltage can't go below 950mV. The 950 is encoded in
192 * our oppt table, here we handle the SOC 1150 rule as a special case.
195 newtargSoc = (newtarg < 18) ? 18 : newtarg;
198 * The first time through the 3 voltages might not be equal so use a
199 * long conservative delay. After that we need to delay 3uS for every
200 * 25mV step upward; we actually delay 6uS because empirically, it works
201 * and the 3uS per step recommended by the docs doesn't (3uS fails when
202 * going from 400->1200, but works for smaller changes).
205 if (newtarg == oldtarg)
207 else if (newtarg > oldtarg)
208 delay = (newtarg - oldtarg) * 6;
212 delay = (700 / 25) * 6;
217 * Make the change and wait for it to take effect.
219 pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK |
220 IMX6_ANALOG_PMU_REG1_TARG_MASK |
221 IMX6_ANALOG_PMU_REG2_TARG_MASK);
223 pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT;
224 pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT;
225 pmureg |= newtargSoc << IMX6_ANALOG_PMU_REG2_TARG_SHIFT;
227 imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg);
229 sc->cpu_curmv = newtarg * 25 + 700;
232 static inline uint32_t
233 cpufreq_mhz_from_div(struct imx6_anatop_softc *sc, uint32_t corediv,
237 return ((sc->refosc_mhz * (plldiv / 2)) / (corediv + 1));
241 cpufreq_mhz_to_div(struct imx6_anatop_softc *sc, uint32_t cpu_mhz,
242 uint32_t *corediv, uint32_t *plldiv)
245 *corediv = (cpu_mhz < 650) ? 1 : 0;
246 *plldiv = ((*corediv + 1) * cpu_mhz) / (sc->refosc_mhz / 2);
249 static inline uint32_t
250 cpufreq_actual_mhz(struct imx6_anatop_softc *sc, uint32_t cpu_mhz)
252 uint32_t corediv, plldiv;
254 cpufreq_mhz_to_div(sc, cpu_mhz, &corediv, &plldiv);
255 return (cpufreq_mhz_from_div(sc, corediv, plldiv));
259 cpufreq_nearest_oppt(struct imx6_anatop_softc *sc, uint32_t cpu_newmhz)
261 int d, diff, i, nearest;
263 if (cpu_newmhz > sc->cpu_maxmhz_hw && !sc->cpu_overclock_enable)
264 cpu_newmhz = sc->cpu_maxmhz_hw;
268 for (i = 0; i < nitems(imx6_oppt_table); ++i) {
269 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz);
275 return (&imx6_oppt_table[nearest]);
279 cpufreq_set_clock(struct imx6_anatop_softc * sc, struct oppt *op)
281 uint32_t corediv, plldiv, timeout, wrk32;
283 /* If increasing the frequency, we must first increase the voltage. */
284 if (op->mhz > sc->cpu_curmhz) {
289 * I can't find a documented procedure for changing the ARM PLL divisor,
290 * but some trial and error came up with this:
291 * - Set the bypass clock source to REF_CLK_24M (source #0).
292 * - Set the PLL into bypass mode; cpu should now be running at 24mhz.
293 * - Change the divisor.
294 * - Wait for the LOCK bit to come on; it takes ~50 loop iterations.
295 * - Turn off bypass mode; cpu should now be running at the new speed.
297 cpufreq_mhz_to_div(sc, op->mhz, &corediv, &plldiv);
298 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR,
299 IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK);
300 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_SET,
301 IMX6_ANALOG_CCM_PLL_ARM_BYPASS);
303 wrk32 = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM);
304 wrk32 &= ~IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK;
306 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM, wrk32);
309 while ((imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) &
310 IMX6_ANALOG_CCM_PLL_ARM_LOCK) == 0)
312 panic("imx6_set_cpu_clock(): PLL never locked");
314 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR,
315 IMX6_ANALOG_CCM_PLL_ARM_BYPASS);
316 imx_ccm_set_cacrr(corediv);
318 /* If lowering the frequency, it is now safe to lower the voltage. */
319 if (op->mhz < sc->cpu_curmhz)
321 sc->cpu_curmhz = op->mhz;
323 /* Tell the mpcore timer that its frequency has changed. */
324 arm_tmr_change_frequency(
325 cpufreq_actual_mhz(sc, sc->cpu_curmhz) * 1000000 / 2);
329 cpufreq_sysctl_minmhz(SYSCTL_HANDLER_ARGS)
331 struct imx6_anatop_softc *sc;
338 temp = sc->cpu_minmhz;
339 err = sysctl_handle_int(oidp, &temp, 0, req);
340 if (err != 0 || req->newptr == NULL)
343 op = cpufreq_nearest_oppt(sc, temp);
344 if (op->mhz > sc->cpu_maxmhz)
346 else if (op->mhz == sc->cpu_minmhz)
350 * Value changed, update softc. If the new min is higher than the
351 * current speed, raise the current speed to match.
353 sc->cpu_minmhz = op->mhz;
354 if (sc->cpu_minmhz > sc->cpu_curmhz) {
355 cpufreq_set_clock(sc, op);
361 cpufreq_sysctl_maxmhz(SYSCTL_HANDLER_ARGS)
363 struct imx6_anatop_softc *sc;
370 temp = sc->cpu_maxmhz;
371 err = sysctl_handle_int(oidp, &temp, 0, req);
372 if (err != 0 || req->newptr == NULL)
375 op = cpufreq_nearest_oppt(sc, temp);
376 if (op->mhz < sc->cpu_minmhz)
378 else if (op->mhz == sc->cpu_maxmhz)
382 * Value changed, update softc and hardware. The hardware update is
383 * unconditional. We always try to run at max speed, so any change of
384 * the max means we need to change the current speed too, regardless of
385 * whether it is higher or lower than the old max.
387 sc->cpu_maxmhz = op->mhz;
388 cpufreq_set_clock(sc, op);
394 cpufreq_initialize(struct imx6_anatop_softc *sc)
399 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6),
400 OID_AUTO, "cpu_mhz", CTLFLAG_RD, &sc->cpu_curmhz, 0,
403 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6),
404 OID_AUTO, "cpu_minmhz", CTLTYPE_INT | CTLFLAG_RWTUN, sc, 0,
405 cpufreq_sysctl_minmhz, "IU", "Minimum CPU frequency");
407 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6),
408 OID_AUTO, "cpu_maxmhz", CTLTYPE_INT | CTLFLAG_RWTUN, sc, 0,
409 cpufreq_sysctl_maxmhz, "IU", "Maximum CPU frequency");
411 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6),
412 OID_AUTO, "cpu_maxmhz_hw", CTLFLAG_RD, &sc->cpu_maxmhz_hw, 0,
413 "Maximum CPU frequency allowed by hardware");
415 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6),
416 OID_AUTO, "cpu_overclock_enable", CTLFLAG_RWTUN,
417 &sc->cpu_overclock_enable, 0,
418 "Allow setting CPU frequency higher than cpu_maxmhz_hw");
421 * XXX 24mhz shouldn't be hard-coded, should get this from imx6_ccm
422 * (even though in the real world it will always be 24mhz). Oh wait a
423 * sec, I never wrote imx6_ccm.
428 * Get the maximum speed this cpu can be set to. The values in the
429 * OCOTP CFG3 register are not documented in the reference manual.
430 * The following info was in an archived email found via web search:
431 * - 2b'11: 1200000000Hz;
432 * - 2b'10: 996000000Hz;
433 * - 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
434 * - 2b'00: 792000000Hz;
435 * The default hardware max speed can be overridden by a tunable.
437 cfg3speed = (fsl_ocotp_read_4(FSL_OCOTP_CFG3) &
438 FSL_OCOTP_CFG3_SPEED_MASK) >> FSL_OCOTP_CFG3_SPEED_SHIFT;
439 sc->cpu_maxmhz_hw = imx6_ocotp_mhz_tab[cfg3speed];
440 sc->cpu_maxmhz = sc->cpu_maxmhz_hw;
442 TUNABLE_INT_FETCH("hw.imx6.cpu_overclock_enable",
443 &sc->cpu_overclock_enable);
445 TUNABLE_INT_FETCH("hw.imx6.cpu_minmhz", &sc->cpu_minmhz);
446 op = cpufreq_nearest_oppt(sc, sc->cpu_minmhz);
447 sc->cpu_minmhz = op->mhz;
448 sc->cpu_minmv = op->mv;
450 TUNABLE_INT_FETCH("hw.imx6.cpu_maxmhz", &sc->cpu_maxmhz);
451 op = cpufreq_nearest_oppt(sc, sc->cpu_maxmhz);
452 sc->cpu_maxmhz = op->mhz;
453 sc->cpu_maxmv = op->mv;
456 * Set the CPU to maximum speed.
458 * We won't have thermal throttling until interrupts are enabled, but we
459 * want to run at full speed through all the device init stuff. This
460 * basically assumes that a single core can't overheat before interrupts
461 * are enabled; empirical testing shows that to be a safe assumption.
463 cpufreq_set_clock(sc, op);
466 static inline uint32_t
467 temp_from_count(struct imx6_anatop_softc *sc, uint32_t count)
470 return (((sc->temp_high_val - (count - sc->temp_high_cnt) *
471 (sc->temp_high_val - 250) /
472 (sc->temp_room_cnt - sc->temp_high_cnt))));
475 static inline uint32_t
476 temp_to_count(struct imx6_anatop_softc *sc, uint32_t temp)
479 return ((sc->temp_room_cnt - sc->temp_high_cnt) *
480 (sc->temp_high_val - temp) / (sc->temp_high_val - 250) +
485 temp_update_count(struct imx6_anatop_softc *sc)
489 val = imx6_anatop_read_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0);
490 if (!(val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_VALID))
493 (val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) >>
494 IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT;
498 temp_sysctl_handler(SYSCTL_HANDLER_ARGS)
500 struct imx6_anatop_softc *sc = arg1;
503 temp_update_count(sc);
505 t = temp_from_count(sc, sc->temp_last_cnt) + TZ_ZEROC;
507 return (sysctl_handle_int(oidp, &t, 0, req));
511 temp_throttle_sysctl_handler(SYSCTL_HANDLER_ARGS)
513 struct imx6_anatop_softc *sc = arg1;
517 temp = sc->temp_throttle_val + TZ_ZEROC;
518 err = sysctl_handle_int(oidp, &temp, 0, req);
522 if (err != 0 || req->newptr == NULL || temp == sc->temp_throttle_val)
525 /* Value changed, update counts in softc and hardware. */
526 sc->temp_throttle_val = temp;
527 sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val);
528 sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 100);
529 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR,
530 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK);
531 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET,
532 (sc->temp_throttle_trigger_cnt <<
533 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT));
538 tempmon_gofast(struct imx6_anatop_softc *sc)
541 if (sc->cpu_curmhz < sc->cpu_maxmhz) {
542 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_maxmhz));
547 tempmon_goslow(struct imx6_anatop_softc *sc)
550 if (sc->cpu_curmhz > sc->cpu_minmhz) {
551 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_minmhz));
556 tempmon_intr(void *arg)
558 struct imx6_anatop_softc *sc = arg;
561 * XXX Note that this code doesn't currently run (for some mysterious
562 * reason we just never get an interrupt), so the real monitoring is
563 * done by tempmon_throttle_check().
566 /* XXX Schedule callout to speed back up eventually. */
567 return (FILTER_HANDLED);
571 tempmon_throttle_check(void *arg)
573 struct imx6_anatop_softc *sc = arg;
575 /* Lower counts are higher temperatures. */
576 if (sc->temp_last_cnt < sc->temp_throttle_trigger_cnt)
578 else if (sc->temp_last_cnt > (sc->temp_throttle_reset_cnt))
581 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay,
582 0, tempmon_throttle_check, sc, 0);
587 initialize_tempmon(struct imx6_anatop_softc *sc)
592 * Fetch calibration data: a sensor count at room temperature (25C),
593 * a sensor count at a high temperature, and that temperature
595 cal = fsl_ocotp_read_4(FSL_OCOTP_ANA1);
596 sc->temp_room_cnt = (cal & 0xFFF00000) >> 20;
597 sc->temp_high_cnt = (cal & 0x000FFF00) >> 8;
598 sc->temp_high_val = (cal & 0x000000FF) * 10;
601 * Throttle to a lower cpu freq at 10C below the "hot" temperature, and
602 * reset back to max cpu freq at 5C below the trigger.
604 sc->temp_throttle_val = sc->temp_high_val - 100;
605 sc->temp_throttle_trigger_cnt =
606 temp_to_count(sc, sc->temp_throttle_val);
607 sc->temp_throttle_reset_cnt =
608 temp_to_count(sc, sc->temp_throttle_val - 50);
611 * Set the sensor to sample automatically at 16Hz (32.768KHz/0x800), set
612 * the throttle count, and begin making measurements.
614 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE1, 0x0800);
615 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0,
616 (sc->temp_throttle_trigger_cnt <<
617 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT) |
618 IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE);
621 * XXX Note that the alarm-interrupt feature isn't working yet, so
622 * we'll use a callout handler to check at 10Hz. Make sure we have an
623 * initial temperature reading before starting up the callouts so we
624 * don't get a bogus reading of zero.
626 while (sc->temp_last_cnt == 0)
627 temp_update_count(sc);
628 sc->temp_throttle_delay = 100 * SBT_1MS;
629 callout_init(&sc->temp_throttle_callout, 0);
630 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay,
631 0, tempmon_throttle_check, sc, 0);
633 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6),
634 OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, sc, 0,
635 temp_sysctl_handler, "IK", "Current die temperature");
636 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6),
637 OID_AUTO, "throttle_temperature", CTLTYPE_INT | CTLFLAG_RW, sc,
638 0, temp_throttle_sysctl_handler, "IK",
639 "Throttle CPU when exceeding this temperature");
643 intr_setup(void *arg)
645 struct imx6_anatop_softc *sc;
648 bus_setup_intr(sc->dev, sc->res[IRQRES], INTR_TYPE_MISC | INTR_MPSAFE,
649 tempmon_intr, NULL, sc, &sc->temp_intrhand);
650 config_intrhook_disestablish(&sc->intr_setup_hook);
654 imx6_anatop_new_pass(device_t dev)
656 struct imx6_anatop_softc *sc;
657 const int cpu_init_pass = BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE;
660 * We attach during BUS_PASS_BUS (because some day we will be a
661 * simplebus that has regulator devices as children), but some of our
662 * init work cannot be done until BUS_PASS_CPU (we rely on other devices
663 * that attach on the CPU pass).
665 sc = device_get_softc(dev);
666 if (!sc->cpu_init_done && bus_current_pass >= cpu_init_pass) {
667 sc->cpu_init_done = true;
668 cpufreq_initialize(sc);
669 initialize_tempmon(sc);
671 device_printf(sc->dev, "CPU %uMHz @ %umV\n",
672 sc->cpu_curmhz, sc->cpu_curmv);
675 bus_generic_new_pass(dev);
679 imx6_anatop_detach(device_t dev)
682 /* This device can never detach. */
687 imx6_anatop_attach(device_t dev)
689 struct imx6_anatop_softc *sc;
692 sc = device_get_softc(dev);
695 /* Allocate bus_space resources. */
696 if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) {
697 device_printf(dev, "Cannot allocate resources\n");
702 sc->intr_setup_hook.ich_func = intr_setup;
703 sc->intr_setup_hook.ich_arg = sc;
704 config_intrhook_establish(&sc->intr_setup_hook);
706 SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev),
707 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
708 OID_AUTO, "cpu_voltage", CTLFLAG_RD,
709 &sc->cpu_curmv, 0, "Current CPU voltage in millivolts");
714 * Other code seen on the net sets this SELFBIASOFF flag around the same
715 * time the temperature sensor is set up, although it's unclear how the
716 * two are related (if at all).
718 imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET,
719 IMX6_ANALOG_PMU_MISC0_SELFBIASOFF);
722 * Some day, when we're ready to deal with the actual anatop regulators
723 * that are described in fdt data as children of this "bus", this would
724 * be the place to invoke a simplebus helper routine to instantiate the
725 * children from the fdt data.
733 bus_release_resources(dev, imx6_anatop_spec, sc->res);
740 pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd)
746 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)
749 reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE);
750 reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \
751 IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT);
752 reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT);
753 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg);
754 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_NUM, mfn);
755 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_DENOM, mfd);
761 imx6_anatop_probe(device_t dev)
764 if (!ofw_bus_status_okay(dev))
767 if (ofw_bus_is_compatible(dev, "fsl,imx6q-anatop") == 0)
770 device_set_desc(dev, "Freescale i.MX6 Analog PLLs and Power");
772 return (BUS_PROBE_DEFAULT);
778 uint32_t corediv, plldiv;
780 corediv = imx_ccm_get_cacrr();
781 plldiv = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) &
782 IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK;
783 return (cpufreq_mhz_from_div(imx6_anatop_sc, corediv, plldiv));
786 static device_method_t imx6_anatop_methods[] = {
787 /* Device interface */
788 DEVMETHOD(device_probe, imx6_anatop_probe),
789 DEVMETHOD(device_attach, imx6_anatop_attach),
790 DEVMETHOD(device_detach, imx6_anatop_detach),
793 DEVMETHOD(bus_new_pass, imx6_anatop_new_pass),
798 static driver_t imx6_anatop_driver = {
801 sizeof(struct imx6_anatop_softc)
804 static devclass_t imx6_anatop_devclass;
806 EARLY_DRIVER_MODULE(imx6_anatop, simplebus, imx6_anatop_driver,
807 imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
808 EARLY_DRIVER_MODULE(imx6_anatop, ofwbus, imx6_anatop_driver,
809 imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);