2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include "opt_platform.h"
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/reboot.h>
39 #include <machine/bus.h>
40 #include <machine/devmap.h>
41 #include <machine/intr.h>
42 #include <machine/machdep.h>
44 #include <arm/arm/mpcore_timervar.h>
45 #include <arm/freescale/imx/imx6_anatopreg.h>
46 #include <arm/freescale/imx/imx6_anatopvar.h>
47 #include <arm/freescale/imx/imx_machdep.h>
49 #include <dev/fdt/fdt_common.h>
50 #include <dev/ofw/openfirm.h>
52 struct fdt_fixup_entry fdt_fixup_table[] = {
56 static uint32_t gpio1_node;
59 * Work around the linux workaround for imx6 erratum 006687, in which some
60 * ethernet interrupts don't go to the GPC and thus won't wake the system from
61 * Wait mode. We don't use Wait mode (which halts the GIC, leaving only GPC
62 * interrupts able to wake the system), so we don't experience the bug at all.
63 * The linux workaround is to reconfigure GPIO1_6 as the ENET interrupt by
64 * writing magic values to an undocumented IOMUX register, then letting the gpio
65 * interrupt driver notify the ethernet driver. We'll be able to do all that
66 * (even though we don't need to) once the INTRNG project is committed and the
67 * imx_gpio driver becomes an interrupt driver. Until then, this crazy little
68 * workaround watches for requests to map an interrupt 6 with the interrupt
69 * controller node referring to gpio1, and it substitutes the proper ffec
73 imx6_decode_fdt(uint32_t iparent, uint32_t *intr, int *interrupt,
77 if (fdt32_to_cpu(intr[0]) == 6 &&
78 OF_node_from_xref(iparent) == gpio1_node) {
80 *trig = INTR_TRIGGER_CONFORM;
81 *pol = INTR_POLARITY_CONFORM;
84 return (gic_decode_fdt(iparent, intr, interrupt, trig, pol));
87 fdt_pic_decode_t fdt_pic_table[] = {
93 initarm_lastaddr(void)
96 return (arm_devmap_lastaddr());
100 initarm_early_init(void)
103 /* Inform the MPCore timer driver that its clock is variable. */
104 arm_tmr_change_frequency(ARM_TMR_FREQUENCY_VARIES);
108 initarm_gpio_init(void)
114 initarm_late_init(void)
117 /* Cache the gpio1 node handle for imx6_decode_fdt() workaround code. */
118 gpio1_node = OF_node_from_xref(
119 OF_finddevice("/soc/aips-bus@02000000/gpio@0209c000"));
123 * Set up static device mappings.
125 * This attempts to cover the most-used devices with 1MB section mappings, which
126 * is good for performance (uses fewer TLB entries for device access).
128 * ARMMP covers the interrupt controller, MPCore timers, global timer, and the
129 * L2 cache controller. Most of the 1MB range is unused reserved space.
131 * AIPS1/AIPS2 cover most of the on-chip devices such as uart, spi, i2c, etc.
133 * Notably not mapped right now are HDMI, GPU, and other devices below ARMMP in
134 * the memory map. When we get support for graphics it might make sense to
135 * static map some of that area. Be careful with other things in that area such
136 * as OCRAM that probably shouldn't be mapped as PTE_DEVICE memory.
139 initarm_devmap_init(void)
141 const uint32_t IMX6_ARMMP_PHYS = 0x00a00000;
142 const uint32_t IMX6_ARMMP_SIZE = 0x00100000;
143 const uint32_t IMX6_AIPS1_PHYS = 0x02000000;
144 const uint32_t IMX6_AIPS1_SIZE = 0x00100000;
145 const uint32_t IMX6_AIPS2_PHYS = 0x02100000;
146 const uint32_t IMX6_AIPS2_SIZE = 0x00100000;
148 arm_devmap_add_entry(IMX6_ARMMP_PHYS, IMX6_ARMMP_SIZE);
149 arm_devmap_add_entry(IMX6_AIPS1_PHYS, IMX6_AIPS1_SIZE);
150 arm_devmap_add_entry(IMX6_AIPS2_PHYS, IMX6_AIPS2_SIZE);
158 const uint32_t IMX6_WDOG_CR_PHYS = 0x020bc000;
160 imx_wdog_cpu_reset(IMX6_WDOG_CR_PHYS);
164 * Determine what flavor of imx6 we're running on.
166 * This code is based on the way u-boot does it. Information found on the web
167 * indicates that Freescale themselves were the original source of this logic,
168 * including the strange check for number of CPUs in the SCU configuration
169 * register, which is apparently needed on some revisions of the SOLO.
171 * According to the documentation, there is such a thing as an i.MX6 Dual
172 * (non-lite flavor). However, Freescale doesn't seem to have assigned it a
173 * number or provided any logic to handle it in their detection code.
175 * Note that the ANALOG_DIGPROG and SCU configuration registers are not
176 * documented in the chip reference manual. (SCU configuration is mentioned,
177 * but not mapped out in detail.) I think the bottom two bits of the scu config
178 * register may be ncpu-1.
180 * This hasn't been tested yet on a dual[-lite].
183 * digprog = 0x00610001
185 * scu config = 0x00000500
187 * digprog = 0x00630002
189 * scu config = 0x00005503
193 uint32_t digprog, hwsoc;
195 static u_int soctype;
196 const vm_offset_t SCU_CONFIG_PHYSADDR = 0x00a00004;
197 #define HWSOC_MX6SL 0x60
198 #define HWSOC_MX6DL 0x61
199 #define HWSOC_MX6SOLO 0x62
200 #define HWSOC_MX6Q 0x63
205 digprog = imx6_anatop_read_4(IMX6_ANALOG_DIGPROG_SL);
206 hwsoc = (digprog >> IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT) &
207 IMX6_ANALOG_DIGPROG_SOCTYPE_MASK;
209 if (hwsoc != HWSOC_MX6SL) {
210 digprog = imx6_anatop_read_4(IMX6_ANALOG_DIGPROG);
211 hwsoc = (digprog & IMX6_ANALOG_DIGPROG_SOCTYPE_MASK) >>
212 IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT;
213 /*printf("digprog = 0x%08x\n", digprog);*/
214 if (hwsoc == HWSOC_MX6DL) {
215 pcr = arm_devmap_ptov(SCU_CONFIG_PHYSADDR, 4);
217 /*printf("scu config = 0x%08x\n", *pcr);*/
218 if ((*pcr & 0x03) == 0) {
219 hwsoc = HWSOC_MX6SOLO;
224 /* printf("hwsoc 0x%08x\n", hwsoc); */
228 soctype = IMXSOC_6SL;
234 soctype = IMXSOC_6DL;
240 printf("imx_soc_type: Don't understand hwsoc 0x%02x, "
241 "digprog 0x%08x; assuming IMXSOC_6Q\n", hwsoc, digprog);
250 * Early putc routine for EARLY_PRINTF support. To use, add to kernel config:
251 * option SOCDEV_PA=0x02000000
252 * option SOCDEV_VA=0x02000000
253 * option EARLY_PRINTF
254 * Resist the temptation to change the #if 0 to #ifdef EARLY_PRINTF here. It
255 * makes sense now, but if multiple SOCs do that it will make early_putc another
256 * duplicate symbol to be eliminated on the path to a generic kernel.
260 imx6_early_putc(int c)
262 volatile uint32_t * UART_STAT_REG = (uint32_t *)0x02020098;
263 volatile uint32_t * UART_TX_REG = (uint32_t *)0x02020040;
264 const uint32_t UART_TXRDY = (1 << 3);
266 while ((*UART_STAT_REG & UART_TXRDY) == 0)
270 early_putc_t *early_putc = imx6_early_putc;