2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * i.MX6 Synchronous Serial Interface (SSI)
30 * Chapter 61, i.MX 6Dual/6Quad Applications Processor Reference Manual,
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/malloc.h>
44 #include <sys/timeet.h>
45 #include <sys/timetc.h>
47 #include <dev/sound/pcm/sound.h>
48 #include <dev/sound/chip.h>
51 #include <dev/fdt/fdt_common.h>
52 #include <dev/ofw/openfirm.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
56 #include <machine/bus.h>
57 #include <machine/fdt.h>
58 #include <machine/cpu.h>
59 #include <machine/intr.h>
61 #include <arm/freescale/imx/imx6_sdma.h>
62 #include <arm/freescale/imx/imx6_anatopvar.h>
63 #include <arm/freescale/imx/imx_ccmvar.h>
65 #define READ4(_sc, _reg) \
66 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
67 #define WRITE4(_sc, _reg, _val) \
68 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
70 #define SSI_NCHANNELS 1
72 /* i.MX6 SSI registers */
74 #define SSI_STX0 0x00 /* Transmit Data Register n */
75 #define SSI_STX1 0x04 /* Transmit Data Register n */
76 #define SSI_SRX0 0x08 /* Receive Data Register n */
77 #define SSI_SRX1 0x0C /* Receive Data Register n */
78 #define SSI_SCR 0x10 /* Control Register */
79 #define SCR_I2S_MODE_S 5 /* I2S Mode Select. */
80 #define SCR_I2S_MODE_M 0x3
81 #define SCR_SYN (1 << 4)
82 #define SCR_NET (1 << 3) /* Network mode */
83 #define SCR_RE (1 << 2) /* Receive Enable. */
84 #define SCR_TE (1 << 1) /* Transmit Enable. */
85 #define SCR_SSIEN (1 << 0) /* SSI Enable */
86 #define SSI_SISR 0x14 /* Interrupt Status Register */
87 #define SSI_SIER 0x18 /* Interrupt Enable Register */
88 #define SIER_RDMAE (1 << 22) /* Receive DMA Enable. */
89 #define SIER_RIE (1 << 21) /* Receive Interrupt Enable. */
90 #define SIER_TDMAE (1 << 20) /* Transmit DMA Enable. */
91 #define SIER_TIE (1 << 19) /* Transmit Interrupt Enable. */
92 #define SIER_TDE0IE (1 << 12) /* Transmit Data Register Empty 0. */
93 #define SIER_TUE0IE (1 << 8) /* Transmitter Underrun Error 0. */
94 #define SIER_TFE0IE (1 << 0) /* Transmit FIFO Empty 0 IE. */
95 #define SSI_STCR 0x1C /* Transmit Configuration Register */
96 #define STCR_TXBIT0 (1 << 9) /* Transmit Bit 0 shift MSB/LSB */
97 #define STCR_TFEN1 (1 << 8) /* Transmit FIFO Enable 1. */
98 #define STCR_TFEN0 (1 << 7) /* Transmit FIFO Enable 0. */
99 #define STCR_TFDIR (1 << 6) /* Transmit Frame Direction. */
100 #define STCR_TXDIR (1 << 5) /* Transmit Clock Direction. */
101 #define STCR_TSHFD (1 << 4) /* Transmit Shift Direction. */
102 #define STCR_TSCKP (1 << 3) /* Transmit Clock Polarity. */
103 #define STCR_TFSI (1 << 2) /* Transmit Frame Sync Invert. */
104 #define STCR_TFSL (1 << 1) /* Transmit Frame Sync Length. */
105 #define STCR_TEFS (1 << 0) /* Transmit Early Frame Sync. */
106 #define SSI_SRCR 0x20 /* Receive Configuration Register */
107 #define SSI_STCCR 0x24 /* Transmit Clock Control Register */
108 #define STCCR_DIV2 (1 << 18) /* Divide By 2. */
109 #define STCCR_PSR (1 << 17) /* Divide clock by 8. */
111 #define WL3_WL0_M 0xf
113 #define DC4_DC0_M 0x1f
115 #define PM7_PM0_M 0xff
116 #define SSI_SRCCR 0x28 /* Receive Clock Control Register */
117 #define SSI_SFCSR 0x2C /* FIFO Control/Status Register */
118 #define SFCSR_RFWM1_S 20 /* Receive FIFO Empty WaterMark 1 */
119 #define SFCSR_RFWM1_M 0xf
120 #define SFCSR_TFWM1_S 16 /* Transmit FIFO Empty WaterMark 1 */
121 #define SFCSR_TFWM1_M 0xf
122 #define SFCSR_RFWM0_S 4 /* Receive FIFO Empty WaterMark 0 */
123 #define SFCSR_RFWM0_M 0xf
124 #define SFCSR_TFWM0_S 0 /* Transmit FIFO Empty WaterMark 0 */
125 #define SFCSR_TFWM0_M 0xf
126 #define SSI_SACNT 0x38 /* AC97 Control Register */
127 #define SSI_SACADD 0x3C /* AC97 Command Address Register */
128 #define SSI_SACDAT 0x40 /* AC97 Command Data Register */
129 #define SSI_SATAG 0x44 /* AC97 Tag Register */
130 #define SSI_STMSK 0x48 /* Transmit Time Slot Mask Register */
131 #define SSI_SRMSK 0x4C /* Receive Time Slot Mask Register */
132 #define SSI_SACCST 0x50 /* AC97 Channel Status Register */
133 #define SSI_SACCEN 0x54 /* AC97 Channel Enable Register */
134 #define SSI_SACCDIS 0x58 /* AC97 Channel Disable Register */
136 static MALLOC_DEFINE(M_SSI, "ssi", "ssi audio");
138 uint32_t ssi_dma_intr(void *arg, int chn);
142 uint32_t mfi; /* PLL4 Multiplication Factor Integer */
143 uint32_t mfn; /* PLL4 Multiplication Factor Numerator */
144 uint32_t mfd; /* PLL4 Multiplication Factor Denominator */
145 /* More dividers to configure can be added here */
148 static struct ssi_rate rate_map[] = {
149 { 192000, 49, 152, 1000 }, /* PLL4 49.152 Mhz */
150 /* TODO: add more frequences */
155 * i.MX6 example bit clock formula
157 * BCLK = 2 channels * 192000 hz * 24 bit = 9216000 hz =
158 * (24000000 * (49 + 152/1000.0) / 4 / 4 / 2 / 2 / 2 / 1 / 1)
159 * ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
160 * | | | | | | | | | | |
161 * Fref ------/ | | | | | | | | | |
162 * PLL4 div select -/ | | | | | | | | |
163 * PLL4 num --------------/ | | | | | | | |
164 * PLL4 denom -------------------/ | | | | | | |
165 * PLL4 post div ---------------------/ | | | | | |
166 * CCM ssi pre div (CCM_CS1CDR) ----------/ | | | | |
167 * CCM ssi post div (CCM_CS1CDR) -------------/ | | | |
168 * SSI PM7_PM0_S ---------------------------------/ | | |
169 * SSI Fixed divider ---------------------------------/ | |
170 * SSI DIV2 ----------------------------------------------/ |
171 * SSI PSR (prescaler /1 or /8) ------------------------------/
173 * MCLK (Master clock) depends on DAC, usually BCLK * 4
177 struct resource *res[2];
179 bus_space_handle_t bsh;
185 bus_dma_tag_t dma_tag;
186 bus_dmamap_t dma_map;
187 bus_addr_t buf_base_phys;
189 struct sdma_conf *conf;
191 struct sdma_softc *sdma_sc;
197 /* Channel registers */
199 struct snd_dbuf *buffer;
200 struct pcm_channel *channel;
201 struct sc_pcminfo *parent;
203 /* Channel information */
211 /* PCM device private data */
214 uint32_t (*ih)(struct sc_pcminfo *scp);
216 struct sc_chinfo chan[SSI_NCHANNELS];
220 static struct resource_spec ssi_spec[] = {
221 { SYS_RES_MEMORY, 0, RF_ACTIVE },
222 { SYS_RES_IRQ, 0, RF_ACTIVE },
226 static int setup_dma(struct sc_pcminfo *scp);
227 static void setup_ssi(struct sc_info *);
228 static void ssi_configure_clock(struct sc_info *);
235 ssimixer_init(struct snd_mixer *m)
237 struct sc_pcminfo *scp;
241 scp = mix_getdevinfo(m);
247 mask = SOUND_MASK_PCM;
248 mask |= SOUND_MASK_VOLUME;
250 snd_mtxlock(sc->lock);
251 pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL);
252 mix_setdevs(m, mask);
253 snd_mtxunlock(sc->lock);
259 ssimixer_set(struct snd_mixer *m, unsigned dev,
260 unsigned left, unsigned right)
262 struct sc_pcminfo *scp;
264 scp = mix_getdevinfo(m);
266 /* Here we can configure hardware volume on our DAC */
269 device_printf(scp->dev, "ssimixer_set() %d %d\n",
276 static kobj_method_t ssimixer_methods[] = {
277 KOBJMETHOD(mixer_init, ssimixer_init),
278 KOBJMETHOD(mixer_set, ssimixer_set),
281 MIXER_DECLARE(ssimixer);
289 ssichan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
290 struct pcm_channel *c, int dir)
292 struct sc_pcminfo *scp;
293 struct sc_chinfo *ch;
296 scp = (struct sc_pcminfo *)devinfo;
299 snd_mtxlock(sc->lock);
306 snd_mtxunlock(sc->lock);
308 if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) {
309 device_printf(scp->dev, "Can't setup sndbuf.\n");
317 ssichan_free(kobj_t obj, void *data)
319 struct sc_chinfo *ch = data;
320 struct sc_pcminfo *scp = ch->parent;
321 struct sc_info *sc = scp->sc;
324 device_printf(scp->dev, "ssichan_free()\n");
327 snd_mtxlock(sc->lock);
328 /* TODO: free channel buffer */
329 snd_mtxunlock(sc->lock);
335 ssichan_setformat(kobj_t obj, void *data, uint32_t format)
337 struct sc_chinfo *ch = data;
345 ssichan_setspeed(kobj_t obj, void *data, uint32_t speed)
347 struct sc_pcminfo *scp;
348 struct sc_chinfo *ch;
360 /* First look for equal frequency. */
361 for (i = 0; rate_map[i].speed != 0; i++) {
362 if (rate_map[i].speed == speed)
366 /* If no match, just find nearest. */
368 for (i = 0; rate_map[i].speed != 0; i++) {
370 threshold = sr->speed + ((rate_map[i + 1].speed != 0) ?
371 ((rate_map[i + 1].speed - sr->speed) >> 1) : 0);
372 if (speed < threshold)
379 ssi_configure_clock(sc);
385 ssi_configure_clock(struct sc_info *sc)
391 pll4_configure_output(sr->mfi, sr->mfn, sr->mfd);
393 /* Configure other dividers here, if any */
397 ssichan_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
399 struct sc_chinfo *ch = data;
400 struct sc_pcminfo *scp = ch->parent;
401 struct sc_info *sc = scp->sc;
403 sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize);
407 return (sndbuf_getblksz(ch->buffer));
411 ssi_dma_intr(void *arg, int chn)
413 struct sc_pcminfo *scp;
414 struct sdma_conf *conf;
415 struct sc_chinfo *ch;
424 bufsize = sndbuf_getsize(ch->buffer);
426 sc->pos += conf->period;
427 if (sc->pos >= bufsize)
431 chn_intr(ch->channel);
437 find_sdma_controller(struct sc_info *sc)
439 struct sdma_softc *sdma_sc;
440 phandle_t node, sdma_node;
445 if ((node = ofw_bus_get_node(sc->dev)) == -1)
448 if ((len = OF_getproplen(node, "dmas")) <= 0)
451 OF_getprop(node, "dmas", &dts_value, len);
453 sc->sdma_ev_rx = fdt32_to_cpu(dts_value[1]);
454 sc->sdma_ev_tx = fdt32_to_cpu(dts_value[5]);
456 sdma_node = OF_node_from_xref(fdt32_to_cpu(dts_value[0]));
460 sdma_dev = devclass_get_device(devclass_find("sdma"), 0);
462 sdma_sc = device_get_softc(sdma_dev);
464 if (sdma_sc == NULL) {
465 device_printf(sc->dev, "No sDMA found. Can't operate\n");
469 sc->sdma_sc = sdma_sc;
475 setup_dma(struct sc_pcminfo *scp)
477 struct sdma_conf *conf;
478 struct sc_chinfo *ch;
486 conf->ih = ssi_dma_intr;
488 conf->saddr = sc->buf_base_phys;
489 conf->daddr = rman_get_start(sc->res[0]) + SSI_STX0;
490 conf->event = sc->sdma_ev_tx; /* SDMA TX event */
491 conf->period = sndbuf_getblksz(ch->buffer);
492 conf->num_bd = sndbuf_getblkcnt(ch->buffer);
496 * Can be 32, 24, 16 or 8 for sDMA.
498 * SSI supports 24 at max.
501 fmt = sndbuf_getfmt(ch->buffer);
503 if (fmt & AFMT_16BIT) {
504 conf->word_length = 16;
505 conf->command = CMD_2BYTES;
506 } else if (fmt & AFMT_24BIT) {
507 conf->word_length = 24;
508 conf->command = CMD_3BYTES;
510 device_printf(sc->dev, "Unknown format\n");
518 ssi_start(struct sc_pcminfo *scp)
525 if (sdma_configure(sc->sdma_channel, sc->conf) != 0) {
526 device_printf(sc->dev, "Can't configure sDMA\n");
530 /* Enable DMA interrupt */
532 WRITE4(sc, SSI_SIER, reg);
534 sdma_start(sc->sdma_channel);
540 ssi_stop(struct sc_pcminfo *scp)
547 reg = READ4(sc, SSI_SIER);
548 reg &= ~(SIER_TDMAE);
549 WRITE4(sc, SSI_SIER, reg);
551 sdma_stop(sc->sdma_channel);
553 bzero(sc->buf_base, sc->dma_size);
559 ssichan_trigger(kobj_t obj, void *data, int go)
561 struct sc_pcminfo *scp;
562 struct sc_chinfo *ch;
569 snd_mtxlock(sc->lock);
574 device_printf(scp->dev, "trigger start\n");
585 device_printf(scp->dev, "trigger stop or abort\n");
594 snd_mtxunlock(sc->lock);
600 ssichan_getptr(kobj_t obj, void *data)
602 struct sc_pcminfo *scp;
603 struct sc_chinfo *ch;
613 static uint32_t ssi_pfmt[] = {
614 SND_FORMAT(AFMT_S24_LE, 2, 0),
618 static struct pcmchan_caps ssi_pcaps = {44100, 192000, ssi_pfmt, 0};
620 static struct pcmchan_caps *
621 ssichan_getcaps(kobj_t obj, void *data)
627 static kobj_method_t ssichan_methods[] = {
628 KOBJMETHOD(channel_init, ssichan_init),
629 KOBJMETHOD(channel_free, ssichan_free),
630 KOBJMETHOD(channel_setformat, ssichan_setformat),
631 KOBJMETHOD(channel_setspeed, ssichan_setspeed),
632 KOBJMETHOD(channel_setblocksize, ssichan_setblocksize),
633 KOBJMETHOD(channel_trigger, ssichan_trigger),
634 KOBJMETHOD(channel_getptr, ssichan_getptr),
635 KOBJMETHOD(channel_getcaps, ssichan_getcaps),
638 CHANNEL_DECLARE(ssichan);
641 ssi_probe(device_t dev)
644 if (!ofw_bus_status_okay(dev))
647 if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ssi"))
650 device_set_desc(dev, "i.MX6 Synchronous Serial Interface (SSI)");
651 return (BUS_PROBE_DEFAULT);
657 struct sc_pcminfo *scp;
658 struct sc_chinfo *ch;
665 /* We don't use SSI interrupt */
667 device_printf(sc->dev, "SSI Intr 0x%08x\n",
668 READ4(sc, SSI_SISR));
673 setup_ssi(struct sc_info *sc)
677 reg = READ4(sc, SSI_STCCR);
678 reg &= ~(WL3_WL0_M << WL3_WL0_S);
679 reg |= (0xb << WL3_WL0_S); /* 24 bit */
680 reg &= ~(DC4_DC0_M << DC4_DC0_S);
681 reg |= (1 << DC4_DC0_S); /* 2 words per frame */
682 reg &= ~(STCCR_DIV2); /* Divide by 1 */
683 reg &= ~(STCCR_PSR); /* Divide by 1 */
684 reg &= ~(PM7_PM0_M << PM7_PM0_S);
685 reg |= (1 << PM7_PM0_S); /* Divide by 2 */
686 WRITE4(sc, SSI_STCCR, reg);
688 reg = READ4(sc, SSI_SFCSR);
689 reg &= ~(SFCSR_TFWM0_M << SFCSR_TFWM0_S);
690 reg |= (8 << SFCSR_TFWM0_S); /* empty slots */
691 WRITE4(sc, SSI_SFCSR, reg);
693 reg = READ4(sc, SSI_STCR);
695 reg &= ~(STCR_TFEN1);
696 reg &= ~(STCR_TSHFD); /* MSB */
697 reg |= (STCR_TXBIT0);
698 reg |= (STCR_TXDIR | STCR_TFDIR);
699 reg |= (STCR_TSCKP); /* falling edge */
701 reg &= ~(STCR_TFSI); /* active high frame sync */
704 WRITE4(sc, SSI_STCR, reg);
706 reg = READ4(sc, SSI_SCR);
707 reg &= ~(SCR_I2S_MODE_M << SCR_I2S_MODE_S); /* Not master */
708 reg |= (SCR_SSIEN | SCR_TE);
711 WRITE4(sc, SSI_SCR, reg);
715 ssi_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
722 addr = (bus_addr_t*)arg;
723 *addr = segs[0].ds_addr;
727 ssi_attach(device_t dev)
729 char status[SND_STATUSLEN];
730 struct sc_pcminfo *scp;
734 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
736 sc->sr = &rate_map[0];
738 sc->conf = malloc(sizeof(struct sdma_conf), M_DEVBUF, M_WAITOK | M_ZERO);
740 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "ssi softc");
741 if (sc->lock == NULL) {
742 device_printf(dev, "Cant create mtx\n");
746 if (bus_alloc_resources(dev, ssi_spec, sc->res)) {
747 device_printf(dev, "could not allocate resources\n");
751 /* Memory interface */
752 sc->bst = rman_get_bustag(sc->res[0]);
753 sc->bsh = rman_get_bushandle(sc->res[0]);
756 if (find_sdma_controller(sc)) {
757 device_printf(dev, "could not find active SDMA\n");
762 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO);
767 * Maximum possible DMA buffer.
768 * Will be used partialy to match 24 bit word.
770 sc->dma_size = 131072;
773 * Must use dma_size boundary as modulo feature required.
774 * Modulo feature allows setup circular buffer.
777 err = bus_dma_tag_create(
778 bus_get_dma_tag(sc->dev),
779 4, sc->dma_size, /* alignment, boundary */
780 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
781 BUS_SPACE_MAXADDR, /* highaddr */
782 NULL, NULL, /* filter, filterarg */
783 sc->dma_size, 1, /* maxsize, nsegments */
784 sc->dma_size, 0, /* maxsegsize, flags */
785 NULL, NULL, /* lockfunc, lockarg */
788 err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base,
789 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map);
791 device_printf(dev, "cannot allocate framebuffer\n");
795 err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base,
796 sc->dma_size, ssi_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT);
798 device_printf(dev, "cannot load DMA map\n");
802 bzero(sc->buf_base, sc->dma_size);
804 /* Setup interrupt handler */
805 err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV,
806 NULL, ssi_intr, scp, &sc->ih);
808 device_printf(dev, "Unable to alloc interrupt resource.\n");
812 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE);
814 err = pcm_register(dev, scp, 1, 0);
816 device_printf(dev, "Can't register pcm.\n");
821 pcm_addchan(dev, PCMDIR_PLAY, &ssichan_class, scp);
824 snprintf(status, SND_STATUSLEN, "at simplebus");
825 pcm_setstatus(dev, status);
827 mixer_init(dev, &ssimixer_class, scp);
830 imx_ccm_ssi_configure(dev);
832 sc->sdma_channel = sdma_alloc();
833 if (sc->sdma_channel < 0) {
834 device_printf(sc->dev, "Can't get sDMA channel\n");
841 static device_method_t ssi_pcm_methods[] = {
842 DEVMETHOD(device_probe, ssi_probe),
843 DEVMETHOD(device_attach, ssi_attach),
847 static driver_t ssi_pcm_driver = {
853 DRIVER_MODULE(ssi, simplebus, ssi_pcm_driver, pcm_devclass, 0, 0);
854 MODULE_DEPEND(ssi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
855 MODULE_VERSION(ssi, 1);