2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk
3 * Copyright (c) 2012, 2013 The FreeBSD Foundation
6 * Portions of this software were developed by Oleksandr Rybalko
7 * under sponsorship from the FreeBSD Foundation.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/limits.h>
39 #include <sys/module.h>
40 #include <sys/resource.h>
42 #include <machine/bus.h>
43 #include <machine/resource.h>
47 #include <sys/mutex.h>
49 #include <arm/freescale/imx/imx_ccmvar.h>
51 #include <dev/iicbus/iiconf.h>
52 #include <dev/iicbus/iicbus.h>
53 #include "iicbus_if.h"
55 #include <dev/fdt/fdt_common.h>
56 #include <dev/ofw/openfirm.h>
57 #include <dev/ofw/ofw_bus.h>
58 #include <dev/ofw/ofw_bus_subr.h>
60 #define I2C_ADDR_REG 0x00 /* I2C slave address register */
61 #define I2C_FDR_REG 0x04 /* I2C frequency divider register */
62 #define I2C_CONTROL_REG 0x08 /* I2C control register */
63 #define I2C_STATUS_REG 0x0C /* I2C status register */
64 #define I2C_DATA_REG 0x10 /* I2C data register */
65 #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */
67 #define I2CCR_MEN (1 << 7) /* Module enable */
68 #define I2CCR_MSTA (1 << 5) /* Master/slave mode */
69 #define I2CCR_MTX (1 << 4) /* Transmit/receive mode */
70 #define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */
71 #define I2CCR_RSTA (1 << 2) /* Repeated START */
73 #define I2CSR_MCF (1 << 7) /* Data transfer */
74 #define I2CSR_MASS (1 << 6) /* Addressed as a slave */
75 #define I2CSR_MBB (1 << 5) /* Bus busy */
76 #define I2CSR_MAL (1 << 4) /* Arbitration lost */
77 #define I2CSR_SRW (1 << 2) /* Slave read/write */
78 #define I2CSR_MIF (1 << 1) /* Module interrupt */
79 #define I2CSR_RXAK (1 << 0) /* Received acknowledge */
81 #define I2C_BAUD_RATE_FAST 0x31
82 #define I2C_BAUD_RATE_DEF 0x3F
83 #define I2C_DFSSR_DIV 0x10
86 * A table of available divisors and the associated coded values to put in the
87 * FDR register to achieve that divisor.. There is no algorithmic relationship I
88 * can see between divisors and the codes that go into the register. The table
89 * begins and ends with entries that handle insane configuration values.
95 static struct clkdiv clkdiv_table[] = {
96 { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 },
97 { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 },
98 { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 },
99 { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a },
100 { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d },
101 { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c },
102 { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f },
103 { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 },
104 { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 },
105 { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 },
106 { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d },
107 { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c },
108 { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f}
112 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \
113 printf(fmt,##args); } while (0)
115 #define debugf(fmt, args...)
118 static struct ofw_compat_data compat_data[] = {
119 {"fsl,imx6q-i2c", 1},
127 struct resource *res;
130 bus_space_handle_t bsh;
134 static phandle_t i2c_get_node(device_t, device_t);
135 static int i2c_probe(device_t);
136 static int i2c_attach(device_t);
138 static int i2c_repeated_start(device_t, u_char, int);
139 static int i2c_start(device_t, u_char, int);
140 static int i2c_stop(device_t);
141 static int i2c_reset(device_t, u_char, u_char, u_char *);
142 static int i2c_read(device_t, char *, int, int *, int, int);
143 static int i2c_write(device_t, const char *, int, int *, int);
145 static device_method_t i2c_methods[] = {
146 DEVMETHOD(device_probe, i2c_probe),
147 DEVMETHOD(device_attach, i2c_attach),
150 DEVMETHOD(ofw_bus_get_node, i2c_get_node),
152 DEVMETHOD(iicbus_callback, iicbus_null_callback),
153 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start),
154 DEVMETHOD(iicbus_start, i2c_start),
155 DEVMETHOD(iicbus_stop, i2c_stop),
156 DEVMETHOD(iicbus_reset, i2c_reset),
157 DEVMETHOD(iicbus_read, i2c_read),
158 DEVMETHOD(iicbus_write, i2c_write),
159 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
164 static driver_t i2c_driver = {
167 sizeof(struct i2c_softc),
169 static devclass_t i2c_devclass;
171 DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0);
172 DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0);
175 i2c_get_node(device_t bus, device_t dev)
178 * Share controller node with iicbus device
180 return ofw_bus_get_node(bus);
184 i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val)
187 bus_space_write_1(sc->bst, sc->bsh, off, val);
190 static __inline uint8_t
191 i2c_read_reg(struct i2c_softc *sc, bus_size_t off)
194 return (bus_space_read_1(sc->bst, sc->bsh, off));
198 i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask)
202 status = i2c_read_reg(sc, off);
204 i2c_write_reg(sc, off, status);
207 /* Wait for transfer interrupt flag */
209 wait_for_iif(struct i2c_softc *sc)
215 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MIF)
220 return (IIC_ETIMEOUT);
223 /* Wait for free bus */
225 wait_for_nibb(struct i2c_softc *sc)
231 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0)
236 return (IIC_ETIMEOUT);
239 /* Wait for transfer complete+interrupt flag */
241 wait_for_icf(struct i2c_softc *sc)
248 if ((i2c_read_reg(sc, I2C_STATUS_REG) &
249 (I2CSR_MCF|I2CSR_MIF)) == (I2CSR_MCF|I2CSR_MIF))
254 return (IIC_ETIMEOUT);
258 i2c_probe(device_t dev)
260 struct i2c_softc *sc;
262 if (!ofw_bus_status_okay(dev))
265 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
268 sc = device_get_softc(dev);
271 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
273 if (sc->res == NULL) {
274 device_printf(dev, "could not allocate resources\n");
278 sc->bst = rman_get_bustag(sc->res);
279 sc->bsh = rman_get_bushandle(sc->res);
282 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
283 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res);
284 device_set_desc(dev, "Freescale i.MX I2C bus controller");
286 return (BUS_PROBE_DEFAULT);
290 i2c_attach(device_t dev)
292 struct i2c_softc *sc;
294 sc = device_get_softc(dev);
298 mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF);
300 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
302 if (sc->res == NULL) {
303 device_printf(dev, "could not allocate resources");
304 mtx_destroy(&sc->mutex);
308 sc->bst = rman_get_bustag(sc->res);
309 sc->bsh = rman_get_bushandle(sc->res);
311 sc->iicbus = device_add_child(dev, "iicbus", -1);
312 if (sc->iicbus == NULL) {
313 device_printf(dev, "could not add iicbus child");
314 mtx_destroy(&sc->mutex);
318 bus_generic_attach(dev);
323 i2c_repeated_start(device_t dev, u_char slave, int timeout)
325 struct i2c_softc *sc;
328 sc = device_get_softc(dev);
330 mtx_lock(&sc->mutex);
332 i2c_write_reg(sc, I2C_ADDR_REG, slave);
333 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) {
334 mtx_unlock(&sc->mutex);
335 return (IIC_EBUSBSY);
338 /* Set repeated start condition */
340 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA);
343 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
344 /* Write target address - LSB is R/W bit */
345 i2c_write_reg(sc, I2C_DATA_REG, slave);
347 error = wait_for_iif(sc);
350 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
352 mtx_unlock(&sc->mutex);
361 i2c_start(device_t dev, u_char slave, int timeout)
363 struct i2c_softc *sc;
366 sc = device_get_softc(dev);
368 mtx_lock(&sc->mutex);
369 i2c_write_reg(sc, I2C_ADDR_REG, slave);
370 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) {
371 mtx_unlock(&sc->mutex);
372 return (IIC_EBUSBSY);
375 /* Set start condition */
376 i2c_write_reg(sc, I2C_CONTROL_REG,
377 I2CCR_MEN | I2CCR_MSTA | I2CCR_TXAK);
379 i2c_write_reg(sc, I2C_CONTROL_REG,
380 I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX | I2CCR_TXAK);
382 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
383 /* Write target address - LSB is R/W bit */
384 i2c_write_reg(sc, I2C_DATA_REG, slave);
386 error = wait_for_iif(sc);
388 mtx_unlock(&sc->mutex);
397 i2c_stop(device_t dev)
399 struct i2c_softc *sc;
401 sc = device_get_softc(dev);
402 mtx_lock(&sc->mutex);
403 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK);
405 /* Reset controller if bus still busy after STOP */
406 if (wait_for_nibb(sc) == IIC_ETIMEOUT) {
407 i2c_write_reg(sc, I2C_CONTROL_REG, 0);
409 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK);
411 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
413 mtx_unlock(&sc->mutex);
419 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
421 struct i2c_softc *sc;
422 u_int busfreq, div, i, ipgfreq;
424 sc = device_get_softc(dev);
427 * Look up the divisor that gives the nearest speed that doesn't exceed
428 * the configured value for the bus.
430 ipgfreq = imx_ccm_ipg_hz();
431 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
432 div = (ipgfreq + busfreq - 1) / busfreq;
433 for (i = 0; i < nitems(clkdiv_table); i++) {
434 if (clkdiv_table[i].divisor >= div)
437 div = clkdiv_table[i].regcode;
439 mtx_lock(&sc->mutex);
440 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0);
441 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
444 i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)div);
445 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
447 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
448 mtx_unlock(&sc->mutex);
454 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay)
456 struct i2c_softc *sc;
459 sc = device_get_softc(dev);
462 mtx_lock(&sc->mutex);
466 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
467 I2CCR_MSTA | I2CCR_TXAK);
470 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
474 i2c_read_reg(sc, I2C_DATA_REG);
478 while (*read < len) {
479 error = wait_for_icf(sc);
481 mtx_unlock(&sc->mutex);
484 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
485 if ((*read == len - 2) && last) {
486 /* NO ACK on last byte */
487 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
488 I2CCR_MSTA | I2CCR_TXAK);
491 if ((*read == len - 1) && last) {
492 /* Transfer done, remove master bit */
493 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
497 reg = i2c_read_reg(sc, I2C_DATA_REG);
501 mtx_unlock(&sc->mutex);
507 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout)
509 struct i2c_softc *sc;
512 sc = device_get_softc(dev);
515 mtx_lock(&sc->mutex);
516 while (*sent < len) {
517 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
518 i2c_write_reg(sc, I2C_DATA_REG, *buf++);
520 error = wait_for_iif(sc);
522 mtx_unlock(&sc->mutex);
528 mtx_unlock(&sc->mutex);