sys/arm/freescale/vybrid/vf_edma.c

   1 /*-
   2  * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * Vybrid Family Enhanced Direct Memory Access Controller (eDMA)
  29  * Chapter 21, Vybrid Reference Manual, Rev. 5, 07/2013
  30  */
  31
  32 #include <sys/cdefs.h>
  33 __FBSDID("$FreeBSD$");
  34
  35 #include <sys/param.h>
  36 #include <sys/systm.h>
  37 #include <sys/bus.h>
  38 #include <sys/kernel.h>
  39 #include <sys/module.h>
  40 #include <sys/malloc.h>
  41 #include <sys/rman.h>
  42 #include <sys/timeet.h>
  43 #include <sys/timetc.h>
  44 #include <sys/watchdog.h>
  45
  46 #include <dev/fdt/fdt_common.h>
  47 #include <dev/ofw/openfirm.h>
  48 #include <dev/ofw/ofw_bus.h>
  49 #include <dev/ofw/ofw_bus_subr.h>
  50
  51 #include <machine/bus.h>
  52 #include <machine/fdt.h>
  53 #include <machine/cpu.h>
  54 #include <machine/intr.h>
  55
  56 #include <arm/freescale/vybrid/vf_edma.h>
  57 #include <arm/freescale/vybrid/vf_dmamux.h>
  58 #include <arm/freescale/vybrid/vf_common.h>
  59
  60 struct edma_channel {
  61         uint32_t        enabled;
  62         uint32_t        mux_num;
  63         uint32_t        mux_src;
  64         uint32_t        mux_chn;
  65         uint32_t        (*ih) (void *, int);
  66         void            *ih_user;
  67 };
  68
  69 static struct edma_channel edma_map[EDMA_NUM_CHANNELS];
  70
  71 static struct resource_spec edma_spec[] = {
  72         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  73         { SYS_RES_MEMORY,       1,      RF_ACTIVE }, /* TCD */
  74         { SYS_RES_IRQ,          0,      RF_ACTIVE }, /* Transfer complete */
  75         { SYS_RES_IRQ,          1,      RF_ACTIVE }, /* Error Interrupt */
  76         { -1, 0 }
  77 };
  78
  79 static int
  80 edma_probe(device_t dev)
  81 {
  82
  83         if (!ofw_bus_status_okay(dev))
  84                 return (ENXIO);
  85
  86         if (!ofw_bus_is_compatible(dev, "fsl,mvf600-edma"))
  87                 return (ENXIO);
  88
  89         device_set_desc(dev, "Vybrid Family eDMA Controller");
  90         return (BUS_PROBE_DEFAULT);
  91 }
  92
  93 static void
  94 edma_transfer_complete_intr(void *arg)
  95 {
  96         struct edma_channel *ch;
  97         struct edma_softc *sc;
  98         int interrupts;
  99         int i;
 100
 101         sc = arg;
 102
 103         interrupts = READ4(sc, DMA_INT);
 104         WRITE1(sc, DMA_CINT, CINT_CAIR);
 105
 106         for (i = 0; i < EDMA_NUM_CHANNELS; i++) {
 107                 if (interrupts & (0x1 << i)) {
 108                         ch = &edma_map[i];
 109                         if (ch->enabled == 1) {
 110                                 if (ch->ih != NULL) {
 111                                         ch->ih(ch->ih_user, i);
 112                                 }
 113                         }
 114                 }
 115         }
 116 }
 117
 118 static void
 119 edma_err_intr(void *arg)
 120 {
 121         struct edma_softc *sc;
 122         int reg;
 123
 124         sc = arg;
 125
 126         reg = READ4(sc, DMA_ERR);
 127
 128 #if 0
 129         device_printf(sc->dev, "DMA_ERR 0x%08x, ES 0x%08x\n",
 130             reg, READ4(sc, DMA_ES));
 131 #endif
 132
 133         WRITE1(sc, DMA_CERR, CERR_CAEI);
 134 }
 135
 136 static int
 137 channel_free(struct edma_softc *sc, int chnum)
 138 {
 139         struct edma_channel *ch;
 140
 141         ch = &edma_map[chnum];
 142         ch->enabled = 0;
 143
 144         dmamux_configure(ch->mux_num, ch->mux_src, ch->mux_chn, 0);
 145
 146         return (0);
 147 }
 148
 149 static int
 150 channel_configure(struct edma_softc *sc, int mux_grp, int mux_src)
 151 {
 152         struct edma_channel *ch;
 153         int channel_first;
 154         int mux_num;
 155         int chnum;
 156         int i;
 157
 158         if ((sc->device_id == 0 && mux_grp == 1) ||     \
 159             (sc->device_id == 1 && mux_grp == 0)) {
 160                 channel_first = NCHAN_PER_MUX;
 161                 mux_num = (sc->device_id * 2) + 1;
 162         } else {
 163                 channel_first = 0;
 164                 mux_num = sc->device_id * 2;
 165         };
 166
 167         /* Take first unused eDMA channel */
 168         ch = NULL;
 169         for (i = channel_first; i < (channel_first + NCHAN_PER_MUX); i++) {
 170                 ch = &edma_map[i];
 171                 if (ch->enabled == 0) {
 172                         break;
 173                 }
 174                 ch = NULL;
 175         };
 176
 177         if (ch == NULL) {
 178                 /* Can't find free channel */
 179                 return (-1);
 180         };
 181
 182         chnum = i;
 183
 184         ch->enabled = 1;
 185         ch->mux_num = mux_num;
 186         ch->mux_src = mux_src;
 187         ch->mux_chn = (chnum - channel_first);  /* 0 to 15 */
 188
 189         dmamux_configure(ch->mux_num, ch->mux_src, ch->mux_chn, 1);
 190
 191         return (chnum);
 192 }
 193
 194 static int
 195 dma_stop(struct edma_softc *sc, int chnum)
 196 {
 197         int reg;
 198
 199         reg = READ4(sc, DMA_ERQ);
 200         reg &= ~(0x1 << chnum);
 201         WRITE4(sc, DMA_ERQ, reg);
 202
 203         return (0);
 204 }
 205
 206 static int
 207 dma_setup(struct edma_softc *sc, struct tcd_conf *tcd)
 208 {
 209         struct edma_channel *ch;
 210         int chnum;
 211         int reg;
 212
 213         chnum = tcd->channel;
 214
 215         ch = &edma_map[chnum];
 216         ch->ih = tcd->ih;
 217         ch->ih_user = tcd->ih_user;
 218
 219         TCD_WRITE4(sc, DMA_TCDn_SADDR(chnum), tcd->saddr);
 220         TCD_WRITE4(sc, DMA_TCDn_DADDR(chnum), tcd->daddr);
 221
 222         reg = (tcd->smod << TCD_ATTR_SMOD_SHIFT);
 223         reg |= (tcd->dmod << TCD_ATTR_DMOD_SHIFT);
 224         reg |= (tcd->ssize << TCD_ATTR_SSIZE_SHIFT);
 225         reg |= (tcd->dsize << TCD_ATTR_DSIZE_SHIFT);
 226         TCD_WRITE2(sc, DMA_TCDn_ATTR(chnum), reg);
 227
 228         TCD_WRITE2(sc, DMA_TCDn_SOFF(chnum), tcd->soff);
 229         TCD_WRITE2(sc, DMA_TCDn_DOFF(chnum), tcd->doff);
 230         TCD_WRITE4(sc, DMA_TCDn_SLAST(chnum), tcd->slast);
 231         TCD_WRITE4(sc, DMA_TCDn_DLASTSGA(chnum), tcd->dlast_sga);
 232         TCD_WRITE4(sc, DMA_TCDn_NBYTES_MLOFFYES(chnum), tcd->nbytes);
 233
 234         reg = tcd->nmajor; /* Current Major Iteration Count */
 235         TCD_WRITE2(sc, DMA_TCDn_CITER_ELINKNO(chnum), reg);
 236         TCD_WRITE2(sc, DMA_TCDn_BITER_ELINKNO(chnum), reg);
 237
 238         reg = (TCD_CSR_INTMAJOR);
 239         if(tcd->majorelink == 1) {
 240                 reg |= TCD_CSR_MAJORELINK;
 241                 reg |= (tcd->majorelinkch << TCD_CSR_MAJORELINKCH_SHIFT);
 242         }
 243         TCD_WRITE2(sc, DMA_TCDn_CSR(chnum), reg);
 244
 245         /* Enable requests */
 246         reg = READ4(sc, DMA_ERQ);
 247         reg |= (0x1 << chnum);
 248         WRITE4(sc, DMA_ERQ, reg);
 249
 250         /* Enable error interrupts */
 251         reg = READ4(sc, DMA_EEI);
 252         reg |= (0x1 << chnum);
 253         WRITE4(sc, DMA_EEI, reg);
 254
 255         return (0);
 256 }
 257
 258 static int
 259 dma_request(struct edma_softc *sc, int chnum)
 260 {
 261         int reg;
 262
 263         /* Start */
 264         reg = TCD_READ2(sc, DMA_TCDn_CSR(chnum));
 265         reg |= TCD_CSR_START;
 266         TCD_WRITE2(sc, DMA_TCDn_CSR(chnum), reg);
 267
 268         return (0);
 269 }
 270
 271 static int
 272 edma_attach(device_t dev)
 273 {
 274         struct edma_softc *sc;
 275         phandle_t node;
 276         int dts_value;
 277         int len;
 278
 279         sc = device_get_softc(dev);
 280         sc->dev = dev;
 281
 282         if ((node = ofw_bus_get_node(sc->dev)) == -1)
 283                 return (ENXIO);
 284
 285         if ((len = OF_getproplen(node, "device-id")) <= 0)
 286                 return (ENXIO);
 287
 288         OF_getprop(node, "device-id", &dts_value, len);
 289         sc->device_id = fdt32_to_cpu(dts_value);
 290
 291         sc->dma_stop = dma_stop;
 292         sc->dma_setup = dma_setup;
 293         sc->dma_request = dma_request;
 294         sc->channel_configure = channel_configure;
 295         sc->channel_free = channel_free;
 296
 297         if (bus_alloc_resources(dev, edma_spec, sc->res)) {
 298                 device_printf(dev, "could not allocate resources\n");
 299                 return (ENXIO);
 300         }
 301
 302         /* Memory interface */
 303         sc->bst = rman_get_bustag(sc->res[0]);
 304         sc->bsh = rman_get_bushandle(sc->res[0]);
 305         sc->bst_tcd = rman_get_bustag(sc->res[1]);
 306         sc->bsh_tcd = rman_get_bushandle(sc->res[1]);
 307
 308         /* Setup interrupt handlers */
 309         if (bus_setup_intr(dev, sc->res[2], INTR_TYPE_BIO | INTR_MPSAFE,
 310                 NULL, edma_transfer_complete_intr, sc, &sc->tc_ih)) {
 311                 device_printf(dev, "Unable to alloc DMA intr resource.\n");
 312                 return (ENXIO);
 313         }
 314
 315         if (bus_setup_intr(dev, sc->res[3], INTR_TYPE_BIO | INTR_MPSAFE,
 316                 NULL, edma_err_intr, sc, &sc->err_ih)) {
 317                 device_printf(dev, "Unable to alloc DMA Err intr resource.\n");
 318                 return (ENXIO);
 319         }
 320
 321         return (0);
 322 }
 323
 324 static device_method_t edma_methods[] = {
 325         DEVMETHOD(device_probe,         edma_probe),
 326         DEVMETHOD(device_attach,        edma_attach),
 327         { 0, 0 }
 328 };
 329
 330 static driver_t edma_driver = {
 331         "edma",
 332         edma_methods,
 333         sizeof(struct edma_softc),
 334 };
 335
 336 static devclass_t edma_devclass;
 337
 338 DRIVER_MODULE(edma, simplebus, edma_driver, edma_devclass, 0, 0);