2 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Vybrid Family Universal Asynchronous Receiver/Transmitter
29 * Chapter 49, Vybrid Reference Manual, Rev. 5, 07/2013
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
42 #include <machine/bus.h>
43 #include <machine/fdt.h>
45 #include <dev/uart/uart.h>
46 #include <dev/uart/uart_cpu.h>
47 #include <dev/uart/uart_cpu_fdt.h>
48 #include <dev/uart/uart_bus.h>
52 #define UART_BDH 0x00 /* Baud Rate Registers: High */
53 #define UART_BDL 0x01 /* Baud Rate Registers: Low */
54 #define UART_C1 0x02 /* Control Register 1 */
55 #define UART_C2 0x03 /* Control Register 2 */
56 #define UART_S1 0x04 /* Status Register 1 */
57 #define UART_S2 0x05 /* Status Register 2 */
58 #define UART_C3 0x06 /* Control Register 3 */
59 #define UART_D 0x07 /* Data Register */
60 #define UART_MA1 0x08 /* Match Address Registers 1 */
61 #define UART_MA2 0x09 /* Match Address Registers 2 */
62 #define UART_C4 0x0A /* Control Register 4 */
63 #define UART_C5 0x0B /* Control Register 5 */
64 #define UART_ED 0x0C /* Extended Data Register */
65 #define UART_MODEM 0x0D /* Modem Register */
66 #define UART_IR 0x0E /* Infrared Register */
67 #define UART_PFIFO 0x10 /* FIFO Parameters */
68 #define UART_CFIFO 0x11 /* FIFO Control Register */
69 #define UART_SFIFO 0x12 /* FIFO Status Register */
70 #define UART_TWFIFO 0x13 /* FIFO Transmit Watermark */
71 #define UART_TCFIFO 0x14 /* FIFO Transmit Count */
72 #define UART_RWFIFO 0x15 /* FIFO Receive Watermark */
73 #define UART_RCFIFO 0x16 /* FIFO Receive Count */
74 #define UART_C7816 0x18 /* 7816 Control Register */
75 #define UART_IE7816 0x19 /* 7816 Interrupt Enable Register */
76 #define UART_IS7816 0x1A /* 7816 Interrupt Status Register */
77 #define UART_WP7816T0 0x1B /* 7816 Wait Parameter Register */
78 #define UART_WP7816T1 0x1B /* 7816 Wait Parameter Register */
79 #define UART_WN7816 0x1C /* 7816 Wait N Register */
80 #define UART_WF7816 0x1D /* 7816 Wait FD Register */
81 #define UART_ET7816 0x1E /* 7816 Error Threshold Register */
82 #define UART_TL7816 0x1F /* 7816 Transmit Length Register */
83 #define UART_C6 0x21 /* CEA709.1-B Control Register 6 */
84 #define UART_PCTH 0x22 /* CEA709.1-B Packet Cycle Time Counter High */
85 #define UART_PCTL 0x23 /* CEA709.1-B Packet Cycle Time Counter Low */
86 #define UART_B1T 0x24 /* CEA709.1-B Beta1 Timer */
87 #define UART_SDTH 0x25 /* CEA709.1-B Secondary Delay Timer High */
88 #define UART_SDTL 0x26 /* CEA709.1-B Secondary Delay Timer Low */
89 #define UART_PRE 0x27 /* CEA709.1-B Preamble */
90 #define UART_TPL 0x28 /* CEA709.1-B Transmit Packet Length */
91 #define UART_IE 0x29 /* CEA709.1-B Interrupt Enable Register */
92 #define UART_WB 0x2A /* CEA709.1-B WBASE */
93 #define UART_S3 0x2B /* CEA709.1-B Status Register */
94 #define UART_S4 0x2C /* CEA709.1-B Status Register */
95 #define UART_RPL 0x2D /* CEA709.1-B Received Packet Length */
96 #define UART_RPREL 0x2E /* CEA709.1-B Received Preamble Length */
97 #define UART_CPW 0x2F /* CEA709.1-B Collision Pulse Width */
98 #define UART_RIDT 0x30 /* CEA709.1-B Receive Indeterminate Time */
99 #define UART_TIDT 0x31 /* CEA709.1-B Transmit Indeterminate Time */
101 #define UART_C2_TE (1 << 3) /* Transmitter Enable */
102 #define UART_C2_TIE (1 << 7) /* Transmitter Interrupt Enable */
103 #define UART_C2_RE (1 << 2) /* Receiver Enable */
104 #define UART_C2_RIE (1 << 5) /* Receiver Interrupt Enable */
105 #define UART_S1_TDRE (1 << 7) /* Transmit Data Register Empty Flag */
106 #define UART_S1_RDRF (1 << 5) /* Receive Data Register Full Flag */
107 #define UART_S2_LBKDIF (1 << 7) /* LIN Break Detect Interrupt Flag */
109 #define UART_C4_BRFA 0x1f /* Baud Rate Fine Adjust */
110 #define UART_BDH_SBR 0x1f /* UART Baud Rate Bits */
113 * Low-level UART interface.
115 static int vf_uart_probe(struct uart_bas *bas);
116 static void vf_uart_init(struct uart_bas *bas, int, int, int, int);
117 static void vf_uart_term(struct uart_bas *bas);
118 static void vf_uart_putc(struct uart_bas *bas, int);
119 static int vf_uart_rxready(struct uart_bas *bas);
120 static int vf_uart_getc(struct uart_bas *bas, struct mtx *);
122 void uart_reinit(struct uart_softc *,int,int);
124 static struct uart_ops uart_vybrid_ops = {
125 .probe = vf_uart_probe,
126 .init = vf_uart_init,
127 .term = vf_uart_term,
128 .putc = vf_uart_putc,
129 .rxready = vf_uart_rxready,
130 .getc = vf_uart_getc,
134 vf_uart_probe(struct uart_bas *bas)
141 vf_uart_init(struct uart_bas *bas, int baudrate, int databits,
142 int stopbits, int parity)
148 vf_uart_term(struct uart_bas *bas)
154 vf_uart_putc(struct uart_bas *bas, int c)
157 while (!(uart_getreg(bas, UART_S1) & UART_S1_TDRE))
160 uart_setreg(bas, UART_D, c);
164 vf_uart_rxready(struct uart_bas *bas)
168 usr1 = uart_getreg(bas, UART_S1);
169 if (usr1 & UART_S1_RDRF) {
177 vf_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
183 while (!(uart_getreg(bas, UART_S1) & UART_S1_RDRF))
186 c = uart_getreg(bas, UART_D);
193 * High-level UART interface.
195 struct vf_uart_softc {
196 struct uart_softc base;
200 uart_reinit(struct uart_softc *sc, int clkspeed, int baud)
202 struct uart_bas *bas;
209 printf("Error: cant reconfigure bas\n");
213 uart_setreg(bas, UART_MODEM, 0x00);
216 * Disable transmitter and receiver
219 reg = uart_getreg(bas, UART_C2);
220 reg &= ~(UART_C2_RE | UART_C2_TE);
221 uart_setreg(bas, UART_C2, 0x00);
223 uart_setreg(bas, UART_C1, 0x00);
225 sbr = (uint16_t) (clkspeed / (baud * 16));
226 brfa = (clkspeed / baud) - (sbr * 16);
228 reg = uart_getreg(bas, UART_BDH);
229 reg &= ~UART_BDH_SBR;
230 reg |= ((sbr & 0x1f00) >> 8);
231 uart_setreg(bas, UART_BDH, reg);
234 uart_setreg(bas, UART_BDL, reg);
236 reg = uart_getreg(bas, UART_C4);
237 reg &= ~UART_C4_BRFA;
238 reg |= (brfa & UART_C4_BRFA);
239 uart_setreg(bas, UART_C4, reg);
241 reg = uart_getreg(bas, UART_C2);
242 reg |= (UART_C2_RE | UART_C2_TE);
243 uart_setreg(bas, UART_C2, reg);
247 static int vf_uart_bus_attach(struct uart_softc *);
248 static int vf_uart_bus_detach(struct uart_softc *);
249 static int vf_uart_bus_flush(struct uart_softc *, int);
250 static int vf_uart_bus_getsig(struct uart_softc *);
251 static int vf_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
252 static int vf_uart_bus_ipend(struct uart_softc *);
253 static int vf_uart_bus_param(struct uart_softc *, int, int, int, int);
254 static int vf_uart_bus_probe(struct uart_softc *);
255 static int vf_uart_bus_receive(struct uart_softc *);
256 static int vf_uart_bus_setsig(struct uart_softc *, int);
257 static int vf_uart_bus_transmit(struct uart_softc *);
259 static kobj_method_t vf_uart_methods[] = {
260 KOBJMETHOD(uart_attach, vf_uart_bus_attach),
261 KOBJMETHOD(uart_detach, vf_uart_bus_detach),
262 KOBJMETHOD(uart_flush, vf_uart_bus_flush),
263 KOBJMETHOD(uart_getsig, vf_uart_bus_getsig),
264 KOBJMETHOD(uart_ioctl, vf_uart_bus_ioctl),
265 KOBJMETHOD(uart_ipend, vf_uart_bus_ipend),
266 KOBJMETHOD(uart_param, vf_uart_bus_param),
267 KOBJMETHOD(uart_probe, vf_uart_bus_probe),
268 KOBJMETHOD(uart_receive, vf_uart_bus_receive),
269 KOBJMETHOD(uart_setsig, vf_uart_bus_setsig),
270 KOBJMETHOD(uart_transmit, vf_uart_bus_transmit),
274 static struct uart_class uart_vybrid_class = {
277 sizeof(struct vf_uart_softc),
278 .uc_ops = &uart_vybrid_ops,
280 .uc_rclk = 24000000 /* TODO: get value from CCM */
283 static struct ofw_compat_data compat_data[] = {
284 {"fsl,mvf600-uart", (uintptr_t)&uart_vybrid_class},
285 {NULL, (uintptr_t)NULL},
287 UART_FDT_CLASS_AND_DEVICE(compat_data);
290 vf_uart_bus_attach(struct uart_softc *sc)
292 struct uart_bas *bas;
300 uart_reinit(sc, 66000000, 115200);
302 reg = uart_getreg(bas, UART_C2);
303 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
308 uart_setreg(bas, UART_C2, reg);
314 vf_uart_bus_detach(struct uart_softc *sc)
322 vf_uart_bus_flush(struct uart_softc *sc, int what)
330 vf_uart_bus_getsig(struct uart_softc *sc)
338 vf_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
340 struct uart_bas *bas;
345 uart_lock(sc->sc_hwmtx);
347 case UART_IOCTL_BREAK:
350 case UART_IOCTL_BAUD:
352 *(int*)data = 115200;
358 uart_unlock(sc->sc_hwmtx);
364 vf_uart_bus_ipend(struct uart_softc *sc)
366 struct uart_bas *bas;
375 uart_lock(sc->sc_hwmtx);
377 usr1 = uart_getreg(bas, UART_S1);
378 usr2 = uart_getreg(bas, UART_S2);
379 sfifo = uart_getreg(bas, UART_SFIFO);
382 uart_setreg(bas, UART_S2, usr2);
384 if (usr1 & UART_S1_TDRE) {
385 reg = uart_getreg(bas, UART_C2);
386 reg &= ~(UART_C2_TIE);
387 uart_setreg(bas, UART_C2, reg);
389 if (sc->sc_txbusy != 0) {
390 ipend |= SER_INT_TXIDLE;
394 if (usr1 & UART_S1_RDRF) {
395 reg = uart_getreg(bas, UART_C2);
396 reg &= ~(UART_C2_RIE);
397 uart_setreg(bas, UART_C2, reg);
399 ipend |= SER_INT_RXREADY;
402 if (usr2 & UART_S2_LBKDIF) {
403 ipend |= SER_INT_BREAK;
406 uart_unlock(sc->sc_hwmtx);
412 vf_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
413 int stopbits, int parity)
416 uart_lock(sc->sc_hwmtx);
417 vf_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
418 uart_unlock(sc->sc_hwmtx);
424 vf_uart_bus_probe(struct uart_softc *sc)
428 error = vf_uart_probe(&sc->sc_bas);
435 device_set_desc(sc->sc_dev, "Vybrid Family UART");
440 vf_uart_bus_receive(struct uart_softc *sc)
442 struct uart_bas *bas;
447 uart_lock(sc->sc_hwmtx);
450 while (uart_getreg(bas, UART_S1) & UART_S1_RDRF) {
451 if (uart_rx_full(sc)) {
452 /* No space left in input buffer */
453 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
457 c = uart_getreg(bas, UART_D);
461 /* Reenable Data Ready interrupt */
462 reg = uart_getreg(bas, UART_C2);
463 reg |= (UART_C2_RIE);
464 uart_setreg(bas, UART_C2, reg);
466 uart_unlock(sc->sc_hwmtx);
471 vf_uart_bus_setsig(struct uart_softc *sc, int sig)
473 struct uart_bas *bas;
476 /* TODO: implement (?) */
478 /* XXX workaround to have working console on mount prompt */
479 /* Enable RX interrupt */
481 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
482 reg = uart_getreg(bas, UART_C2);
483 reg |= (UART_C2_RIE);
484 uart_setreg(bas, UART_C2, reg);
491 vf_uart_bus_transmit(struct uart_softc *sc)
493 struct uart_bas *bas = &sc->sc_bas;
498 uart_lock(sc->sc_hwmtx);
501 for (i = 0; i < sc->sc_txdatasz; i++) {
502 uart_setreg(bas, UART_D, sc->sc_txbuf[i] & 0xff);
503 uart_barrier(&sc->sc_bas);
508 /* Call me when ready */
509 reg = uart_getreg(bas, UART_C2);
510 reg |= (UART_C2_TIE);
511 uart_setreg(bas, UART_C2, reg);
513 uart_unlock(sc->sc_hwmtx);