2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Samsung Exynos 5 Inter-Integrated Circuit (I2C)
29 * Chapter 13, Exynos 5 Dual User's Manual Public Rev 1.00
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/malloc.h>
42 #include <sys/timeet.h>
43 #include <sys/timetc.h>
45 #include <dev/iicbus/iiconf.h>
46 #include <dev/iicbus/iicbus.h>
48 #include "iicbus_if.h"
50 #include <dev/fdt/fdt_common.h>
51 #include <dev/ofw/openfirm.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
55 #include <machine/bus.h>
56 #include <machine/fdt.h>
57 #include <machine/cpu.h>
58 #include <machine/intr.h>
60 #include <arm/samsung/exynos/exynos5_common.h>
62 #define I2CCON 0x00 /* Control register */
63 #define ACKGEN (1 << 7) /* Acknowledge Enable */
65 * Source Clock of I2C-bus Transmit Clock Prescaler
67 * 0 = I2CCLK = fPCLK/16
68 * 1 = I2CCLK = fPCLK/512
70 #define I2CCLK (1 << 6)
71 #define IRQ_EN (1 << 5) /* Tx/Rx Interrupt Enable/Disable */
72 #define IPEND (1 << 4) /* Tx/Rx Interrupt Pending Flag */
73 #define CLKVAL_M 0xf /* Transmit Clock Prescaler Mask */
75 #define I2CSTAT 0x04 /* Control/status register */
76 #define I2CMODE_M 0x3 /* Master/Slave Tx/Rx Mode Select */
78 #define I2CMODE_SR 0x0 /* Slave Receive Mode */
79 #define I2CMODE_ST 0x1 /* Slave Transmit Mode */
80 #define I2CMODE_MR 0x2 /* Master Receive Mode */
81 #define I2CMODE_MT 0x3 /* Master Transmit Mode */
82 #define I2CSTAT_BSY (1 << 5) /* Busy Signal Status bit */
83 #define I2C_START_STOP (1 << 5) /* Busy Signal Status bit */
84 #define RXTX_EN (1 << 4) /* Data Output Enable/Disable */
85 #define ARBST (1 << 3) /* Arbitration status flag */
86 #define ADDAS (1 << 2) /* Address-as-slave Status Flag */
87 #define ADDZERO (1 << 1) /* Address Zero Status Flag */
88 #define ACKRECVD (1 << 0) /* Last-received Bit Status Flag */
89 #define I2CADD 0x08 /* Address register */
90 #define I2CDS 0x0C /* Transmit/receive data shift */
91 #define I2CLC 0x10 /* Multi-master line control */
92 #define FILTER_EN (1 << 2) /* Filter Enable bit */
93 #define SDAOUT_DELAY_M 0x3 /* SDA Line Delay Length */
94 #define SDAOUT_DELAY_S 0
97 #define DPRINTF(fmt, args...) \
100 #define DPRINTF(fmt, args...)
103 static int i2c_start(device_t, u_char, int);
104 static int i2c_stop(device_t);
105 static int i2c_reset(device_t, u_char, u_char, u_char *);
106 static int i2c_read(device_t, char *, int, int *, int, int);
107 static int i2c_write(device_t, const char *, int, int *, int);
110 struct resource *res[2];
112 bus_space_handle_t bsh;
120 static struct resource_spec i2c_spec[] = {
121 { SYS_RES_MEMORY, 0, RF_ACTIVE },
122 { SYS_RES_IRQ, 0, RF_ACTIVE },
127 i2c_probe(device_t dev)
130 if (!ofw_bus_status_okay(dev))
133 if (!ofw_bus_is_compatible(dev, "exynos,i2c"))
136 device_set_desc(dev, "Samsung Exynos 5 I2C controller");
137 return (BUS_PROBE_DEFAULT);
141 clear_ipend(struct i2c_softc *sc)
145 reg = READ1(sc, I2CCON);
147 WRITE1(sc, I2CCON, reg);
153 i2c_attach(device_t dev)
155 struct i2c_softc *sc;
158 sc = device_get_softc(dev);
161 mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF);
163 if (bus_alloc_resources(dev, i2c_spec, sc->res)) {
164 device_printf(dev, "could not allocate resources\n");
168 /* Memory interface */
169 sc->bst = rman_get_bustag(sc->res[0]);
170 sc->bsh = rman_get_bushandle(sc->res[0]);
172 sc->iicbus = device_add_child(dev, "iicbus", -1);
173 if (sc->iicbus == NULL) {
174 device_printf(dev, "could not add iicbus child");
175 mtx_destroy(&sc->mutex);
179 WRITE1(sc, I2CSTAT, 0);
180 WRITE1(sc, I2CADD, 0x00);
184 reg |= (I2CMODE_MT << I2CMODE_S);
185 WRITE1(sc, I2CSTAT, reg);
187 bus_generic_attach(dev);
193 wait_for_iif(struct i2c_softc *sc)
200 reg = READ1(sc, I2CCON);
207 return (IIC_ETIMEOUT);
211 wait_for_nibb(struct i2c_softc *sc)
217 if ((READ1(sc, I2CSTAT) & I2CSTAT_BSY) == 0)
222 return (IIC_ETIMEOUT);
226 is_ack(struct i2c_softc *sc)
230 stat = READ1(sc, I2CSTAT);
240 i2c_start(device_t dev, u_char slave, int timeout)
242 struct i2c_softc *sc;
246 sc = device_get_softc(dev);
248 DPRINTF("i2c start\n");
250 mtx_lock(&sc->mutex);
253 DPRINTF("I2CCON == 0x%08x\n", READ1(sc, I2CCON));
254 DPRINTF("I2CSTAT == 0x%08x\n", READ1(sc, I2CSTAT));
265 error = wait_for_nibb(sc);
267 mtx_unlock(&sc->mutex);
268 DPRINTF("cant i2c start: IIC_EBUSBSY\n");
269 return (IIC_EBUSBSY);
272 reg = READ1(sc, I2CCON);
273 reg |= (IRQ_EN | ACKGEN);
274 WRITE1(sc, I2CCON, reg);
276 WRITE1(sc, I2CDS, slave);
280 reg |= I2C_START_STOP;
281 reg |= (I2CMODE_MT << I2CMODE_S);
282 WRITE1(sc, I2CSTAT, reg);
284 error = wait_for_iif(sc);
286 DPRINTF("cant i2c start: iif error\n");
288 mtx_unlock(&sc->mutex);
293 DPRINTF("cant i2c start: no ack\n");
295 mtx_unlock(&sc->mutex);
299 mtx_unlock(&sc->mutex);
304 i2c_stop(device_t dev)
306 struct i2c_softc *sc;
310 sc = device_get_softc(dev);
312 DPRINTF("i2c stop\n");
314 mtx_lock(&sc->mutex);
316 reg = READ1(sc, I2CSTAT);
317 int mode = (reg >> I2CMODE_S) & I2CMODE_M;
320 reg |= (mode << I2CMODE_S);
321 WRITE1(sc, I2CSTAT, reg);
325 error = wait_for_nibb(sc);
327 DPRINTF("cant i2c stop: nibb error\n");
331 mtx_unlock(&sc->mutex);
336 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
338 struct i2c_softc *sc;
340 sc = device_get_softc(dev);
342 DPRINTF("i2c reset\n");
344 mtx_lock(&sc->mutex);
348 mtx_unlock(&sc->mutex);
354 i2c_read(device_t dev, char *buf, int len,
355 int *read, int last, int delay)
357 struct i2c_softc *sc;
362 sc = device_get_softc(dev);
364 DPRINTF("i2c read\n");
367 reg |= (I2CMODE_MR << I2CMODE_S);
368 reg |= I2C_START_STOP;
369 WRITE1(sc, I2CSTAT, reg);
372 mtx_lock(&sc->mutex);
378 while (*read < len) {
380 /* Do not ack last read */
381 if (*read == (len - 1)) {
382 reg = READ1(sc, I2CCON);
384 WRITE1(sc, I2CCON, reg);
389 error = wait_for_iif(sc);
391 DPRINTF("cant i2c read: iif error\n");
392 mtx_unlock(&sc->mutex);
396 d = READ1(sc, I2CDS);
397 DPRINTF("0x%02x ", d);
403 mtx_unlock(&sc->mutex);
408 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout)
410 struct i2c_softc *sc;
413 sc = device_get_softc(dev);
415 DPRINTF("i2c write\n");
419 mtx_lock(&sc->mutex);
422 while (*sent < len) {
424 DPRINTF("0x%02x ", d);
426 WRITE1(sc, I2CDS, d);
431 error = wait_for_iif(sc);
433 DPRINTF("cant i2c write: iif error\n");
434 mtx_unlock(&sc->mutex);
439 DPRINTF("cant i2c write: no ack\n");
440 mtx_unlock(&sc->mutex);
448 mtx_unlock(&sc->mutex);
452 static device_method_t i2c_methods[] = {
453 DEVMETHOD(device_probe, i2c_probe),
454 DEVMETHOD(device_attach, i2c_attach),
456 DEVMETHOD(iicbus_callback, iicbus_null_callback),
457 DEVMETHOD(iicbus_start, i2c_start),
458 DEVMETHOD(iicbus_stop, i2c_stop),
459 DEVMETHOD(iicbus_reset, i2c_reset),
460 DEVMETHOD(iicbus_read, i2c_read),
461 DEVMETHOD(iicbus_write, i2c_write),
462 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
467 static driver_t i2c_driver = {
470 sizeof(struct i2c_softc),
473 static devclass_t i2c_devclass;
475 DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0);
476 DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0);