2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #define CPSW_SS_OFFSET 0x0000
33 #define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00)
34 #define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
35 #define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
36 #define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
37 #define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24)
39 #define CPSW_PORT_OFFSET 0x0100
40 #define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100))
41 #define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100))
42 #define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100))
43 #define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C)
44 #define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020)
45 #define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100))
46 #define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100))
48 #define CPSW_CPDMA_OFFSET 0x0800
49 #define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04)
50 #define CPSW_CPDMA_TX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x08)
51 #define CPSW_CPDMA_RX_CONTROL (CPSW_CPDMA_OFFSET + 0x14)
52 #define CPSW_CPDMA_RX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x18)
53 #define CPSW_CPDMA_SOFT_RESET (CPSW_CPDMA_OFFSET + 0x1c)
54 #define CPSW_CPDMA_DMACONTROL (CPSW_CPDMA_OFFSET + 0x20)
55 #define CPSW_CPDMA_DMASTATUS (CPSW_CPDMA_OFFSET + 0x24)
56 #define CPSW_CPDMA_RX_BUFFER_OFFSET (CPSW_CPDMA_OFFSET + 0x28)
57 #define CPSW_CPDMA_TX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0x80)
58 #define CPSW_CPDMA_TX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0x84)
59 #define CPSW_CPDMA_TX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0x88)
60 #define CPSW_CPDMA_TX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0x8C)
61 #define CPSW_CPDMA_CPDMA_EOI_VECTOR (CPSW_CPDMA_OFFSET + 0x94)
62 #define CPSW_CPDMA_RX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xA0)
63 #define CPSW_CPDMA_RX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xA4)
64 #define CPSW_CPDMA_RX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xA8)
65 #define CPSW_CPDMA_RX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xAc)
66 #define CPSW_CPDMA_DMA_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xB0)
67 #define CPSW_CPDMA_DMA_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xB4)
68 #define CPSW_CPDMA_DMA_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xB8)
69 #define CPSW_CPDMA_DMA_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xBC)
70 #define CPSW_CPDMA_RX_FREEBUFFER(p) (CPSW_CPDMA_OFFSET + 0x0e0 + ((p) * 0x04))
72 #define CPSW_STATS_OFFSET 0x0900
74 #define CPSW_STATERAM_OFFSET 0x0A00
75 #define CPSW_CPDMA_TX_HDP(p) (CPSW_STATERAM_OFFSET + 0x00 + ((p) * 0x04))
76 #define CPSW_CPDMA_RX_HDP(p) (CPSW_STATERAM_OFFSET + 0x20 + ((p) * 0x04))
77 #define CPSW_CPDMA_TX_CP(p) (CPSW_STATERAM_OFFSET + 0x40 + ((p) * 0x04))
78 #define CPSW_CPDMA_RX_CP(p) (CPSW_STATERAM_OFFSET + 0x60 + ((p) * 0x04))
80 #define CPSW_CPTS_OFFSET 0x0C00
82 #define CPSW_ALE_OFFSET 0x0D00
83 #define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08)
84 #define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20)
85 #define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34)
86 #define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38)
87 #define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C)
88 #define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04))
90 /* SL1 is at 0x0D80, SL2 is at 0x0DC0 */
91 #define CPSW_SL_OFFSET 0x0D80
92 #define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04)
93 #define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08)
94 #define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C)
95 #define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10)
96 #define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18)
97 #define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C)
98 #define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24)
100 #define MDIO_OFFSET 0x1000
101 #define MDIOCONTROL (MDIO_OFFSET + 0x04)
102 #define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80)
103 #define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84)
105 #define CPSW_WR_OFFSET 0x1200
106 #define CPSW_WR_SOFT_RESET (CPSW_WR_OFFSET + 0x04)
107 #define CPSW_WR_CONTROL (CPSW_WR_OFFSET + 0x08)
108 #define CPSW_WR_INT_CONTROL (CPSW_WR_OFFSET + 0x0c)
109 #define CPSW_WR_C_RX_THRESH_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x10)
110 #define CPSW_WR_C_RX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x14)
111 #define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18)
112 #define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C)
113 #define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40)
114 #define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44)
115 #define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48)
116 #define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C)
118 #define CPSW_CPPI_RAM_OFFSET 0x2000
119 #define CPSW_CPPI_RAM_SIZE 0x2000
121 #define CPDMA_BD_SOP (1<<15)
122 #define CPDMA_BD_EOP (1<<14)
123 #define CPDMA_BD_OWNER (1<<13)
124 #define CPDMA_BD_EOQ (1<<12)
125 #define CPDMA_BD_TDOWNCMPLT (1<<11)
126 #define CPDMA_BD_PKT_ERR_MASK (3<< 4)
128 struct cpsw_cpdma_bd {
129 volatile uint32_t next;
130 volatile uint32_t bufptr;
131 volatile uint16_t buflen;
132 volatile uint16_t bufoff;
133 volatile uint16_t pktlen;
134 volatile uint16_t flags;
137 #endif /*_IF_CPSWREG_H */