2 * Copyright 2014 Luiz Otavio O Souza <loos@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/limits.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/resource.h>
41 #include <sys/sysctl.h>
43 #include <machine/bus.h>
45 #include <dev/ofw/openfirm.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
49 #include <arm/ti/ti_prcm.h>
50 #include <arm/ti/ti_adcreg.h>
51 #include <arm/ti/ti_adcvar.h>
53 /* Define our 8 steps, one for each input channel. */
54 static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = {
55 { .stepconfig = ADC_STEPCFG1, .stepdelay = ADC_STEPDLY1 },
56 { .stepconfig = ADC_STEPCFG2, .stepdelay = ADC_STEPDLY2 },
57 { .stepconfig = ADC_STEPCFG3, .stepdelay = ADC_STEPDLY3 },
58 { .stepconfig = ADC_STEPCFG4, .stepdelay = ADC_STEPDLY4 },
59 { .stepconfig = ADC_STEPCFG5, .stepdelay = ADC_STEPDLY5 },
60 { .stepconfig = ADC_STEPCFG6, .stepdelay = ADC_STEPDLY6 },
61 { .stepconfig = ADC_STEPCFG7, .stepdelay = ADC_STEPDLY7 },
62 { .stepconfig = ADC_STEPCFG8, .stepdelay = ADC_STEPDLY8 },
65 static int ti_adc_samples[5] = { 0, 2, 4, 8, 16 };
68 ti_adc_enable(struct ti_adc_softc *sc)
71 TI_ADC_LOCK_ASSERT(sc);
73 if (sc->sc_last_state == 1)
76 /* Enable the FIFO0 threshold and the end of sequence interrupt. */
77 ADC_WRITE4(sc, ADC_IRQENABLE_SET,
78 ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ);
80 /* Enable the ADC. Run thru enabled steps, start the conversions. */
81 ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) | ADC_CTRL_ENABLE);
83 sc->sc_last_state = 1;
87 ti_adc_disable(struct ti_adc_softc *sc)
92 TI_ADC_LOCK_ASSERT(sc);
94 if (sc->sc_last_state == 0)
97 /* Disable all the enabled steps. */
98 ADC_WRITE4(sc, ADC_STEPENABLE, 0);
100 /* Disable the ADC. */
101 ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE);
103 /* Disable the FIFO0 threshold and the end of sequence interrupt. */
104 ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
105 ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ);
107 /* ACK any pending interrupt. */
108 ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS));
110 /* Drain the FIFO data. */
111 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
113 data = ADC_READ4(sc, ADC_FIFO0DATA);
114 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
117 sc->sc_last_state = 0;
121 ti_adc_setup(struct ti_adc_softc *sc)
126 TI_ADC_LOCK_ASSERT(sc);
128 /* Check for enabled inputs. */
130 for (ain = 0; ain < TI_ADC_NPINS; ain++) {
131 if (ti_adc_inputs[ain].enable)
132 enabled |= (1U << (ain + 1));
135 /* Set the ADC global status. */
138 /* Update the enabled steps. */
139 if (enabled != ADC_READ4(sc, ADC_STEPENABLE))
140 ADC_WRITE4(sc, ADC_STEPENABLE, enabled);
148 ti_adc_input_setup(struct ti_adc_softc *sc, int32_t ain)
150 struct ti_adc_input *input;
153 TI_ADC_LOCK_ASSERT(sc);
155 input = &ti_adc_inputs[ain];
156 reg = input->stepconfig;
157 val = ADC_READ4(sc, reg);
159 /* Set single ended operation. */
160 val &= ~ADC_STEP_DIFF_CNTRL;
162 /* Set the negative voltage reference. */
163 val &= ~ADC_STEP_RFM_MSK;
164 val |= ADC_STEP_RFM_VREFN << ADC_STEP_RFM_SHIFT;
166 /* Set the positive voltage reference. */
167 val &= ~ADC_STEP_RFP_MSK;
168 val |= ADC_STEP_RFP_VREFP << ADC_STEP_RFP_SHIFT;
170 /* Set the samples average. */
171 val &= ~ADC_STEP_AVG_MSK;
172 val |= input->samples << ADC_STEP_AVG_SHIFT;
174 /* Select the desired input. */
175 val &= ~ADC_STEP_INP_MSK;
176 val |= ain << ADC_STEP_INP_SHIFT;
178 /* Set the ADC to one-shot mode. */
179 val &= ~ADC_STEP_MODE_MSK;
181 ADC_WRITE4(sc, reg, val);
185 ti_adc_reset(struct ti_adc_softc *sc)
189 TI_ADC_LOCK_ASSERT(sc);
191 /* Disable all the inputs. */
192 for (ain = 0; ain < TI_ADC_NPINS; ain++)
193 ti_adc_inputs[ain].enable = 0;
197 ti_adc_clockdiv_proc(SYSCTL_HANDLER_ARGS)
200 struct ti_adc_softc *sc;
202 sc = (struct ti_adc_softc *)arg1;
205 reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1;
208 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
209 if (error != 0 || req->newptr == NULL)
213 * The actual written value is the prescaler setting - 1.
214 * Enforce a minimum value of 10 (i.e. 9) which limits the maximum
215 * ADC clock to ~2.4Mhz (CLK_M_OSC / 10).
224 /* Disable the ADC. */
226 /* Update the ADC prescaler setting. */
227 ADC_WRITE4(sc, ADC_CLKDIV, reg);
228 /* Enable the ADC again. */
236 ti_adc_enable_proc(SYSCTL_HANDLER_ARGS)
240 struct ti_adc_softc *sc;
241 struct ti_adc_input *input;
243 input = (struct ti_adc_input *)arg1;
246 enable = input->enable;
247 error = sysctl_handle_int(oidp, &enable, sizeof(enable),
249 if (error != 0 || req->newptr == NULL)
256 /* Setup the ADC as needed. */
257 if (input->enable != enable) {
258 input->enable = enable;
260 if (input->enable == 0)
269 ti_adc_open_delay_proc(SYSCTL_HANDLER_ARGS)
272 struct ti_adc_softc *sc;
273 struct ti_adc_input *input;
275 input = (struct ti_adc_input *)arg1;
279 reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY;
282 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
283 if (error != 0 || req->newptr == NULL)
290 ADC_WRITE4(sc, input->stepdelay, reg & ADC_STEP_OPEN_DELAY);
297 ti_adc_samples_avg_proc(SYSCTL_HANDLER_ARGS)
299 int error, samples, i;
300 struct ti_adc_softc *sc;
301 struct ti_adc_input *input;
303 input = (struct ti_adc_input *)arg1;
306 if (input->samples > nitems(ti_adc_samples))
307 input->samples = nitems(ti_adc_samples);
308 samples = ti_adc_samples[input->samples];
310 error = sysctl_handle_int(oidp, &samples, 0, req);
311 if (error != 0 || req->newptr == NULL)
315 if (samples != ti_adc_samples[input->samples]) {
317 for (i = 0; i < nitems(ti_adc_samples); i++)
318 if (samples >= ti_adc_samples[i])
320 ti_adc_input_setup(sc, input->input);
328 ti_adc_read_data(struct ti_adc_softc *sc)
331 struct ti_adc_input *input;
334 TI_ADC_LOCK_ASSERT(sc);
336 /* Read the available data. */
337 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
339 data = ADC_READ4(sc, ADC_FIFO0DATA);
340 ain = (data & ADC_FIFO_STEP_ID_MSK) >> ADC_FIFO_STEP_ID_SHIFT;
341 input = &ti_adc_inputs[ain];
342 if (input->enable == 0)
345 input->value = (int32_t)(data & ADC_FIFO_DATA_MSK);
346 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
351 ti_adc_intr(void *arg)
353 struct ti_adc_softc *sc;
356 sc = (struct ti_adc_softc *)arg;
358 status = ADC_READ4(sc, ADC_IRQSTATUS);
361 if (status & ~(ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ))
362 device_printf(sc->sc_dev, "stray interrupt: %#x\n", status);
365 /* ACK the interrupt. */
366 ADC_WRITE4(sc, ADC_IRQSTATUS, status);
368 /* Read the available data. */
369 if (status & ADC_IRQ_FIFO0_THRES)
370 ti_adc_read_data(sc);
372 /* Start the next conversion ? */
373 if (status & ADC_IRQ_END_OF_SEQ)
379 ti_adc_sysctl_init(struct ti_adc_softc *sc)
382 struct sysctl_ctx_list *ctx;
383 struct sysctl_oid *tree_node, *inp_node, *inpN_node;
384 struct sysctl_oid_list *tree, *inp_tree, *inpN_tree;
388 * Add per-pin sysctl tree/handlers.
390 ctx = device_get_sysctl_ctx(sc->sc_dev);
391 tree_node = device_get_sysctl_tree(sc->sc_dev);
392 tree = SYSCTL_CHILDREN(tree_node);
393 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clockdiv",
394 CTLFLAG_RW | CTLTYPE_UINT, sc, 0,
395 ti_adc_clockdiv_proc, "IU", "ADC clock prescaler");
396 inp_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "ain",
397 CTLFLAG_RD, NULL, "ADC inputs");
398 inp_tree = SYSCTL_CHILDREN(inp_node);
400 for (ain = 0; ain < TI_ADC_NPINS; ain++) {
402 snprintf(pinbuf, sizeof(pinbuf), "%d", ain);
403 inpN_node = SYSCTL_ADD_NODE(ctx, inp_tree, OID_AUTO, pinbuf,
404 CTLFLAG_RD, NULL, "ADC input");
405 inpN_tree = SYSCTL_CHILDREN(inpN_node);
407 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "enable",
408 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0,
409 ti_adc_enable_proc, "IU", "Enable ADC input");
410 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "open_delay",
411 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0,
412 ti_adc_open_delay_proc, "IU", "ADC open delay");
413 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "samples_avg",
414 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0,
415 ti_adc_samples_avg_proc, "IU", "ADC samples average");
416 SYSCTL_ADD_INT(ctx, inpN_tree, OID_AUTO, "input",
417 CTLFLAG_RD, &ti_adc_inputs[ain].value, 0,
418 "Converted raw value for the ADC input");
423 ti_adc_inputs_init(struct ti_adc_softc *sc)
426 struct ti_adc_input *input;
429 for (ain = 0; ain < TI_ADC_NPINS; ain++) {
430 input = &ti_adc_inputs[ain];
436 ti_adc_input_setup(sc, ain);
442 ti_adc_idlestep_init(struct ti_adc_softc *sc)
446 val = ADC_READ4(sc, ADC_IDLECONFIG);
448 /* Set single ended operation. */
449 val &= ~ADC_STEP_DIFF_CNTRL;
451 /* Set the negative voltage reference. */
452 val &= ~ADC_STEP_RFM_MSK;
453 val |= ADC_STEP_RFM_VREFN << ADC_STEP_RFM_SHIFT;
455 /* Set the positive voltage reference. */
456 val &= ~ADC_STEP_RFP_MSK;
457 val |= ADC_STEP_RFP_VREFP << ADC_STEP_RFP_SHIFT;
459 /* Connect the input to VREFN. */
460 val &= ~ADC_STEP_INP_MSK;
461 val |= ADC_STEP_IN_VREFN << ADC_STEP_INP_SHIFT;
463 ADC_WRITE4(sc, ADC_IDLECONFIG, val);
467 ti_adc_probe(device_t dev)
470 if (!ofw_bus_is_compatible(dev, "ti,adc"))
472 device_set_desc(dev, "TI ADC controller");
474 return (BUS_PROBE_DEFAULT);
478 ti_adc_attach(device_t dev)
481 struct ti_adc_softc *sc;
484 sc = device_get_softc(dev);
488 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
490 if (!sc->sc_mem_res) {
491 device_printf(dev, "cannot allocate memory window\n");
496 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
498 if (!sc->sc_irq_res) {
499 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
500 device_printf(dev, "cannot allocate interrupt\n");
504 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
505 NULL, ti_adc_intr, sc, &sc->sc_intrhand) != 0) {
506 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
507 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
508 device_printf(dev, "Unable to setup the irq handler.\n");
512 /* Activate the ADC_TSC module. */
513 err = ti_prcm_clk_enable(TSC_ADC_CLK);
517 /* Check the ADC revision. */
518 rev = ADC_READ4(sc, ADC_REVISION);
520 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n",
521 (rev & ADC_REV_SCHEME_MSK) >> ADC_REV_SCHEME_SHIFT,
522 (rev & ADC_REV_FUNC_MSK) >> ADC_REV_FUNC_SHIFT,
523 (rev & ADC_REV_RTL_MSK) >> ADC_REV_RTL_SHIFT,
524 (rev & ADC_REV_MAJOR_MSK) >> ADC_REV_MAJOR_SHIFT,
525 rev & ADC_REV_MINOR_MSK,
526 (rev & ADC_REV_CUSTOM_MSK) >> ADC_REV_CUSTOM_SHIFT);
529 * Disable the step write protect and make it store the step ID for
530 * the captured data on FIFO.
532 reg = ADC_READ4(sc, ADC_CTRL);
533 ADC_WRITE4(sc, ADC_CTRL, reg | ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID);
536 * Set the ADC prescaler to 2400 (yes, the actual value written here
538 * This sets the ADC clock to ~10Khz (CLK_M_OSC / 2400).
540 ADC_WRITE4(sc, ADC_CLKDIV, 2399);
542 TI_ADC_LOCK_INIT(sc);
544 ti_adc_idlestep_init(sc);
545 ti_adc_inputs_init(sc);
546 ti_adc_sysctl_init(sc);
552 ti_adc_detach(device_t dev)
554 struct ti_adc_softc *sc;
556 sc = device_get_softc(dev);
558 /* Turn off the ADC. */
564 TI_ADC_LOCK_DESTROY(sc);
567 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
569 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
571 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
573 return (bus_generic_detach(dev));
576 static device_method_t ti_adc_methods[] = {
577 DEVMETHOD(device_probe, ti_adc_probe),
578 DEVMETHOD(device_attach, ti_adc_attach),
579 DEVMETHOD(device_detach, ti_adc_detach),
584 static driver_t ti_adc_driver = {
587 sizeof(struct ti_adc_softc),
590 static devclass_t ti_adc_devclass;
592 DRIVER_MODULE(ti_adc, simplebus, ti_adc_driver, ti_adc_devclass, 0, 0);
593 MODULE_VERSION(ti_adc, 1);
594 MODULE_DEPEND(ti_adc, simplebus, 1, 1, 1);