2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Driver for the I2C module on the TI SoC.
31 * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c).
33 * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses,
34 * 32 bit data access is not allowed and can corrupt register content.
36 * This driver currently doesn't use DMA for the transfer, although I hope to
37 * incorporate that sometime in the future. The idea being that for transaction
38 * larger than a certain size the DMA engine is used, for anything less the
39 * normal interrupt/fifo driven option is used.
42 * WARNING: This driver uses mtx_sleep and interrupts to perform transactions,
43 * which means you can't do a transaction during startup before the interrupts
44 * have been enabled. Hint - the freebsd function config_intrhook_establish().
47 #include <sys/cdefs.h>
48 __FBSDID("$FreeBSD$");
50 #include <sys/param.h>
51 #include <sys/systm.h>
54 #include <sys/kernel.h>
57 #include <sys/malloc.h>
58 #include <sys/module.h>
59 #include <sys/mutex.h>
61 #include <sys/sysctl.h>
62 #include <machine/bus.h>
64 #include <dev/ofw/openfirm.h>
65 #include <dev/ofw/ofw_bus.h>
66 #include <dev/ofw/ofw_bus_subr.h>
68 #include <arm/ti/ti_cpuid.h>
69 #include <arm/ti/ti_prcm.h>
70 #include <arm/ti/ti_i2c.h>
72 #include <dev/iicbus/iiconf.h>
73 #include <dev/iicbus/iicbus.h>
75 #include "iicbus_if.h"
78 * I2C device driver context, a pointer to this is stored in the device
85 struct resource* sc_irq_res;
86 struct resource* sc_mem_res;
93 struct iic_msg* sc_buffer;
103 struct ti_i2c_clock_config
105 u_int frequency; /* Bus frequency in Hz */
106 uint8_t psc; /* Fast/Standard mode prescale divider */
107 uint8_t scll; /* Fast/Standard mode SCL low time */
108 uint8_t sclh; /* Fast/Standard mode SCL high time */
109 uint8_t hsscll; /* High Speed mode SCL low time */
110 uint8_t hssclh; /* High Speed mode SCL high time */
113 #if defined(SOC_OMAP3)
114 #error "Unsupported SoC"
117 #if defined(SOC_OMAP4)
119 * OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)).
120 * The prescaler values for 100KHz and 400KHz modes come from the table in the
121 * OMAP4 TRM. The table doesn't list 1MHz; these values should give that speed.
123 static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = {
124 { 100000, 23, 13, 15, 0, 0},
125 { 400000, 9, 5, 7, 0, 0},
126 { 1000000, 3, 5, 7, 0, 0},
127 /* { 3200000, 1, 113, 115, 7, 10}, - HS mode */
128 { 0 /* Table terminator */ }
132 #if defined(SOC_TI_AM335X)
134 * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5))
135 * In all cases we prescale the clock to 24MHz as recommended in the manual.
137 static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = {
138 { 100000, 1, 111, 117, 0, 0},
139 { 400000, 1, 23, 25, 0, 0},
140 { 1000000, 1, 5, 7, 0, 0},
141 { 0 /* Table terminator */ }
146 * Locking macros used throughout the driver
148 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
149 #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
150 #define TI_I2C_LOCK_INIT(_sc) \
151 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
153 #define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
154 #define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
155 #define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
158 #define ti_i2c_dbg(_sc, fmt, args...) \
159 device_printf((_sc)->sc_dev, fmt, ##args)
161 #define ti_i2c_dbg(_sc, fmt, args...)
165 * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers
166 * @sc: I2C device context
167 * @off: the byte offset within the register bank to read from.
171 * No locking required
174 * 16-bit value read from the register.
176 static inline uint16_t
177 ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off)
180 return (bus_read_2(sc->sc_mem_res, off));
184 * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers
185 * @sc: I2C device context
186 * @off: the byte offset within the register bank to read from.
187 * @val: the value to write into the register
190 * No locking required
193 * 16-bit value read from the register.
196 ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val)
199 bus_write_2(sc->sc_mem_res, off, val);
203 ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status)
209 /* Check for the error conditions. */
210 if (status & I2C_STAT_NACK) {
211 /* No ACK from slave. */
212 ti_i2c_dbg(sc, "NACK\n");
213 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK);
214 sc->sc_error = ENXIO;
215 } else if (status & I2C_STAT_AL) {
216 /* Arbitration lost. */
217 ti_i2c_dbg(sc, "Arbitration lost\n");
218 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL);
219 sc->sc_error = ENXIO;
222 /* Check if we have finished. */
223 if (status & I2C_STAT_ARDY) {
224 /* Register access ready - transaction complete basically. */
225 ti_i2c_dbg(sc, "ARDY transaction complete\n");
226 if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) {
227 ti_i2c_write_2(sc, I2C_REG_CON,
228 sc->sc_con_reg | I2C_CON_STP);
230 ti_i2c_write_2(sc, I2C_REG_STATUS,
231 I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY |
232 I2C_STAT_XDR | I2C_STAT_XRDY);
236 if (sc->sc_buffer->flags & IIC_M_RD) {
237 /* Read some data. */
238 if (status & I2C_STAT_RDR) {
240 * Receive draining interrupt - last data received.
241 * The set FIFO threshold wont be reached to trigger
244 ti_i2c_dbg(sc, "Receive draining interrupt\n");
247 * Drain the FIFO. Read the pending data in the FIFO.
249 amount = sc->sc_buffer->len - sc->sc_buffer_pos;
250 } else if (status & I2C_STAT_RRDY) {
252 * Receive data ready interrupt - FIFO has reached the
255 ti_i2c_dbg(sc, "Receive data ready interrupt\n");
257 amount = min(sc->sc_fifo_trsh,
258 sc->sc_buffer->len - sc->sc_buffer_pos);
261 /* Read the bytes from the fifo. */
262 for (i = 0; i < amount; i++)
263 sc->sc_buffer->buf[sc->sc_buffer_pos++] =
264 (uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff);
266 if (status & I2C_STAT_RDR)
267 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR);
268 if (status & I2C_STAT_RRDY)
269 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY);
272 /* Write some data. */
273 if (status & I2C_STAT_XDR) {
275 * Transmit draining interrupt - FIFO level is below
276 * the set threshold and the amount of data still to
277 * be transferred wont reach the set FIFO threshold.
279 ti_i2c_dbg(sc, "Transmit draining interrupt\n");
282 * Drain the TX data. Write the pending data in the
285 amount = sc->sc_buffer->len - sc->sc_buffer_pos;
286 } else if (status & I2C_STAT_XRDY) {
288 * Transmit data ready interrupt - the FIFO level
289 * is below the set threshold.
291 ti_i2c_dbg(sc, "Transmit data ready interrupt\n");
293 amount = min(sc->sc_fifo_trsh,
294 sc->sc_buffer->len - sc->sc_buffer_pos);
297 /* Write the bytes from the fifo. */
298 for (i = 0; i < amount; i++)
299 ti_i2c_write_2(sc, I2C_REG_DATA,
300 sc->sc_buffer->buf[sc->sc_buffer_pos++]);
302 if (status & I2C_STAT_XDR)
303 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR);
304 if (status & I2C_STAT_XRDY)
305 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY);
312 * ti_i2c_intr - interrupt handler for the I2C module
313 * @dev: i2c device handle
318 * Called from timer context
321 * EH_HANDLED or EH_NOT_HANDLED
324 ti_i2c_intr(void *arg)
327 struct ti_i2c_softc *sc;
328 uint16_t events, status;
330 sc = (struct ti_i2c_softc *)arg;
334 status = ti_i2c_read_2(sc, I2C_REG_STATUS);
340 /* Save enabled interrupts. */
341 events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET);
343 /* We only care about enabled interrupts. */
348 if (sc->sc_buffer != NULL)
349 done = ti_i2c_transfer_intr(sc, status);
351 ti_i2c_dbg(sc, "Transfer interrupt without buffer\n");
352 sc->sc_error = EINVAL;
357 /* Wakeup the process that started the transaction. */
364 * ti_i2c_transfer - called to perform the transfer
365 * @dev: i2c device handle
366 * @msgs: the messages to send/receive
367 * @nmsgs: the number of messages in the msgs array
374 * 0 on function succeeded
375 * EINVAL if invalid message is passed as an arg
378 ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
380 int err, i, repstart, timeout;
381 struct ti_i2c_softc *sc;
384 sc = device_get_softc(dev);
387 /* If the controller is busy wait until it is available. */
388 while (sc->sc_bus_inuse == 1)
389 mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0);
391 /* Now we have control over the I2C controller. */
392 sc->sc_bus_inuse = 1;
396 for (i = 0; i < nmsgs; i++) {
398 sc->sc_buffer = &msgs[i];
399 sc->sc_buffer_pos = 0;
402 /* Zero byte transfers aren't allowed. */
403 if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL ||
404 sc->sc_buffer->len == 0) {
409 /* Check if the i2c bus is free. */
412 * On repeated start we send the START condition while
416 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
417 if (timeout++ > 100) {
427 if (sc->sc_buffer->flags & IIC_M_NOSTOP)
430 /* Set the slave address. */
431 ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1);
433 /* Write the data length. */
434 ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len);
436 /* Clear the RX and the TX FIFO. */
437 reg = ti_i2c_read_2(sc, I2C_REG_BUF);
438 reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR;
439 ti_i2c_write_2(sc, I2C_REG_BUF, reg);
441 reg = sc->sc_con_reg | I2C_CON_STT;
444 if ((sc->sc_buffer->flags & IIC_M_RD) == 0)
446 ti_i2c_write_2(sc, I2C_REG_CON, reg);
448 /* Wait for an event. */
449 err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", hz);
459 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
465 /* Put the controller in master mode again. */
466 if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0)
467 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
469 sc->sc_buffer = NULL;
470 sc->sc_bus_inuse = 0;
472 /* Wake up the processes that are waiting for the bus. */
481 * ti_i2c_callback - as we only provide iicbus_transfer() interface
482 * we don't need to implement the serialization here.
483 * @dev: i2c device handle
488 * Called from timer context
491 * EH_HANDLED or EH_NOT_HANDLED
494 ti_i2c_callback(device_t dev, int index, caddr_t data)
499 case IIC_REQUEST_BUS:
502 case IIC_RELEASE_BUS:
513 ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed)
516 struct ti_i2c_clock_config *clkcfg;
518 uint16_t fifo_trsh, reg, scll, sclh;
523 clkcfg = ti_omap4_i2c_clock_configs;
528 clkcfg = ti_am335x_i2c_clock_configs;
532 panic("Unknown Ti SoC, unable to reset the i2c");
536 * If we haven't attached the bus yet, just init at the default slow
537 * speed. This lets us get the hardware initialized enough to attach
538 * the bus which is where the real speed configuration is handled. After
539 * the bus is attached, get the configured speed from it. Search the
540 * configuration table for the best speed we can do that doesn't exceed
541 * the requested speed.
543 if (sc->sc_iicbus == NULL)
546 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
548 if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq)
554 * 23.1.4.3 - HS I2C Software Reset
555 * From OMAP4 TRM at page 4068.
557 * 1. Ensure that the module is disabled.
560 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
562 /* 2. Issue a softreset to the controller. */
563 bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST);
566 * 3. Enable the module.
567 * The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module
568 * is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1.
570 ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN);
572 /* 4. Wait for the software reset to complete. */
574 while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) {
581 * Disable the I2C controller once again, now that the reset has
584 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
587 * The following sequence is taken from the OMAP4 TRM at page 4077.
589 * 1. Enable the functional and interface clocks (see Section
590 * 23.1.5.1.1.1.1). Done at ti_i2c_activate().
592 * 2. Program the prescaler to obtain an approximately 12MHz internal
593 * sampling clock (I2Ci_INTERNAL_CLK) by programming the
594 * corresponding value in the I2Ci.I2C_PSC[3:0] PSC field.
595 * This value depends on the frequency of the functional clock
596 * (I2Ci_FCLK). Because this frequency is 96MHz, the
597 * I2Ci.I2C_PSC[7:0] PSC field value is 0x7.
599 ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc);
602 * 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH
603 * bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps.
604 * These values depend on the internal sampling clock frequency
607 scll = clkcfg->scll & I2C_SCLL_MASK;
608 sclh = clkcfg->sclh & I2C_SCLH_MASK;
611 * 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and
612 * I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of
613 * 400K bps or 3.4M bps (for the second phase of HS mode). These
614 * values depend on the internal sampling clock frequency (see
617 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line
618 * capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional
619 * Multiplexing and Configuration).
624 if ((clkcfg->hsscll + clkcfg->hssclh) > 0) {
625 scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT;
626 sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT;
627 sc->sc_con_reg |= I2C_CON_OPMODE_HS;
633 /* Write the selected bit rate. */
634 ti_i2c_write_2(sc, I2C_REG_SCLL, scll);
635 ti_i2c_write_2(sc, I2C_REG_SCLH, sclh);
638 * 6. Configure the Own Address of the I2C controller by storing it in
639 * the I2Ci.I2C_OA0 register. Up to four Own Addresses can be
640 * programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3)
641 * for each I2C controller.
643 * Note: For a 10-bit address, set the corresponding expand Own Address
644 * bit in the I2Ci.I2C_CON register.
646 * Driver currently always in single master mode so ignore this step.
650 * 7. Set the TX threshold (in transmitter mode) and the RX threshold
651 * (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to
652 * (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX
653 * threshold - 1), where the TX and RX thresholds are greater than
656 * The threshold is set to 5 for now.
658 fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK;
659 reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT);
660 ti_i2c_write_2(sc, I2C_REG_BUF, reg);
663 * 8. Take the I2C controller out of reset by setting the
664 * I2Ci.I2C_CON[15] I2C_EN bit to 1.
666 * 23.1.5.1.1.1.2 - Initialize the I2C Controller
668 * To initialize the I2C controller, perform the following steps:
670 * 1. Configure the I2Ci.I2C_CON register:
671 * . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit
672 * (0: slave, 1: master).
673 * . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX
674 * bit (0: receiver, 1: transmitter).
677 /* Enable the I2C controller in master mode. */
678 sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST;
679 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
682 * 2. If using an interrupt to transmit/receive data, set the
683 * corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4]
684 * XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY
685 * bit for the receive interrupt).
688 /* Set the interrupts we want to be notified. */
689 reg = I2C_IE_XDR | /* Transmit draining interrupt. */
690 I2C_IE_XRDY | /* Transmit Data Ready interrupt. */
691 I2C_IE_RDR | /* Receive draining interrupt. */
692 I2C_IE_RRDY | /* Receive Data Ready interrupt. */
693 I2C_IE_ARDY | /* Register Access Ready interrupt. */
694 I2C_IE_NACK | /* No Acknowledgment interrupt. */
695 I2C_IE_AL; /* Arbitration lost interrupt. */
697 /* Enable the interrupts. */
698 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg);
701 * 3. If using DMA to receive/transmit data, set to 1 the corresponding
702 * bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN
703 * bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit
704 * for the transmit DMA channel).
706 * Not using DMA for now, so ignore this.
713 ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
715 struct ti_i2c_softc *sc;
718 sc = device_get_softc(dev);
720 err = ti_i2c_reset(sc, speed);
725 return (IIC_ENOADDR);
729 ti_i2c_activate(device_t dev)
733 struct ti_i2c_softc *sc;
735 sc = (struct ti_i2c_softc*)device_get_softc(dev);
738 * 1. Enable the functional and interface clocks (see Section
741 clk = I2C0_CLK + sc->device_id;
742 err = ti_prcm_clk_enable(clk);
746 return (ti_i2c_reset(sc, IIC_UNKNOWN));
750 * ti_i2c_deactivate - deactivates the controller and releases resources
751 * @dev: i2c device handle
756 * Assumed called in an atomic context.
762 ti_i2c_deactivate(device_t dev)
764 struct ti_i2c_softc *sc = device_get_softc(dev);
767 /* Disable the controller - cancel all transactions. */
768 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff);
769 ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff);
770 ti_i2c_write_2(sc, I2C_REG_CON, 0);
772 /* Release the interrupt handler. */
773 if (sc->sc_irq_h != NULL) {
774 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
778 bus_generic_detach(sc->sc_dev);
780 /* Unmap the I2C controller registers. */
781 if (sc->sc_mem_res != NULL) {
782 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
783 sc->sc_mem_res = NULL;
786 /* Release the IRQ resource. */
787 if (sc->sc_irq_res != NULL) {
788 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
789 sc->sc_irq_res = NULL;
792 /* Finally disable the functional and interface clocks. */
793 clk = I2C0_CLK + sc->device_id;
794 ti_prcm_clk_disable(clk);
798 ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS)
801 int clk, psc, sclh, scll;
802 struct ti_i2c_softc *sc;
804 dev = (device_t)arg1;
805 sc = device_get_softc(dev);
808 /* Get the system prescaler value. */
809 psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1;
811 /* Get the bitrate. */
812 scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK;
813 sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK;
815 clk = I2C_CLK / psc / (scll + 7 + sclh + 5);
818 return (sysctl_handle_int(oidp, &clk, 0, req));
822 ti_i2c_probe(device_t dev)
825 if (!ofw_bus_status_okay(dev))
827 if (!ofw_bus_is_compatible(dev, "ti,i2c"))
829 device_set_desc(dev, "TI I2C Controller");
835 ti_i2c_attach(device_t dev)
839 struct ti_i2c_softc *sc;
840 struct sysctl_ctx_list *ctx;
841 struct sysctl_oid_list *tree;
844 sc = device_get_softc(dev);
847 /* Get the i2c device id from FDT. */
848 node = ofw_bus_get_node(dev);
849 if ((OF_getencprop(node, "i2c-device-id", &sc->device_id,
850 sizeof(sc->device_id))) <= 0) {
851 device_printf(dev, "missing i2c-device-id attribute in FDT\n");
855 /* Get the memory resource for the register mapping. */
857 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
859 if (sc->sc_mem_res == NULL) {
860 device_printf(dev, "Cannot map registers.\n");
864 /* Allocate our IRQ resource. */
866 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
867 RF_ACTIVE | RF_SHAREABLE);
868 if (sc->sc_irq_res == NULL) {
869 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
870 device_printf(dev, "Cannot allocate interrupt.\n");
874 TI_I2C_LOCK_INIT(sc);
876 /* First of all, we _must_ activate the H/W. */
877 err = ti_i2c_activate(dev);
879 device_printf(dev, "ti_i2c_activate failed\n");
883 /* Read the version number of the I2C module */
884 sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff;
886 /* Get the fifo size. */
887 fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT);
888 fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT;
889 fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK;
891 device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n",
892 sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz);
894 /* Set the FIFO threshold to 5 for now. */
895 sc->sc_fifo_trsh = 5;
897 ctx = device_get_sysctl_ctx(dev);
898 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
899 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock",
900 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, dev, 0,
901 ti_i2c_sysctl_clk, "IU", "I2C bus clock");
903 /* Activate the interrupt. */
904 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
905 NULL, ti_i2c_intr, sc, &sc->sc_irq_h);
909 /* Attach the iicbus. */
910 if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
911 device_printf(dev, "could not allocate iicbus instance\n");
916 /* Probe and attach the iicbus */
917 bus_generic_attach(dev);
921 ti_i2c_deactivate(dev);
922 TI_I2C_LOCK_DESTROY(sc);
929 ti_i2c_detach(device_t dev)
931 struct ti_i2c_softc *sc;
934 sc = device_get_softc(dev);
935 ti_i2c_deactivate(dev);
936 TI_I2C_LOCK_DESTROY(sc);
938 (rv = device_delete_child(dev, sc->sc_iicbus)) != 0)
945 ti_i2c_get_node(device_t bus, device_t dev)
948 /* Share controller node with iibus device. */
949 return (ofw_bus_get_node(bus));
952 static device_method_t ti_i2c_methods[] = {
953 /* Device interface */
954 DEVMETHOD(device_probe, ti_i2c_probe),
955 DEVMETHOD(device_attach, ti_i2c_attach),
956 DEVMETHOD(device_detach, ti_i2c_detach),
959 DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node),
961 /* iicbus interface */
962 DEVMETHOD(iicbus_callback, ti_i2c_callback),
963 DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset),
964 DEVMETHOD(iicbus_transfer, ti_i2c_transfer),
969 static driver_t ti_i2c_driver = {
972 sizeof(struct ti_i2c_softc),
975 static devclass_t ti_i2c_devclass;
977 DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, ti_i2c_devclass, 0, 0);
978 DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, iicbus_devclass, 0, 0);
980 MODULE_DEPEND(ti_iic, ti_prcm, 1, 1, 1);
981 MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1);