2 * Copyright (c) 2013 Thomas Skibo. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
27 #include <sys/param.h>
28 #include <sys/systm.h>
31 #include <sys/mutex.h>
34 #include <machine/smp.h>
35 #include <machine/fdt.h>
36 #include <machine/intr.h>
38 #include <arm/xilinx/zy7_reg.h>
40 #define ZYNQ7_CPU1_ENTRY 0xfffffff0
42 #define SCU_CONTROL_REG 0xf8f00000
43 #define SCU_CONTROL_ENABLE (1 << 0)
46 platform_mp_init_secondary(void)
53 platform_mp_setmaxid(void)
60 platform_mp_probe(void)
68 platform_mp_start_ap(void)
70 bus_space_handle_t scu_handle;
71 bus_space_handle_t ocm_handle;
74 /* Map in SCU control register. */
75 if (bus_space_map(fdtbus_bs_tag, SCU_CONTROL_REG, 4,
77 panic("platform_mp_start_ap: Couldn't map SCU config reg\n");
79 /* Set SCU enable bit. */
80 scu_ctrl = bus_space_read_4(fdtbus_bs_tag, scu_handle, 0);
81 scu_ctrl |= SCU_CONTROL_ENABLE;
82 bus_space_write_4(fdtbus_bs_tag, scu_handle, 0, scu_ctrl);
84 bus_space_unmap(fdtbus_bs_tag, scu_handle, 4);
86 /* Map in magic location to give entry address to CPU1. */
87 if (bus_space_map(fdtbus_bs_tag, ZYNQ7_CPU1_ENTRY, 4,
89 panic("platform_mp_start_ap: Couldn't map OCM\n");
91 /* Write start address for CPU1. */
92 bus_space_write_4(fdtbus_bs_tag, ocm_handle, 0,
93 pmap_kextract((vm_offset_t)mpentry));
95 bus_space_unmap(fdtbus_bs_tag, ocm_handle, 4);
98 * The SCU is enabled above but I think the second CPU doesn't
99 * turn on filtering until after the wake-up below. I think that's why
100 * things don't work if I don't put these cache ops here. Also, the
101 * magic location, 0xfffffff0, isn't in the SCU's filtering range so it
102 * needs a write-back too.
104 cpu_idcache_wbinv_all();
105 cpu_l2cache_wbinv_all();
112 platform_ipi_send(cpuset_t cpus, u_int ipi)
115 pic_ipi_send(cpus, ipi);