1 /* $NetBSD: i80321_timer.c,v 1.7 2003/07/27 04:52:28 thorpej Exp $ */
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Timer/clock support for the Intel i80321 I/O processor.
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
51 #include <sys/resource.h>
53 #include <sys/timetc.h>
55 #include <machine/armreg.h>
56 #include <machine/bus.h>
57 #include <machine/cpu.h>
58 #include <machine/cpufunc.h>
59 #include <machine/frame.h>
60 #include <machine/resource.h>
61 #include <machine/intr.h>
62 #include <arm/xscale/i80321/i80321reg.h>
63 #include <arm/xscale/i80321/i80321var.h>
65 #ifdef CPU_XSCALE_81342
66 #define ICU_INT_TIMER0 (8) /* XXX: Can't include i81342reg.h because
67 definitions overrides the ones from i80321reg.h
70 #include "opt_timer.h"
72 void (*i80321_hardclock_hook)(void) = NULL;
73 struct i80321_timer_softc {
78 static unsigned i80321_timer_get_timecount(struct timecounter *tc);
81 static uint32_t counts_per_hz;
83 #if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342)
84 static uint32_t offset;
85 static uint32_t last = -1;
88 static int ticked = 0;
90 #ifndef COUNTS_PER_SEC
91 #define COUNTS_PER_SEC 200000000 /* 200MHz */
94 #define COUNTS_PER_USEC (COUNTS_PER_SEC / 1000000)
96 static struct timecounter i80321_timer_timecounter = {
97 i80321_timer_get_timecount, /* get_timecount */
98 NULL, /* no poll_pps */
99 ~0u, /* counter_mask */
100 #if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342)
103 COUNTS_PER_SEC * 3, /* frequency */
105 "i80321 timer", /* name */
110 i80321_timer_probe(device_t dev)
113 device_set_desc(dev, "i80321 timer");
118 i80321_timer_attach(device_t dev)
120 timer_softc.dev = dev;
125 static device_method_t i80321_timer_methods[] = {
126 DEVMETHOD(device_probe, i80321_timer_probe),
127 DEVMETHOD(device_attach, i80321_timer_attach),
131 static driver_t i80321_timer_driver = {
133 i80321_timer_methods,
134 sizeof(struct i80321_timer_softc),
136 static devclass_t i80321_timer_devclass;
138 DRIVER_MODULE(itimer, iq, i80321_timer_driver, i80321_timer_devclass, 0, 0);
140 int clockhandler(void *);
143 static __inline uint32_t
148 #ifdef CPU_XSCALE_81342
149 __asm __volatile("mrc p6, 0, %0, c1, c9, 0"
151 __asm __volatile("mrc p6, 0, %0, c1, c1, 0"
158 tmr1_write(uint32_t val)
162 #ifdef CPU_XSCALE_81342
163 __asm __volatile("mcr p6, 0, %0, c1, c9, 0"
165 __asm __volatile("mcr p6, 0, %0, c1, c1, 0"
171 static __inline uint32_t
176 #ifdef CPU_XSCALE_81342
177 __asm __volatile("mrc p6, 0, %0, c3, c9, 0"
179 __asm __volatile("mrc p6, 0, %0, c3, c1, 0"
185 tcr1_write(uint32_t val)
188 #ifdef CPU_XSCALE_81342
189 __asm __volatile("mcr p6, 0, %0, c3, c9, 0"
191 __asm __volatile("mcr p6, 0, %0, c3, c1, 0"
198 trr1_write(uint32_t val)
201 #ifdef CPU_XSCALE_81342
202 __asm __volatile("mcr p6, 0, %0, c5, c9, 0"
204 __asm __volatile("mcr p6, 0, %0, c5, c1, 0"
210 static __inline uint32_t
215 #ifdef CPU_XSCALE_81342
216 __asm __volatile("mrc p6, 0, %0, c0, c9, 0"
218 __asm __volatile("mrc p6, 0, %0, c0, c1, 0"
225 tmr0_write(uint32_t val)
228 #ifdef CPU_XSCALE_81342
229 __asm __volatile("mcr p6, 0, %0, c0, c9, 0"
231 __asm __volatile("mcr p6, 0, %0, c0, c1, 0"
237 static __inline uint32_t
242 #ifdef CPU_XSCALE_81342
243 __asm __volatile("mrc p6, 0, %0, c2, c9, 0"
245 __asm __volatile("mrc p6, 0, %0, c2, c1, 0"
251 tcr0_write(uint32_t val)
254 #ifdef CPU_XSCALE_81342
255 __asm __volatile("mcr p6, 0, %0, c2, c9, 0"
257 __asm __volatile("mcr p6, 0, %0, c2, c1, 0"
264 trr0_write(uint32_t val)
267 #ifdef CPU_XSCALE_81342
268 __asm __volatile("mcr p6, 0, %0, c4, c9, 0"
270 __asm __volatile("mcr p6, 0, %0, c4, c1, 0"
277 tisr_write(uint32_t val)
280 #ifdef CPU_XSCALE_81342
281 __asm __volatile("mcr p6, 0, %0, c6, c9, 0"
283 __asm __volatile("mcr p6, 0, %0, c6, c1, 0"
289 static __inline uint32_t
294 #ifdef CPU_XSCALE_81342
295 __asm __volatile("mrc p6, 0, %0, c6, c9, 0" : "=r" (ret));
297 __asm __volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (ret));
303 i80321_timer_get_timecount(struct timecounter *tc)
305 #if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342)
306 uint32_t cur = tcr0_read();
308 if (cur > last && last != -1) {
309 offset += counts_per_hz;
314 offset += ticked * counts_per_hz;
317 return (counts_per_hz - cur + offset);
321 __asm __volatile("mrc p14, 0, %0, c1, c0, 0\n"
328 * i80321_calibrate_delay:
330 * Calibrate the delay loop.
333 i80321_calibrate_delay(void)
337 * Just use hz=100 for now -- we'll adjust it, if necessary,
338 * in cpu_initclocks().
340 counts_per_hz = COUNTS_PER_SEC / 100;
342 tmr0_write(0); /* stop timer */
343 tisr_write(TISR_TMR0); /* clear interrupt */
344 trr0_write(counts_per_hz); /* reload value */
345 tcr0_write(counts_per_hz); /* current value */
347 tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE);
353 * Initialize the clock and get them going.
359 struct resource *irq;
362 device_t dev = timer_softc.dev;
364 if (hz < 50 || COUNTS_PER_SEC % hz) {
365 printf("Cannot get %d Hz clock; using 100 Hz\n", hz);
368 tick = 1000000 / hz; /* number of microseconds between interrupts */
371 * We only have one timer available; stathz and profhz are
372 * always left as 0 (the upper-layer clock code deals with
376 printf("Cannot get %d Hz statclock\n", stathz);
380 printf("Cannot get %d Hz profclock\n", profhz);
383 /* Report the clock frequency. */
385 oldirqstate = disable_interrupts(PSR_I);
387 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
388 #ifdef CPU_XSCALE_81342
389 ICU_INT_TIMER0, ICU_INT_TIMER0,
391 ICU_INT_TMR0, ICU_INT_TMR0,
395 panic("Unable to setup the clock irq handler.\n");
397 bus_setup_intr(dev, irq, INTR_TYPE_CLK, clockhandler, NULL,
399 tmr0_write(0); /* stop timer */
400 tisr_write(TISR_TMR0); /* clear interrupt */
402 counts_per_hz = COUNTS_PER_SEC / hz;
404 trr0_write(counts_per_hz); /* reload value */
405 tcr0_write(counts_per_hz); /* current value */
406 tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE);
408 tc_init(&i80321_timer_timecounter);
409 restore_interrupts(oldirqstate);
411 #if !defined(XSCALE_DISABLE_CCNT) && !defined(CPU_XSCALE_81342)
412 /* Enable the clock count register. */
413 __asm __volatile("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (rid));
416 __asm __volatile("mcr p14, 0, %0, c0, c0, 0\n"
425 * Delay for at least N microseconds.
430 uint32_t cur, last, delta, usecs;
433 * This works by polling the timer and counting the
434 * number of microseconds that go by.
442 /* Check to see if the timer has wrapped around. */
444 delta += (last + (counts_per_hz - cur));
446 delta += (last - cur);
450 if (delta >= COUNTS_PER_USEC) {
451 usecs += delta / COUNTS_PER_USEC;
452 delta %= COUNTS_PER_USEC;
460 * Handle the hardclock interrupt.
463 clockhandler(void *arg)
465 struct trapframe *frame = arg;
468 tisr_write(TISR_TMR0);
469 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
471 if (i80321_hardclock_hook != NULL)
472 (*i80321_hardclock_hook)();
473 return (FILTER_HANDLED);
477 cpu_startprofclock(void)
482 cpu_stopprofclock(void)