1 /* $NetBSD: pxa2x0reg.h,v 1.9 2006/04/10 04:13:58 simonb Exp $ */
4 * Copyright (c) 2002 Genetec Corporation. All rights reserved.
5 * Written by Hiroyuki Bessho for Genetec Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed for the NetBSD Project by
18 * Genetec Corporation.
19 * 4. The name of Genetec Corporation may not be used to endorse or
20 * promote products derived from this software without specific prior
23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
40 * Intel PXA2[15]0 processor is XScale based integrated CPU
43 * Intel(r) PXA250 and PXA210 Application Processors
47 #ifndef _ARM_XSCALE_PXAREG_H_
48 #define _ARM_XSCALE_PXAREG_H_
51 #include <sys/types.h> /* for uint32_t */
57 #define PXA2X0_CS0_START 0x00000000
58 #define PXA2X0_CS1_START 0x04000000
59 #define PXA2X0_CS2_START 0x08000000
60 #define PXA2X0_CS3_START 0x0c000000
61 #define PXA2X0_CS4_START 0x10000000
62 #define PXA2X0_CS5_START 0x14000000
63 #define PXA2X0_CS_SIZE 0x04000000
65 #define PXA2X0_PCMCIA_SLOT0 0x20000000
66 #define PXA2X0_PCMCIA_SLOT1 0x30000000
68 #define PXA2X0_PERIPH_START 0x40000000
69 /* #define PXA2X0_MEMCTL_START 0x48000000 */
70 #define PXA270_PERIPH_END 0x530fffff
71 #define PXA250_PERIPH_END 0x480fffff
72 #define PXA2X0_PERIPH_OFFSET 0xa8000000
74 #define PXA2X0_SDRAM0_START 0xa0000000
75 #define PXA2X0_SDRAM1_START 0xa4000000
76 #define PXA2X0_SDRAM2_START 0xa8000000
77 #define PXA2X0_SDRAM3_START 0xac000000
78 #define PXA2X0_SDRAM_BANKS 4
79 #define PXA2X0_SDRAM_BANK_SIZE 0x04000000
82 * Physical address of integrated peripherals
85 #define PXA2X0_DMAC_BASE 0x40000000
86 #define PXA2X0_DMAC_SIZE 0x300
87 #define PXA2X0_FFUART_BASE 0x40100000 /* Full Function UART */
88 #define PXA2X0_FFUART_SIZE 0x20
89 #define PXA2X0_BTUART_BASE 0x40200000 /* Bluetooth UART */
90 #define PXA2X0_BTUART_SIZE 0x24
91 #define PXA2X0_I2C_BASE 0x40300000
92 #define PXA2X0_I2C_SIZE 0x000016a4
93 #define PXA2X0_I2S_BASE 0x40400000
94 #define PXA2X0_AC97_BASE 0x40500000
95 #define PXA2X0_AC97_SIZE 0x600
96 #define PXA2X0_USBDC_BASE 0x40600000 /* USB Client */
97 #define PXA2X0_USBDC_SIZE 0x0e04
98 #define PXA2X0_STUART_BASE 0x40700000 /* Standard UART */
99 #define PXA2X0_STUART_SIZE 0x24
100 #define PXA2X0_ICP_BASE 0x40800000
101 #define PXA2X0_RTC_BASE 0x40900000
102 #define PXA2X0_RTC_SIZE 0x10
103 #define PXA2X0_OST_BASE 0x40a00000 /* OS Timer */
104 #define PXA2X0_OST_SIZE 0x20
105 #define PXA2X0_PWM0_BASE 0x40b00000
106 #define PXA2X0_PWM1_BASE 0x40c00000
107 #define PXA2X0_INTCTL_BASE 0x40d00000 /* Interrupt controller */
108 #define PXA2X0_INTCTL_SIZE 0x20
109 #define PXA2X0_GPIO_BASE 0x40e00000
111 #define PXA270_GPIO_SIZE 0x150
112 #define PXA250_GPIO_SIZE 0x70
113 #define PXA2X0_POWMAN_BASE 0x40f00000 /* Power management */
114 #define PXA2X0_SSP_BASE 0x41000000
115 #define PXA2X0_MMC_BASE 0x41100000 /* MultiMediaCard */
116 #define PXA2X0_MMC_SIZE 0x48
117 #define PXA2X0_CLKMAN_BASE 0x41300000 /* Clock Manager */
118 #define PXA2X0_CLKMAN_SIZE 12
119 #define PXA2X0_HWUART_BASE 0x41600000 /* Hardware UART */
120 #define PXA2X0_HWUART_SIZE 0x30
121 #define PXA2X0_LCDC_BASE 0x44000000 /* LCD Controller */
122 #define PXA2X0_LCDC_SIZE 0x220
123 #define PXA2X0_MEMCTL_BASE 0x48000000 /* Memory Controller */
124 #define PXA2X0_MEMCTL_SIZE 0x48
125 #define PXA2X0_USBH_BASE 0x4c000000 /* USB Host controller */
126 #define PXA2X0_USBH_SIZE 0x70
128 /* Internal SRAM storage. PXA27x only */
129 #define PXA270_SRAM0_START 0x5c000000
130 #define PXA270_SRAM1_START 0x5c010000
131 #define PXA270_SRAM2_START 0x5c020000
132 #define PXA270_SRAM3_START 0x5c030000
133 #define PXA270_SRAM_BANKS 4
134 #define PXA270_SRAM_BANK_SIZE 0x00010000
136 /* width of interrupt controller */
137 #define ICU_LEN 32 /* but [0..7,15,16] is not used */
138 #define ICU_INT_HWMASK 0xffffff00
139 #define PXA250_IRQ_MIN 8 /* 0..7 are not used by integrated
141 #define PXA270_IRQ_MIN 0
143 #define PXA2X0_INT_USBH1 3 /* USB host (OHCI) */
145 #define PXA2X0_INT_HWUART 7
146 #define PXA2X0_INT_GPIO0 8
147 #define PXA2X0_INT_GPIO1 9
148 #define PXA2X0_INT_GPION 10 /* irq from GPIO[2..80] */
149 #define PXA2X0_INT_USB 11
150 #define PXA2X0_INT_PMU 12
151 #define PXA2X0_INT_I2S 13
152 #define PXA2X0_INT_AC97 14
153 #define PXA2X0_INT_LCD 17
154 #define PXA2X0_INT_I2C 18
155 #define PXA2X0_INT_ICP 19
156 #define PXA2X0_INT_STUART 20
157 #define PXA2X0_INT_BTUART 21
158 #define PXA2X0_INT_FFUART 22
159 #define PXA2X0_INT_MMC 23
160 #define PXA2X0_INT_SSP 24
161 #define PXA2X0_INT_DMA 25
162 #define PXA2X0_INT_OST0 26
163 #define PXA2X0_INT_OST1 27
164 #define PXA2X0_INT_OST2 28
165 #define PXA2X0_INT_OST3 29
166 #define PXA2X0_INT_RTCHZ 30
167 #define PXA2X0_INT_ALARM 31 /* RTC Alarm interrupt */
170 #define DMAC_N_CHANNELS 16
171 #define DMAC_N_PRIORITIES 3
173 #define DMAC_DCSR(n) ((n)*4)
174 #define DCSR_BUSERRINTR (1<<0) /* bus error interrupt */
175 #define DCSR_STARTINTR (1<<1) /* start interrupt */
176 #define DCSR_ENDINTR (1<<2) /* end interrupt */
177 #define DCSR_STOPSTATE (1<<3) /* channel is not running */
178 #define DCSR_REQPEND (1<<8) /* request pending */
179 #define DCSR_STOPIRQEN (1<<29) /* stop interrupt enable */
180 #define DCSR_NODESCFETCH (1<<30) /* no-descriptor fetch mode */
181 #define DCSR_RUN (1<<31)
182 #define DMAC_DINT 0x00f0 /* DAM interrupt */
183 #define DMAC_DINT_MASK 0xffffu
184 #define DMAC_DRCMR(n) (0x100+(n)*4) /* Channel map register */
185 #define DRCMR_CHLNUM 0x0f /* channel number */
186 #define DRCMR_MAPVLD (1<<7) /* map valid */
187 #define DMAC_DDADR(n) (0x0200+(n)*16)
188 #define DDADR_STOP (1<<0)
189 #define DMAC_DSADR(n) (0x0204+(n)*16)
190 #define DMAC_DTADR(n) (0x0208+(n)*16)
191 #define DMAC_DCMD(n) (0x020c+(n)*16)
192 #define DCMD_LENGTH_MASK 0x1fff
193 #define DCMD_WIDTH_SHIFT 14
194 #define DCMD_WIDTH_0 (0<<DCMD_WIDTH_SHIFT) /* for mem-to-mem transfer*/
195 #define DCMD_WIDTH_1 (1<<DCMD_WIDTH_SHIFT)
196 #define DCMD_WIDTH_2 (2<<DCMD_WIDTH_SHIFT)
197 #define DCMD_WIDTH_4 (3<<DCMD_WIDTH_SHIFT)
198 #define DCMD_SIZE_SHIFT 16
199 #define DCMD_SIZE_8 (1<<DCMD_SIZE_SHIFT)
200 #define DCMD_SIZE_16 (2<<DCMD_SIZE_SHIFT)
201 #define DCMD_SIZE_32 (3<<DCMD_SIZE_SHIFT)
202 #define DCMD_LITTLE_ENDIEN (0<<18)
203 #define DCMD_ENDIRQEN (1<<21)
204 #define DCMD_STARTIRQEN (1<<22)
205 #define DCMD_FLOWTRG (1<<28) /* flow control by target */
206 #define DCMD_FLOWSRC (1<<29) /* flow control by source */
207 #define DCMD_INCTRGADDR (1<<30) /* increment target address */
208 #define DCMD_INCSRCADDR (1<<31) /* increment source address */
210 #ifndef __ASSEMBLER__
212 struct pxa_dma_desc {
213 volatile uint32_t dd_ddadr;
214 #define DMAC_DESC_LAST 0x1
215 volatile uint32_t dd_dsadr;
216 volatile uint32_t dd_dtadr;
217 volatile uint32_t dd_dcmd; /* command and length */
222 #define PXA2X0_COM_FREQ 14745600L
225 #define I2C_IBMR 0x1680 /* Bus monitor register */
226 #define I2C_IDBR 0x1688 /* Data buffer */
227 #define I2C_ICR 0x1690 /* Control register */
228 #define ICR_START (1<<0)
229 #define ICR_STOP (1<<1)
230 #define ICR_ACKNAK (1<<2)
231 #define ICR_TB (1<<3)
232 #define ICR_MA (1<<4)
233 #define I2C_ISR 0x1698 /* Status register */
234 #define I2C_ISAR 0x16a0 /* Slave address */
237 #define CLKMAN_CCCR 0x00 /* Core Clock Configuration */
238 #define CCCR_TURBO_X1 (2<<7)
239 #define CCCR_TURBO_X15 (3<<7) /* x 1.5 */
240 #define CCCR_TURBO_X2 (4<<7)
241 #define CCCR_TURBO_X25 (5<<7) /* x 2.5 */
242 #define CCCR_TURBO_X3 (6<<7) /* x 3.0 */
243 #define CCCR_RUN_X1 (1<<5)
244 #define CCCR_RUN_X2 (2<<5)
245 #define CCCR_RUN_X4 (3<<5)
246 #define CCCR_MEM_X27 (1<<0) /* x27, 99.53MHz */
247 #define CCCR_MEM_X32 (2<<0) /* x32, 117,96MHz */
248 #define CCCR_MEM_X36 (3<<0) /* x26, 132.71MHz */
249 #define CCCR_MEM_X40 (4<<0) /* x27, 99.53MHz */
250 #define CCCR_MEM_X45 (5<<0) /* x27, 99.53MHz */
251 #define CCCR_MEM_X9 (0x1f<<0) /* x9, 33.2MHz */
253 #define CLKMAN_CKEN 0x04 /* Clock Enable Register */
254 #define CLKMAN_OSCC 0x08 /* Osillcator Configuration Register */
256 #define CCCR_N_SHIFT 7
257 #define CCCR_N_MASK (0x07<<CCCR_N_SHIFT)
258 #define CCCR_M_SHIFT 5
259 #define CCCR_M_MASK (0x03<<CCCR_M_SHIFT)
260 #define CCCR_L_MASK 0x1f
262 #define CKEN_PWM0 (1<<0)
263 #define CKEN_PWM1 (1<<1)
264 #define CKEN_AC97 (1<<2)
265 #define CKEN_SSP (1<<3)
266 #define CKEN_STUART (1<<5)
267 #define CKEN_FFUART (1<<6)
268 #define CKEN_BTUART (1<<7)
269 #define CKEN_I2S (1<<8)
270 #define CKEN_USBH (1<<10)
271 #define CKEN_USB (1<<11)
272 #define CKEN_MMC (1<<12)
273 #define CKEN_FICP (1<<13)
274 #define CKEN_I2C (1<<14)
275 #define CKEN_LCD (1<<16)
277 #define OSCC_OOK (1<<0) /* 32.768 kHz oscillator status */
278 #define OSCC_OON (1<<1) /* 32.768 kHz oscillator */
283 #define RTC_RCNR 0x0000 /* count register */
284 #define RTC_RTAR 0x0004 /* alarm register */
285 #define RTC_RTSR 0x0008 /* status register */
286 #define RTC_RTTR 0x000c /* trim register */
290 #define GPIO_GPLR0 0x00 /* Level reg [31:0] */
291 #define GPIO_GPLR1 0x04 /* Level reg [63:32] */
292 #define GPIO_GPLR2 0x08 /* Level reg [80:64] */
294 #define GPIO_GPDR0 0x0c /* dir reg [31:0] */
295 #define GPIO_GPDR1 0x10 /* dir reg [63:32] */
296 #define GPIO_GPDR2 0x14 /* dir reg [80:64] */
298 #define GPIO_GPSR0 0x18 /* set reg [31:0] */
299 #define GPIO_GPSR1 0x1c /* set reg [63:32] */
300 #define GPIO_GPSR2 0x20 /* set reg [80:64] */
302 #define GPIO_GPCR0 0x24 /* clear reg [31:0] */
303 #define GPIO_GPCR1 0x28 /* clear reg [63:32] */
304 #define GPIO_GPCR2 0x2c /* clear reg [80:64] */
306 #define GPIO_GPER0 0x30 /* rising edge [31:0] */
307 #define GPIO_GPER1 0x34 /* rising edge [63:32] */
308 #define GPIO_GPER2 0x38 /* rising edge [80:64] */
310 #define GPIO_GRER0 0x30 /* rising edge [31:0] */
311 #define GPIO_GRER1 0x34 /* rising edge [63:32] */
312 #define GPIO_GRER2 0x38 /* rising edge [80:64] */
314 #define GPIO_GFER0 0x3c /* falling edge [31:0] */
315 #define GPIO_GFER1 0x40 /* falling edge [63:32] */
316 #define GPIO_GFER2 0x44 /* falling edge [80:64] */
318 #define GPIO_GEDR0 0x48 /* edge detect [31:0] */
319 #define GPIO_GEDR1 0x4c /* edge detect [63:32] */
320 #define GPIO_GEDR2 0x50 /* edge detect [80:64] */
322 #define GPIO_GAFR0_L 0x54 /* alternate function [15:0] */
323 #define GPIO_GAFR0_U 0x58 /* alternate function [31:16] */
324 #define GPIO_GAFR1_L 0x5c /* alternate function [47:32] */
325 #define GPIO_GAFR1_U 0x60 /* alternate function [63:48] */
326 #define GPIO_GAFR2_L 0x64 /* alternate function [79:64] */
327 #define GPIO_GAFR2_U 0x68 /* alternate function [80] */
329 /* Only for PXA270 */
330 #define GPIO_GAFR3_L 0x6c /* alternate function [111:96] */
331 #define GPIO_GAFR3_U 0x70 /* alternate function [120:112] */
333 #define GPIO_GPLR3 0x100 /* Level reg [120:96] */
334 #define GPIO_GPDR3 0x10c /* dir reg [120:96] */
335 #define GPIO_GPSR3 0x118 /* set reg [120:96] */
336 #define GPIO_GPCR3 0x124 /* clear reg [120:96] */
337 #define GPIO_GRER3 0x130 /* rising edge [120:96] */
338 #define GPIO_GFER3 0x13c /* falling edge [120:96] */
339 #define GPIO_GEDR3 0x148 /* edge detect [120:96] */
341 /* a bit simpler if we don't support PXA270 */
342 #define PXA250_GPIO_REG(r, pin) ((r) + (((pin) / 32) * 4))
343 #define PXA250_GPIO_NPINS 85
345 #define PXA270_GPIO_REG(r, pin) \
346 (pin < 96 ? PXA250_GPIO_REG(r,pin) : ((r) + 0x100 + ((((pin)-96) / 32) * 4)))
347 #define PXA270_GPIO_NPINS 121
350 #define GPIO_BANK(pin) ((pin) / 32)
351 #define GPIO_BIT(pin) (1u << ((pin) & 0x1f))
352 #define GPIO_FN_REG(pin) (GPIO_GAFR0_L + (((pin) / 16) * 4))
353 #define GPIO_FN_SHIFT(pin) ((pin & 0xf) * 2)
355 #define GPIO_IN 0x00 /* Regular GPIO input pin */
356 #define GPIO_OUT 0x10 /* Regular GPIO output pin */
357 #define GPIO_ALT_FN_1_IN 0x01 /* Alternate function 1 input */
358 #define GPIO_ALT_FN_1_OUT 0x11 /* Alternate function 1 output */
359 #define GPIO_ALT_FN_2_IN 0x02 /* Alternate function 2 input */
360 #define GPIO_ALT_FN_2_OUT 0x12 /* Alternate function 2 output */
361 #define GPIO_ALT_FN_3_IN 0x03 /* Alternate function 3 input */
362 #define GPIO_ALT_FN_3_OUT 0x13 /* Alternate function 3 output */
363 #define GPIO_SET 0x20 /* Initial state is Set */
364 #define GPIO_CLR 0x00 /* Initial state is Clear */
366 #define GPIO_FN_MASK 0x03
367 #define GPIO_FN_IS_OUT(n) ((n) & GPIO_OUT)
368 #define GPIO_FN_IS_SET(n) ((n) & GPIO_SET)
369 #define GPIO_FN(n) ((n) & GPIO_FN_MASK)
370 #define GPIO_IS_GPIO(n) (GPIO_FN(n) == 0)
371 #define GPIO_IS_GPIO_IN(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_IN)
372 #define GPIO_IS_GPIO_OUT(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_OUT)
375 #define IRQ_NGPIO 128
376 #define IRQ_GPIO_MAX IRQ_GPIO0 + IRQ_NGPIO
377 #define IRQ_TO_GPIO(x) (x - IRQ_GPIO0)
378 #define GPIO_TO_IRQ(x) (x + IRQ_GPIO0)
384 #define MEMCTL_MDCNFG 0x0000
385 #define MDCNFG_DE0 (1<<0)
386 #define MDCNFG_DE1 (1<<1)
387 #define MDCNFD_DWID01_SHIFT 2
388 #define MDCNFD_DCAC01_SHIFT 3
389 #define MDCNFD_DRAC01_SHIFT 5
390 #define MDCNFD_DNB01_SHIFT 7
391 #define MDCNFG_DE2 (1<<16)
392 #define MDCNFG_DE3 (1<<17)
393 #define MDCNFD_DWID23_SHIFT 18
394 #define MDCNFD_DCAC23_SHIFT 19
395 #define MDCNFD_DRAC23_SHIFT 21
396 #define MDCNFD_DNB23_SHIFT 23
398 #define MDCNFD_DWID_MASK 0x1
399 #define MDCNFD_DCAC_MASK 0x3
400 #define MDCNFD_DRAC_MASK 0x3
401 #define MDCNFD_DNB_MASK 0x1
403 #define MEMCTL_MDREFR 0x04 /* refresh control register */
404 #define MDREFR_DRI 0xfff
405 #define MDREFR_E0PIN (1<<12)
406 #define MDREFR_K0RUN (1<<13) /* SDCLK0 enable */
407 #define MDREFR_K0DB2 (1<<14) /* SDCLK0 1/2 freq */
408 #define MDREFR_E1PIN (1<<15)
409 #define MDREFR_K1RUN (1<<16) /* SDCLK1 enable */
410 #define MDREFR_K1DB2 (1<<17) /* SDCLK1 1/2 freq */
411 #define MDREFR_K2RUN (1<<18) /* SDCLK2 enable */
412 #define MDREFR_K2DB2 (1<<19) /* SDCLK2 1/2 freq */
413 #define MDREFR_APD (1<<20) /* Auto Power Down */
414 #define MDREFR_SLFRSH (1<<22) /* Self Refresh */
415 #define MDREFR_K0FREE (1<<23) /* SDCLK0 free run */
416 #define MDREFR_K1FREE (1<<24) /* SDCLK1 free run */
417 #define MDREFR_K2FREE (1<<25) /* SDCLK2 free run */
419 #define MEMCTL_MSC0 0x08 /* Asychronous Statis memory Control CS[01] */
420 #define MEMCTL_MSC1 0x0c /* Asychronous Statis memory Control CS[23] */
421 #define MEMCTL_MSC2 0x10 /* Asychronous Statis memory Control CS[45] */
422 #define MSC_RBUFF_SHIFT 15 /* return data buffer */
423 #define MSC_RBUFF (1<<MSC_RBUFF_SHIFT)
424 #define MSC_RRR_SHIFT 12 /* recovery time */
425 #define MSC_RRR (7<<MSC_RRR_SHIFT)
426 #define MSC_RDN_SHIFT 8 /* ROM delay next access */
427 #define MSC_RDN (0x0f<<MSC_RDN_SHIFT)
428 #define MSC_RDF_SHIFT 4 /* ROM delay first access*/
429 #define MSC_RDF (0x0f<<MSC_RDF_SHIFT)
430 #define MSC_RBW_SHIFT 3 /* 32/16 bit bus */
431 #define MSC_RBW (1<<MSC_RBW_SHIFT)
432 #define MSC_RT_SHIFT 0 /* type */
433 #define MSC_RT (7<<MSC_RT_SHIFT)
434 #define MSC_RT_NONBURST 0
435 #define MSC_RT_SRAM 1
436 #define MSC_RT_BURST4 2
437 #define MSC_RT_BURST8 3
438 #define MSC_RT_VLIO 4
440 /* expansion memory timing configuration */
441 #define MEMCTL_MCMEM(n) (0x28+4*(n))
442 #define MEMCTL_MCATT(n) (0x30+4*(n))
443 #define MEMCTL_MCIO(n) (0x38+4*(n))
445 #define MC_HOLD_SHIFT 14
446 #define MC_ASST_SHIFT 7
447 #define MC_SET_SHIFT 0
448 #define MC_TIMING_VAL(hold,asst,set) (((hold)<<MC_HOLD_SHIFT)| \
449 ((asst)<<MC_ASST_SHIFT)|((set)<<MC_SET_SHIFT))
451 #define MEMCTL_MECR 0x14 /* Expansion memory configuration */
452 #define MECR_NOS (1<<0) /* Number of sockets */
453 #define MECR_CIT (1<<1) /* Card-is-there */
455 #define MEMCTL_MDMRS 0x0040
460 #define LCDC_LCCR0 0x000 /* Controller Control Register 0 */
461 #define LCCR0_ENB (1U<<0) /* LCD Controller Enable */
462 #define LCCR0_CMS (1U<<1) /* Color/Mono select */
463 #define LCCR0_SDS (1U<<2) /* Single/Dual -panel */
464 #define LCCR0_LDM (1U<<3) /* LCD Disable Done Mask */
465 #define LCCR0_SFM (1U<<4) /* Start of Frame Mask */
466 #define LCCR0_IUM (1U<<5) /* Input FIFO Underrun Mask */
467 #define LCCR0_EFM (1U<<6) /* End of Frame Mask */
468 #define LCCR0_PAS (1U<<7) /* Passive/Active Display select */
469 #define LCCR0_DPD (1U<<9) /* Double-Pixel Data pin mode */
470 #define LCCR0_DIS (1U<<10) /* LCD Disable */
471 #define LCCR0_QDM (1U<<11) /* LCD Quick Disable Mask */
472 #define LCCR0_BM (1U<<20) /* Branch Mask */
473 #define LCCR0_OUM (1U<<21) /* Output FIFO Underrun Mask */
475 #define LCCR0_IMASK (LCCR0_LDM|LCCR0_SFM|LCCR0_IUM|LCCR0_EFM|LCCR0_QDM|LCCR0_BM|LCCR0_OUM)
478 #define LCDC_LCCR1 0x004 /* Controller Control Register 1 */
479 #define LCDC_LCCR2 0x008 /* Controller Control Register 2 */
480 #define LCDC_LCCR3 0x00c /* Controller Control Register 2 */
481 #define LCCR3_BPP_SHIFT 24 /* Bits per pixel */
482 #define LCCR3_BPP (0x07<<LCCR3_BPP_SHIFT)
483 #define LCDC_LCCR4 0x010 /* Controller Control Register 4 */
484 #define LCDC_LCCR5 0x014 /* Controller Control Register 5 */
485 #define LCDC_FBR0 0x020 /* DMA ch0 frame branch register */
486 #define LCDC_FBR1 0x024 /* DMA ch1 frame branch register */
487 #define LCDC_FBR2 0x028 /* DMA ch2 frame branch register */
488 #define LCDC_FBR3 0x02c /* DMA ch3 frame branch register */
489 #define LCDC_FBR4 0x030 /* DMA ch4 frame branch register */
490 #define LCDC_LCSR1 0x034 /* controller status register 1 PXA27x only */
491 #define LCDC_LCSR 0x038 /* controller status register */
492 #define LCSR_LDD (1U<<0) /* LCD disable done */
493 #define LCSR_SOF (1U<<1) /* Start of frame */
494 #define LCDC_LIIDR 0x03c /* controller interrupt ID Register */
495 #define LCDC_TRGBR 0x040 /* TMED RGB Speed Register */
496 #define LCDC_TCR 0x044 /* TMED Control Register */
497 #define LCDC_OVL1C1 0x050 /* Overlay 1 control register 1 */
498 #define LCDC_OVL1C2 0x060 /* Overlay 1 control register 2 */
499 #define LCDC_OVL2C1 0x070 /* Overlay 1 control register 1 */
500 #define LCDC_OVL2C2 0x080 /* Overlay 1 control register 2 */
501 #define LCDC_CCR 0x090 /* Cursor control register */
502 #define LCDC_CMDCR 0x100 /* Command control register */
503 #define LCDC_PRSR 0x104 /* Panel read status register */
504 #define LCDC_FBR5 0x110 /* DMA ch5 frame branch register */
505 #define LCDC_FBR6 0x114 /* DMA ch6 frame branch register */
506 #define LCDC_FDADR0 0x200 /* DMA ch0 frame descriptor address */
507 #define LCDC_FSADR0 0x204 /* DMA ch0 frame source address */
508 #define LCDC_FIDR0 0x208 /* DMA ch0 frame ID register */
509 #define LCDC_LDCMD0 0x20c /* DMA ch0 command register */
510 #define LCDC_FDADR1 0x210 /* DMA ch1 frame descriptor address */
511 #define LCDC_FSADR1 0x214 /* DMA ch1 frame source address */
512 #define LCDC_FIDR1 0x218 /* DMA ch1 frame ID register */
513 #define LCDC_LDCMD1 0x21c /* DMA ch1 command register */
514 #define LCDC_FDADR2 0x220 /* DMA ch2 frame descriptor address */
515 #define LCDC_FSADR2 0x224 /* DMA ch2 frame source address */
516 #define LCDC_FIDR2 0x228 /* DMA ch2 frame ID register */
517 #define LCDC_LDCMD2 0x22c /* DMA ch2 command register */
518 #define LCDC_FDADR3 0x230 /* DMA ch3 frame descriptor address */
519 #define LCDC_FSADR3 0x234 /* DMA ch3 frame source address */
520 #define LCDC_FIDR3 0x238 /* DMA ch3 frame ID register */
521 #define LCDC_LDCMD3 0x23c /* DMA ch3 command register */
522 #define LCDC_FDADR4 0x240 /* DMA ch4 frame descriptor address */
523 #define LCDC_FSADR4 0x244 /* DMA ch4 frame source address */
524 #define LCDC_FIDR4 0x248 /* DMA ch4 frame ID register */
525 #define LCDC_LDCMD4 0x24c /* DMA ch4 command register */
526 #define LCDC_FDADR5 0x250 /* DMA ch5 frame descriptor address */
527 #define LCDC_FSADR5 0x254 /* DMA ch5 frame source address */
528 #define LCDC_FIDR5 0x258 /* DMA ch5 frame ID register */
529 #define LCDC_LDCMD5 0x25c /* DMA ch5 command register */
530 #define LCDC_FDADR6 0x260 /* DMA ch6 frame descriptor address */
531 #define LCDC_FSADR6 0x264 /* DMA ch6 frame source address */
532 #define LCDC_FIDR6 0x268 /* DMA ch6 frame ID register */
533 #define LCDC_LDCMD6 0x26c /* DMA ch6 command register */
534 #define LCDC_LCDBSCNTR 0x054 /* LCD buffer strength control register */
539 #define MMC_STRPCL 0x00 /* start/stop MMC clock */
540 #define STRPCL_NOOP 0
541 #define STRPCL_STOP 1 /* stop MMC clock */
542 #define STRPCL_START 2 /* start MMC clock */
543 #define MMC_STAT 0x04 /* status register */
544 #define STAT_READ_TIME_OUT (1<<0)
545 #define STAT_TIMEOUT_RESPONSE (1<<1)
546 #define STAT_CRC_WRITE_ERROR (1<<2)
547 #define STAT_CRC_READ_ERROR (1<<3)
548 #define STAT_SPI_READ_ERROR_TOKEN (1<<4)
549 #define STAT_RES_CRC_ERR (1<<5)
550 #define STAT_XMIT_FIFO_EMPTY (1<<6)
551 #define STAT_RECV_FIFO_FULL (1<<7)
552 #define STAT_CLK_EN (1<<8)
553 #define STAT_DATA_TRAN_DONE (1<<11)
554 #define STAT_PRG_DONE (1<<12)
555 #define STAT_END_CMD_RES (1<<13)
556 #define MMC_CLKRT 0x08 /* MMC clock rate */
561 #define CLKRT_1_25M 4
564 #define MMC_SPI 0x0c /* SPI mode control */
565 #define SPI_EN (1<<0) /* enable SPI mode */
566 #define SPI_CRC_ON (1<<1) /* enable CRC generation */
567 #define SPI_CS_EN (1<<2) /* Enable CS[01] */
568 #define SPI_CS_ADDRESS (1<<3) /* CS0/CS1 */
569 #define MMC_CMDAT 0x10 /* command/response/data */
570 #define CMDAT_RESPONSE_FORMAT 0x03
571 #define CMDAT_RESPONSE_FORMAT_NO 0 /* no response */
572 #define CMDAT_RESPONSE_FORMAT_R1 1 /* R1, R1b, R4, R5 */
573 #define CMDAT_RESPONSE_FORMAT_R2 2
574 #define CMDAT_RESPONSE_FORMAT_R3 3
575 #define CMDAT_DATA_EN (1<<2)
576 #define CMDAT_WRITE (1<<3) /* 1=write 0=read operation */
577 #define CMDAT_STREAM_BLOCK (1<<4) /* stream mode */
578 #define CMDAT_BUSY (1<<5) /* busy signal is expected */
579 #define CMDAT_INIT (1<<6) /* preceede command with 80 clocks */
580 #define CMDAT_MMC_DMA_EN (1<<7) /* DMA enable */
581 #define MMC_RESTO 0x14 /* expected response time out */
582 #define MMC_RDTO 0x18 /* expected data read time out */
583 #define MMC_BLKLEN 0x1c /* block length of data transaction */
584 #define MMC_NOB 0x20 /* number of blocks (block mode) */
585 #define MMC_PRTBUF 0x24 /* partial MMC_TXFIFO written */
586 #define PRTBUF_BUF_PART_FULL (1<<0) /* buffer partially full */
587 #define MMC_I_MASK 0x28 /* interrupt mask */
588 #define MMC_I_REG 0x2c /* interrupt register */
589 #define MMC_I_DATA_TRAN_DONE (1<<0)
590 #define MMC_I_PRG_DONE (1<<1)
591 #define MMC_I_END_CMD_RES (1<<2)
592 #define MMC_I_STOP_CMD (1<<3)
593 #define MMC_I_CLK_IS_OFF (1<<4)
594 #define MMC_I_RXFIFO_RD_REQ (1<<5)
595 #define MMC_I_TXFIFO_WR_REQ (1<<6)
596 #define MMC_CMD 0x30 /* index of current command */
597 #define MMC_ARGH 0x34 /* MSW part of the current command arg */
598 #define MMC_ARGL 0x38 /* LSW part of the current command arg */
599 #define MMC_RES 0x3c /* response FIFO */
600 #define MMC_RXFIFO 0x40 /* receive FIFO */
601 #define MMC_TXFIFO 0x44 /* transmit FIFO */
606 #define AC97_N_CODECS 2
607 #define AC97_GCR 0x000c /* Global control register */
608 #define GCR_GIE (1<<0) /* interrupt enable */
609 #define GCR_COLD_RST (1<<1)
610 #define GCR_WARM_RST (1<<2)
611 #define GCR_ACLINK_OFF (1<<3)
612 #define GCR_PRIRES_IEN (1<<4) /* Primary resume interrupt enable */
613 #define GCR_SECRES_IEN (1<<5) /* Secondary resume interrupt enable */
614 #define GCR_PRIRDY_IEN (1<<8) /* Primary ready interrupt enable */
615 #define GCR_SECRDY_IEN (1<<9) /* Primary ready interrupt enable */
616 #define GCR_SDONE_IE (1<<18) /* Status done interrupt enable */
617 #define GCR_CDONE_IE (1<<19) /* Command done interrupt enable */
619 #define AC97_GSR 0x001c /* Global status register */
620 #define GSR_GSCI (1<<0) /* codec GPI status change interrupt */
621 #define GSR_MIINT (1<<1) /* modem in interrupt */
622 #define GSR_MOINT (1<<2) /* modem out interrupt */
623 #define GSR_PIINT (1<<5) /* PCM in interrupt */
624 #define GSR_POINT (1<<6) /* PCM out interrupt */
625 #define GSR_MINT (1<<7) /* Mic in interrupt */
626 #define GSR_PCR (1<<8) /* primary code ready */
627 #define GSR_SCR (1<<9) /* secondary code ready */
628 #define GSR_PRIRES (1<<10) /* primary resume interrupt */
629 #define GSR_SECRES (1<<11) /* secondary resume interrupt */
630 #define GSR_BIT1SLT12 (1<<12) /* Bit 1 of slot 12 */
631 #define GSR_BIT2SLT12 (1<<13) /* Bit 2 of slot 12 */
632 #define GSR_BIT3SLT12 (1<<14) /* Bit 3 of slot 12 */
633 #define GSR_RDCS (1<<15) /* Read completion status */
634 #define GSR_SDONE (1<<18) /* status done */
635 #define GSR_CDONE (1<<19) /* command done */
637 #define AC97_POCR 0x0000 /* PCM-out control */
638 #define AC97_PICR 0x0004 /* PCM-in control */
639 #define AC97_POSR 0x0010 /* PCM-out status */
640 #define AC97_PISR 0x0014 /* PCM-out status */
641 #define AC97_MCCR 0x0008 /* MIC-in control register */
642 #define AC97_MCSR 0x0018 /* MIC-in status register */
643 #define AC97_MICR 0x0100 /* Modem-in control register */
644 #define AC97_MISR 0x0108 /* Modem-in status register */
645 #define AC97_MOCR 0x0110 /* Modem-out control register */
646 #define AC97_MOSR 0x0118 /* Modem-out status register */
647 #define AC97_FEFIE (1<<3) /* fifo error interrupt enable */
648 #define AC97_FIFOE (1<<4) /* fifo error */
650 #define AC97_CAR 0x0020 /* Codec access register */
651 #define CAR_CAIP (1<<0) /* Codec access in progress */
653 #define AC97_PCDR 0x0040 /* PCM data register */
654 #define AC97_MCDR 0x0060 /* MIC-in data register */
655 #define AC97_MODR 0x0140 /* Modem data register */
657 /* address to access codec registers */
658 #define AC97_PRIAUDIO 0x0200 /* Primary audio codec */
659 #define AC97_SECAUDIO 0x0300 /* Secondary autio codec */
660 #define AC97_PRIMODEM 0x0400 /* Primary modem codec */
661 #define AC97_SECMODEM 0x0500 /* Secondary modem codec */
662 #define AC97_CODEC_BASE(c) (AC97_PRIAUDIO + ((c) * 0x100))
665 * USB device controller
667 #define USBDC_UDCCR 0x0000 /* UDC control register */
668 #define USBDC_UDCCS(n) (0x0010+4*(n)) /* Endpoint Control/Status Registers */
669 #define USBDC_UICR0 0x0050 /* UDC Interrupt Control Register 0 */
670 #define USBDC_UICR1 0x0054 /* UDC Interrupt Control Register 1 */
671 #define USBDC_USIR0 0x0058 /* UDC Status Interrupt Register 0 */
672 #define USBDC_USIR1 0x005C /* UDC Status Interrupt Register 1 */
673 #define USBDC_UFNHR 0x0060 /* UDC Frame Number Register High */
674 #define USBDC_UFNLR 0x0064 /* UDC Frame Number Register Low */
675 #define USBDC_UBCR2 0x0068 /* UDC Byte Count Register 2 */
676 #define USBDC_UBCR4 0x006C /* UDC Byte Count Register 4 */
677 #define USBDC_UBCR7 0x0070 /* UDC Byte Count Register 7 */
678 #define USBDC_UBCR9 0x0074 /* UDC Byte Count Register 9 */
679 #define USBDC_UBCR12 0x0078 /* UDC Byte Count Register 12 */
680 #define USBDC_UBCR14 0x007C /* UDC Byte Count Register 14 */
681 #define USBDC_UDDR0 0x0080 /* UDC Endpoint 0 Data Register */
682 #define USBDC_UDDR1 0x0100 /* UDC Endpoint 1 Data Register */
683 #define USBDC_UDDR2 0x0180 /* UDC Endpoint 2 Data Register */
684 #define USBDC_UDDR3 0x0200 /* UDC Endpoint 3 Data Register */
685 #define USBDC_UDDR4 0x0400 /* UDC Endpoint 4 Data Register */
686 #define USBDC_UDDR5 0x00A0 /* UDC Endpoint 5 Data Register */
687 #define USBDC_UDDR6 0x0600 /* UDC Endpoint 6 Data Register */
688 #define USBDC_UDDR7 0x0680 /* UDC Endpoint 7 Data Register */
689 #define USBDC_UDDR8 0x0700 /* UDC Endpoint 8 Data Register */
690 #define USBDC_UDDR9 0x0900 /* UDC Endpoint 9 Data Register */
691 #define USBDC_UDDR10 0x00C0 /* UDC Endpoint 10 Data Register */
692 #define USBDC_UDDR11 0x0B00 /* UDC Endpoint 11 Data Register */
693 #define USBDC_UDDR12 0x0B80 /* UDC Endpoint 12 Data Register */
694 #define USBDC_UDDR13 0x0C00 /* UDC Endpoint 13 Data Register */
695 #define USBDC_UDDR14 0x0E00 /* UDC Endpoint 14 Data Register */
696 #define USBDC_UDDR15 0x00E0 /* UDC Endpoint 15 Data Register */
698 #define USBHC_UHCRHDA 0x0048 /* UHC Root Hub Descriptor A */
699 #define UHCRHDA_POTPGT_SHIFT 24 /* Power on to power good time */
700 #define UHCRHDA_NOCP (1<<12) /* No over current protection */
701 #define UHCRHDA_OCPM (1<<11) /* Over current protection mode */
702 #define UHCRHDA_DT (1<<10) /* Device type */
703 #define UHCRHDA_NPS (1<<9) /* No power switching */
704 #define UHCRHDA_PSM (1<<8) /* Power switching mode */
705 #define UHCRHDA_NDP_MASK 0xff /* Number downstream ports */
706 #define USBHC_UHCRHDB 0x004c /* UHC Root Hub Descriptor B */
707 #define USBHC_UHCRHS 0x0050 /* UHC Root Hub Stauts */
708 #define USBHC_UHCHR 0x0064 /* UHC Reset Register */
709 #define UHCHR_SSEP3 (1<<11) /* Sleep standby enable for port3 */
710 #define UHCHR_SSEP2 (1<<10) /* Sleep standby enable for port2 */
711 #define UHCHR_SSEP1 (1<<9) /* Sleep standby enable for port1 */
712 #define UHCHR_PCPL (1<<7) /* Power control polarity low */
713 #define UHCHR_PSPL (1<<6) /* Power sense polarity low */
714 #define UHCHR_SSE (1<<5) /* Sleep standby enable */
715 #define UHCHR_UIT (1<<4) /* USB interrupt test */
716 #define UHCHR_SSDC (1<<3) /* Simulation scale down clock */
717 #define UHCHR_CGR (1<<2) /* Clock generation reset */
718 #define UHCHR_FHR (1<<1) /* Force host controller reset */
719 #define UHCHR_FSBIR (1<<0) /* Force system bus interface reset */
720 #define UHCHR_MASK 0xeff
725 #define PWM_PWMCR 0x0000 /* Control register */
726 #define PWM_PWMDCR 0x0004 /* Duty cycle register */
727 #define PWM_FD (1<<10) /* Full duty */
728 #define PWM_PWMPCR 0x0008 /* Period register */
733 #define OST_MR0 0x00 /* Match register 0 */
734 #define OST_MR1 0x04 /* Match register 1 */
735 #define OST_MR2 0x08 /* Match register 2 */
736 #define OST_MR3 0x0c /* Match register 3 */
737 #define OST_CR 0x10 /* Count register */
738 #define OST_SR 0x14 /* Status register */
739 #define OST_SR_CH0 (1<<0)
740 #define OST_SR_CH1 (1<<1)
741 #define OST_SR_CH2 (1<<2)
742 #define OST_SR_CH3 (1<<3)
743 #define OST_WR 0x18 /* Watchdog enable register */
744 #define OST_IR 0x1c /* Interrupt enable register */
747 * Interrupt controller
749 #define ICU_IP 0x00 /* IRQ pending register */
750 #define ICU_MR 0x04 /* Mask register */
751 #define ICU_LR 0x08 /* Level register */
752 #define ICU_FP 0x0c /* FIQ pending register */
753 #define ICU_PR 0x10 /* Pending register */
754 #define ICU_CR 0x14 /* Control register */
756 #endif /* _ARM_XSCALE_PXAREG_H_ */
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