sys/boot/fdt/dts/arm/exynos5.dtsi

   1 /*-
   2  * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 / {
  30         compatible = "samsung,exynos5";
  31         #address-cells = <1>;
  32         #size-cells = <1>;
  33         interrupt-parent = <&GIC>;
  34
  35         aliases {
  36                 soc = &SOC;
  37                 serial0 = &serial0;
  38                 serial1 = &serial1;
  39                 serial2 = &serial2;
  40                 serial3 = &serial3;
  41                 clk0 = &clk0;
  42                 dp0 = &dp0;
  43                 fimd0 = &fimd0;
  44         };
  45
  46         SOC: Exynos5@0 {
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49                 compatible = "simple-bus";
  50                 ranges;
  51                 bus-frequency = <0>;
  52
  53                 GIC: interrupt-controller@10481000 {
  54                         compatible = "arm,gic";
  55                         reg =   < 0x10481000 0x1000 >,  /* Distributor Registers */
  56                                 < 0x10482000 0x2000 >;  /* CPU Interface Registers */
  57                         interrupt-controller;
  58                         #address-cells = <0>;
  59                         #interrupt-cells = <1>;
  60                 };
  61
  62                 combiner: interrupt-controller@10440000 {
  63                         compatible = "exynos,combiner";
  64                         reg = <0x10440000 0x1000>;
  65                         interrupts = < 32 33 34 35 36 37 38 39
  66                                        40 41 42 43 44 45 46 47
  67                                        48 49 50 51 52 53 54 55
  68                                        56 57 58 59 60 61 62 63 >;
  69                         interrupt-parent = <&GIC>;
  70                 };
  71
  72                 clk0: clk@10010000 {
  73                         compatible = "exynos,clk";
  74                         reg = < 0x10020000 0x20000 >;
  75                 };
  76
  77                 mct {
  78                         compatible = "exynos,mct";
  79                         reg = < 0x101C0000 0x1000 >;
  80                         clock-frequency = <24000000>;
  81                 };
  82
  83                 generic_timer {
  84                         compatible = "arm,armv7-timer";
  85                         clock-frequency = <24000000>;
  86                         interrupts = < 29 30 27 26 >;
  87                         interrupt-parent = <&GIC>;
  88                 };
  89
  90                 pwm {
  91                         compatible = "samsung,s3c24x0-timer";
  92                         reg = <0x12DD0000 0x1000>;
  93                         interrupts = < 71 >;
  94                         interrupt-parent = <&GIC>;
  95                         clock-frequency = <24000000>;
  96                 };
  97
  98                 pad0: pad@11400000 {
  99                         compatible = "exynos,pad";
 100                         status = "disabled";
 101                         reg = <0x11400000 0x1000>, /* gpio left */
 102                               <0x13400000 0x1000>, /* gpio right */
 103                               <0x10D10000 0x1000>, /* gpio c2c */
 104                               <0x03860000 0x1000>;
 105                         interrupts = < 78 77 82 79 >;
 106                         interrupt-parent = <&GIC>;
 107                 };
 108
 109                 usb@12110000 {
 110                         compatible = "exynos,usb-ehci", "usb-ehci";
 111                         reg = <0x12110000 0x1000>, /* EHCI */
 112                               <0x12130000 0x1000>, /* EHCI host ctrl */
 113                               <0x10040000 0x1000>, /* Power */
 114                               <0x10050230 0x10>; /* Sysreg */
 115                         interrupts = < 103 >;
 116                         interrupt-parent = <&GIC>;
 117                 };
 118
 119                 usb@12120000 {
 120                         compatible = "exynos,usb-ohci", "usb-ohci";
 121                         status = "disabled";
 122                         reg = <0x12120000 0x10000>;
 123                         interrupts = < 103 >;
 124                         interrupt-parent = <&GIC>;
 125                 };
 126
 127                 sdhci@12200000 {
 128                         compatible = "sdhci_generic";
 129                         status = "disabled";
 130                         reg = <0x12200000 0x1000>;
 131                         interrupts = <107>;
 132                         interrupt-parent = <&GIC>;
 133                         max-frequency = <24000000>; /* TODO: verify freq */
 134                 };
 135
 136                 sdhci@12210000 {
 137                         compatible = "sdhci_generic";
 138                         status = "disabled";
 139                         reg = <0x12210000 0x1000>;
 140                         interrupts = <108>;
 141                         interrupt-parent = <&GIC>;
 142                         max-frequency = <24000000>;
 143                 };
 144
 145                 sdhci@12220000 {
 146                         compatible = "sdhci_generic";
 147                         status = "disabled";
 148                         reg = <0x12220000 0x1000>;
 149                         interrupts = <109>;
 150                         interrupt-parent = <&GIC>;
 151                         max-frequency = <24000000>;
 152                 };
 153
 154                 sdhci@12230000 {
 155                         compatible = "sdhci_generic";
 156                         status = "disabled";
 157                         reg = <0x12230000 0x1000>;
 158                         interrupts = <110>;
 159                         interrupt-parent = <&GIC>;
 160                         max-frequency = <24000000>;
 161                 };
 162
 163                 serial0: serial@12C00000 {
 164                         compatible = "exynos";
 165                         status = "disabled";
 166                         reg = <0x12C00000 0x100>;
 167                         interrupts = < 83 >;
 168                         interrupt-parent = <&GIC>;
 169                         clock-frequency = < 100000000 >;
 170                         current-speed = <115200>;
 171                 };
 172
 173                 serial1: serial@12C10000 {
 174                         compatible = "exynos";
 175                         status = "disabled";
 176                         reg = <0x12C10000 0x100>;
 177                         interrupts = < 84 >;
 178                         interrupt-parent = <&GIC>;
 179                         clock-frequency = < 100000000 >;
 180                         current-speed = <115200>;
 181                 };
 182
 183                 serial2: serial@12C20000 {
 184                         compatible = "exynos";
 185                         status = "disabled";
 186                         reg = <0x12C20000 0x100>;
 187                         interrupts = < 85 >;
 188                         interrupt-parent = <&GIC>;
 189                         clock-frequency = < 100000000 >;
 190                         current-speed = <115200>;
 191                 };
 192
 193                 serial3: serial@12C30000 {
 194                         compatible = "exynos";
 195                         status = "disabled";
 196                         reg = <0x12C30000 0x100>;
 197                         interrupts = < 86 >;
 198                         interrupt-parent = <&GIC>;
 199                         clock-frequency = < 100000000 >;
 200                         current-speed = <115200>;
 201                 };
 202
 203                 i2c0: i2c@12C60000 {
 204                         compatible = "exynos,i2c";
 205                         status = "disabled";
 206                         reg = <0x12C60000 0x10000>;
 207                         interrupts = < 88 >;
 208                         interrupt-parent = <&GIC>;
 209                 };
 210
 211                 i2c1: i2c@12C70000 {
 212                         compatible = "exynos,i2c";
 213                         status = "disabled";
 214                         reg = <0x12C70000 0x10000>;
 215                         interrupts = < 89 >;
 216                         interrupt-parent = <&GIC>;
 217                 };
 218
 219                 i2c2: i2c@12C80000 {
 220                         compatible = "exynos,i2c";
 221                         status = "disabled";
 222                         reg = <0x12C80000 0x10000>;
 223                         interrupts = < 90 >;
 224                         interrupt-parent = <&GIC>;
 225                 };
 226
 227                 i2c3: i2c@12C90000 {
 228                         compatible = "exynos,i2c";
 229                         status = "disabled";
 230                         reg = <0x12C90000 0x10000>;
 231                         interrupts = < 91 >;
 232                         interrupt-parent = <&GIC>;
 233                 };
 234
 235                 i2c4: i2c@12CA0000 {
 236                         compatible = "exynos,i2c";
 237                         status = "disabled";
 238                         reg = <0x12CA0000 0x10000>;
 239                         interrupts = < 92 >;
 240                         interrupt-parent = <&GIC>;
 241                 };
 242
 243                 i2c5: i2c@12CB0000 {
 244                         compatible = "exynos,i2c";
 245                         status = "disabled";
 246                         reg = <0x12CB0000 0x10000>;
 247                         interrupts = < 93 >;
 248                         interrupt-parent = <&GIC>;
 249                 };
 250
 251                 i2c6: i2c@12CC0000 {
 252                         compatible = "exynos,i2c";
 253                         status = "disabled";
 254                         reg = <0x12CC0000 0x10000>;
 255                         interrupts = < 94 >;
 256                         interrupt-parent = <&GIC>;
 257                 };
 258
 259                 i2c7: i2c@12CD0000 {
 260                         compatible = "exynos,i2c";
 261                         status = "disabled";
 262                         reg = <0x12CD0000 0x10000>;
 263                         interrupts = < 95 >;
 264                         interrupt-parent = <&GIC>;
 265                 };
 266
 267                 fimd0: fimd@14400000 {
 268                         compatible = "exynos,fimd";
 269                         status = "disabled";
 270                         reg = < 0x14400000 0x10000 >, /* fimd */
 271                               < 0x14420000 0x10000 >, /* disp */
 272                               < 0x10050000 0x220 >; /* sysreg */
 273                         interrupt-parent = <&GIC>;
 274                 };
 275
 276                 dp0: dp@145B0000 {
 277                         compatible = "exynos,dp";
 278                         status = "disabled";
 279                         reg = < 0x145B0000 0x10000 >,
 280                               < 0x10040720 0x10 >; /* PHY */
 281                         interrupt-parent = <&GIC>;
 282                 };
 283         };
 284 };