2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 compatible = "rockchip,rk3188";
34 interrupt-parent = <&GIC>;
43 compatible = "simple-bus";
47 GIC: interrupt-controller@1013d000 {
48 compatible = "arm,gic";
49 reg = <0x1013d000 0x1000>, /* Distributor Registers */
50 <0x1013c100 0x0100>; /* CPU Interface Registers */
52 #interrupt-cells = <1>;
56 compatible = "rockchip,rk30xx-pmu";
59 reg = <0x20004000 0x100>;
63 compatible = "rockchip,rk30xx-grf";
66 reg = < 0x20008000 0x2000 >;
70 compatible = "arm,mpcore-timers";
73 clock-frequency = < 148500000 >;
74 reg = <0x1013c200 0x100>, /* Global Timer Regs */
75 <0x1013c600 0x20>; /* Private Timer Regs */
76 interrupts = < 27 29 >;
77 interrupt-parent = <&GIC>;
81 compatible = "rockchip,rk30xx-timer";
82 reg = <0x20038000 0x20>;
84 clock-frequency = <24000000>;
89 compatible = "rockchip,rk30xx-timer";
90 reg = <0x20038020 0x20>;
92 clock-frequency = <24000000>;
97 compatible = "rockchip,rk30xx-timer";
98 reg = <0x20038060 0x20>;
100 clock-frequency = <24000000>;
105 compatible = "rockchip,rk30xx-timer";
106 reg = <0x20038080 0x20>;
108 clock-frequency = <24000000>;
113 compatible = "rockchip,rk30xx-timer";
114 reg = <0x200380a0 0x20>;
116 clock-frequency = <24000000>;
121 compatible = "rockchip,rk30xx-wdt";
122 reg = <0x2004c000 0x100>;
123 clock-frequency = < 66000000 >;
126 gpio0: gpio@2000a000 {
127 compatible = "rockchip,rk30xx-gpio";
130 reg = <0x2000a000 0x100>;
132 interrupt-parent = <&GIC>;
135 gpio1: gpio@2003c000 {
136 compatible = "rockchip,rk30xx-gpio";
139 reg = <0x2003c000 0x100>;
141 interrupt-parent = <&GIC>;
144 gpio2: gpio@2003e000 {
145 compatible = "rockchip,rk30xx-gpio";
148 reg = <0x2003e000 0x100>;
150 interrupt-parent = <&GIC>;
153 gpio3: gpio@20080000 {
154 compatible = "rockchip,rk30xx-gpio";
157 reg = <0x20080000 0x100>;
159 interrupt-parent = <&GIC>;
163 compatible = "synopsys,designware-hs-otg2";
164 reg = <0x10180000 0x40000>;
166 interrupt-parent = <&GIC>;
167 #address-cells = <1>;
172 compatible = "synopsys,designware-hs-otg2";
173 reg = <0x101c0000 0x40000>;
175 interrupt-parent = <&GIC>;
176 #address-cells = <1>;
178 gpios = <&gpio0 3 2 2>;
181 uart0: serial@10124000 {
182 compatible = "ns16550";
183 reg = <0x10124000 0x400>;
186 interrupt-parent = <&GIC>;
187 current-speed = <115200>;
188 clock-frequency = < 24000000 >;
194 uart1: serial@10126000 {
195 compatible = "ns16550";
196 reg = <0x10126000 0x400>;
199 interrupt-parent = <&GIC>;
200 current-speed = <115200>;
201 clock-frequency = < 24000000 >;
207 uart2: serial@20064000 {
208 compatible = "ns16550";
209 reg = <0x20064000 0x400>;
212 interrupt-parent = <&GIC>;
213 current-speed = <115200>;
214 clock-frequency = < 24000000 >;
220 uart3: serial@20068000 {
221 compatible = "ns16550";
222 reg = <0x20068000 0x400>;
225 interrupt-parent = <&GIC>;
226 current-speed = <115200>;
227 clock-frequency = < 24000000 >;
234 compatible = "rockchip,rk30xx-mmc";
235 reg = <0x10214000 0x1000>;
237 #address-cells = <1>;
239 clock-frequency = <24000000>; /* TODO: verify freq */
244 compatible = "rockchip,rk30xx-mmc";
245 reg = <0x10218000 0x1000>;
247 #address-cells = <1>;
249 clock-frequency = <24000000>; /* TODO: verify freq */