sys/boot/fdt/dts/arm/sheevaplug.dts

   1 /*
   2  * Copyright (c) 2010 The FreeBSD Foundation
   3  * All rights reserved.
   4  *
   5  * This software was developed by Semihalf under sponsorship from
   6  * the FreeBSD Foundation.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * Marvell SheevaPlug Device Tree Source.
  30  *
  31  * $FreeBSD$
  32  */
  33
  34 /dts-v1/;
  35
  36 / {
  37         model = "mrvl,SheevaPlug";
  38         compatible = "SheevaPlug";
  39         #address-cells = <1>;
  40         #size-cells = <1>;
  41
  42         aliases {
  43                 ethernet0 = &enet0;
  44                 mpp = &MPP;
  45                 serial0 = &serial0;
  46                 serial1 = &serial1;
  47                 soc = &SOC;
  48                 sram = &SRAM;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu@0 {
  56                         device_type = "cpu";
  57                         compatible = "ARM,88FR131";
  58                         reg = <0x0>;
  59                         d-cache-line-size = <32>;       // 32 bytes
  60                         i-cache-line-size = <32>;       // 32 bytes
  61                         d-cache-size = <0x4000>;        // L1, 16K
  62                         i-cache-size = <0x4000>;        // L1, 16K
  63                         timebase-frequency = <0>;
  64                         bus-frequency = <0>;
  65                         clock-frequency = <0>;
  66                 };
  67         };
  68
  69         memory {
  70                 device_type = "memory";
  71                 reg = <0x0 0x20000000>;         // 512M at 0x0
  72         };
  73
  74         localbus@0 {
  75                 #address-cells = <2>;
  76                 #size-cells = <1>;
  77                 compatible = "mrvl,lbc";
  78                 bank-count = <3>;
  79
  80                 /* This reflects CPU decode windows setup. */
  81                 ranges = <0x0 0x2f 0xf9300000 0x00100000>;
  82
  83                 nand@0,0 {
  84                         #address-cells = <1>;
  85                         #size-cells = <1>;
  86                         compatible = "mrvl,nfc";
  87                         reg = <0x0 0x0 0x00100000>;
  88                         bank-width = <2>;
  89                         device-width = <1>;
  90
  91                         slice@0 {
  92                                 reg = <0x0 0x200000>;
  93                                 label = "u-boot";
  94                                 read-only;
  95                         };
  96
  97                         slice@200000 {
  98                                 reg = <0x200000 0x1fe00000>;
  99                                 label = "root";
 100                         };
 101                 };
 102         };
 103
 104         SOC: soc88f6281@f1000000 {
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 compatible = "simple-bus";
 108                 ranges = <0x0 0xf1000000 0x00100000>;
 109                 bus-frequency = <0>;
 110
 111                 PIC: pic@20200 {
 112                         interrupt-controller;
 113                         #address-cells = <0>;
 114                         #interrupt-cells = <1>;
 115                         reg = <0x20200 0x3c>;
 116                         compatible = "mrvl,pic";
 117                 };
 118
 119                 timer@20300 {
 120                         compatible = "mrvl,timer";
 121                         reg = <0x20300 0x30>;
 122                         interrupts = <1>;
 123                         interrupt-parent = <&PIC>;
 124                         mrvl,has-wdt;
 125                 };
 126
 127                 MPP: mpp@10000 {
 128                         #pin-cells = <2>;
 129                         compatible = "mrvl,mpp";
 130                         reg = <0x10000 0x34>;
 131                         pin-count = <50>;
 132                         pin-map = <
 133                                 0  1            /* MPP[0]:  NF_IO[2] */
 134                                 1  1            /* MPP[1]:  NF_IO[3] */
 135                                 2  1            /* MPP[2]:  NF_IO[4] */
 136                                 3  1            /* MPP[3]:  NF_IO[5] */
 137                                 4  1            /* MPP[4]:  NF_IO[6] */
 138                                 5  1            /* MPP[5]:  NF_IO[7] */
 139                                 6  1            /* MPP[6]:  SYSRST_OUTn */
 140                                 8  2            /* MPP[8]:  UA0_RTS */
 141                                 9  2            /* MPP[9]:  UA0_CTS */
 142                                 10 3            /* MPP[10]: UA0_TXD */
 143                                 11 3            /* MPP[11]: UA0_RXD */
 144                                 12 1            /* MPP[12]: SD_CLK */
 145                                 13 1            /* MPP[13]: SD_CMD */
 146                                 14 1            /* MPP[14]: SD_D[0] */
 147                                 15 1            /* MPP[15]: SD_D[1] */
 148                                 16 1            /* MPP[16]: SD_D[2] */
 149                                 17 1            /* MPP[17]: SD_D[3] */
 150                                 18 1            /* MPP[18]: NF_IO[0] */
 151                                 19 1            /* MPP[19]: NF_IO[1] */
 152                                 29 1 >;         /* MPP[29]: TSMP[9] */
 153                 };
 154
 155                 GPIO: gpio@10100 {
 156                         #gpio-cells = <3>;
 157                         compatible = "mrvl,gpio";
 158                         reg = <0x10100 0x20>;
 159                         gpio-controller;
 160                         interrupts = <35 36 37 38 39 40 41>;
 161                         interrupt-parent = <&PIC>;
 162                 };
 163
 164                 rtc@10300 {
 165                         compatible = "mrvl,rtc";
 166                         reg = <0x10300 0x08>;
 167                 };
 168
 169                 twsi@11000 {
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                         compatible = "mrvl,twsi";
 173                         reg = <0x11000 0x20>;
 174                         interrupts = <43>;
 175                         interrupt-parent = <&PIC>;
 176                 };
 177
 178                 enet0: ethernet@72000 {
 179                         #address-cells = <1>;
 180                         #size-cells = <1>;
 181                         model = "V2";
 182                         compatible = "mrvl,ge";
 183                         reg = <0x72000 0x2000>;
 184                         ranges = <0x0 0x72000 0x2000>;
 185                         local-mac-address = [ 00 00 00 00 00 00 ];
 186                         interrupts = <12 13 14 11 46>;
 187                         interrupt-parent = <&PIC>;
 188                         phy-handle = <&phy0>;
 189
 190                         mdio@0 {
 191                                 #address-cells = <1>;
 192                                 #size-cells = <0>;
 193                                 compatible = "mrvl,mdio";
 194
 195                                 phy0: ethernet-phy@0 {
 196                                         reg = <0x0>;
 197                                 };
 198                         };
 199                 };
 200
 201                 serial0: serial@12000 {
 202                         compatible = "ns16550";
 203                         reg = <0x12000 0x20>;
 204                         reg-shift = <2>;
 205                         clock-frequency = <0>;
 206                         interrupts = <33>;
 207                         interrupt-parent = <&PIC>;
 208                 };
 209
 210                 serial1: serial@12100 {
 211                         compatible = "ns16550";
 212                         reg = <0x12100 0x20>;
 213                         reg-shift = <2>;
 214                         clock-frequency = <0>;
 215                         interrupts = <34>;
 216                         interrupt-parent = <&PIC>;
 217                 };
 218
 219                 crypto@30000 {
 220                         compatible = "mrvl,cesa";
 221                         reg = <0x30000 0x10000>;
 222                         interrupts = <22>;
 223                         interrupt-parent = <&PIC>;
 224
 225                         sram-handle = <&SRAM>;
 226                 };
 227
 228                 usb@50000 {
 229                         compatible = "mrvl,usb-ehci", "usb-ehci";
 230                         reg = <0x50000 0x1000>;
 231                         interrupts = <48 19>;
 232                         interrupt-parent = <&PIC>;
 233                 };
 234
 235                 xor@60000 {
 236                         compatible = "mrvl,xor";
 237                         reg = <0x60000 0x1000>;
 238                         interrupts = <5 6 7 8>;
 239                         interrupt-parent = <&PIC>;
 240                 };
 241         };
 242
 243         SRAM: sram@fd000000 {
 244                 compatible = "mrvl,cesa-sram";
 245                 reg = <0xfd000000 0x00100000>;
 246         };
 247
 248         chosen {
 249                 stdin = "serial0";
 250                 stdout = "serial0";
 251         };
 252 };