sys/boot/fdt/dts/arm/versatilepb.dts

   1 /*
   2  * $FreeBSD$
   3  */
   4 /dts-v1/;
   5
   6 / {
   7         model = "ARM Versatile PB";
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10         compatible = "arm,versatile-pb";
  11
  12         amba {
  13                 compatible = "simple-bus";
  14                 #address-cells = <1>;
  15                 #size-cells = <1>;
  16                 ranges;
  17
  18                 intc: interrupt-controller {
  19                         compatible = "arm,versatile-vic";
  20                         reg = <0x10140000 0x1000>;
  21
  22                         interrupt-controller;
  23                         #interrupt-cells = <1>;
  24                 };
  25
  26                 sic: secondary-interrupt-controller {
  27                         compatible = "arm,versatile-sic";
  28                         reg = <0x10003000 0x28>;
  29
  30                         interrupt-controller;
  31                         #interrupt-cells = <1>;
  32                 };
  33
  34                 uart0: uart0 {
  35                         compatible = "arm,pl011", "arm,primecell";
  36                         reg = <0x101f1000 0x1000>;
  37                         interrupts = <12>;
  38                         interrupt-parent = <&intc>;
  39                         clock-frequency = <3000000>;
  40                         reg-shift = <2>;
  41                 };
  42
  43                 uart1: uart1 {
  44                         compatible = "arm,pl011", "arm,primecell";
  45                         reg = <0x101f2000 0x1000>;
  46                         interrupts = <13>;
  47                         interrupt-parent = <&intc>;
  48                         clock-frequency = <3000000>;
  49                         reg-shift = <2>;
  50                 };
  51
  52                 uart2: uart2 {
  53                         compatible = "arm,pl011", "arm,primecell";
  54                         reg = <0x101f3000 0x1000>;
  55                         interrupts = <14>;
  56                         interrupt-parent = <&intc>;
  57                         clock-frequency = <3000000>;
  58                         reg-shift = <2>;
  59                 };
  60
  61                 timer0 {
  62                         compatible = "arm,sp804", "arm,primecell";
  63                         reg = <0x101e2000 0x40>;
  64                         interrupts = <4>;
  65                         interrupt-parent = <&intc>;
  66                 };
  67
  68                 pci0 {
  69
  70                         compatible = "versatile,pci";
  71                         reg = <0x10000044 0x4
  72                                 0x10001000 0x1000
  73                                 0x41000000 0x01000000
  74                                 0x42000000 0x02000000>;
  75                 };
  76
  77                 net {
  78                         compatible = "smsc,lan91c111";
  79                         reg = <0x10010000 0x10000>;
  80                         interrupts = <25>;
  81                         interrupt-parent = <&intc>;
  82                 };
  83
  84                 display {
  85                         compatible = "arm,pl110", "arm,primecell";
  86                         reg = <0x10000050 4
  87                                 0x10120000 0x1000>;
  88                         interrupts = <16>;
  89                         interrupt-parent = <&intc>;
  90                 };
  91
  92                 /*
  93                  * Cut corner here: we do not have proper interrupt
  94                  * controllers cascading so just hardwire SIC IRQ 3
  95                  * to VIC IRQ31
  96                  */
  97                 kmi {
  98                         compatible = "arm,pl050", "arm,primecell";
  99                         reg = <0x10006000 0x1000>;
 100                         interrupt-parent = <&intc>;
 101                         interrupts = <31>;
 102                 };
 103         };
 104
 105         memory {
 106                 device_type = "memory";
 107                 reg = <0 0x08000000>; /* 128MB */
 108         };
 109
 110         aliases {
 111                 uart0 = &uart0;
 112         };
 113
 114         chosen {
 115                 stdin = "uart0";
 116                 stdout = "uart0";
 117         };
 118 };